2 * (C) Copyright 2015 Google, Inc
4 * (C) Copyright 2008-2014 Rockchip Electronics
5 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/errno.h>
17 #include <asm/arch/clock.h>
18 #include <dm/pinctrl.h>
19 #include <dt-bindings/gpio/gpio.h>
20 #include <dt-bindings/clock/rk3288-cru.h>
23 ROCKCHIP_GPIOS_PER_BANK
= 32,
26 #define OFFSET_TO_BIT(bit) (1UL << (bit))
28 struct rockchip_gpio_priv
{
29 struct rockchip_gpio_regs
*regs
;
30 struct udevice
*pinctrl
;
35 static int rockchip_gpio_direction_input(struct udevice
*dev
, unsigned offset
)
37 struct rockchip_gpio_priv
*priv
= dev_get_priv(dev
);
38 struct rockchip_gpio_regs
*regs
= priv
->regs
;
40 clrbits_le32(®s
->swport_ddr
, OFFSET_TO_BIT(offset
));
45 static int rockchip_gpio_direction_output(struct udevice
*dev
, unsigned offset
,
48 struct rockchip_gpio_priv
*priv
= dev_get_priv(dev
);
49 struct rockchip_gpio_regs
*regs
= priv
->regs
;
50 int mask
= OFFSET_TO_BIT(offset
);
52 clrsetbits_le32(®s
->swport_dr
, mask
, value
? mask
: 0);
53 setbits_le32(®s
->swport_ddr
, mask
);
58 static int rockchip_gpio_get_value(struct udevice
*dev
, unsigned offset
)
60 struct rockchip_gpio_priv
*priv
= dev_get_priv(dev
);
61 struct rockchip_gpio_regs
*regs
= priv
->regs
;
63 return readl(®s
->ext_port
) & OFFSET_TO_BIT(offset
) ? 1 : 0;
66 static int rockchip_gpio_set_value(struct udevice
*dev
, unsigned offset
,
69 struct rockchip_gpio_priv
*priv
= dev_get_priv(dev
);
70 struct rockchip_gpio_regs
*regs
= priv
->regs
;
71 int mask
= OFFSET_TO_BIT(offset
);
73 clrsetbits_le32(®s
->swport_dr
, mask
, value
? mask
: 0);
78 static int rockchip_gpio_get_function(struct udevice
*dev
, unsigned offset
)
80 #ifdef CONFIG_SPL_BUILD
83 struct rockchip_gpio_priv
*priv
= dev_get_priv(dev
);
84 struct rockchip_gpio_regs
*regs
= priv
->regs
;
88 ret
= pinctrl_get_gpio_mux(priv
->pinctrl
, priv
->bank
, offset
);
92 /* If it's not 0, then it is not a GPIO */
95 is_output
= readl(®s
->swport_ddr
) & OFFSET_TO_BIT(offset
);
97 return is_output
? GPIOF_OUTPUT
: GPIOF_INPUT
;
101 static int rockchip_gpio_xlate(struct udevice
*dev
, struct gpio_desc
*desc
,
102 struct fdtdec_phandle_args
*args
)
104 desc
->offset
= args
->args
[0];
105 desc
->flags
= args
->args
[1] & GPIO_ACTIVE_LOW
? GPIOD_ACTIVE_LOW
: 0;
110 static int rockchip_gpio_probe(struct udevice
*dev
)
112 struct gpio_dev_priv
*uc_priv
= dev_get_uclass_priv(dev
);
113 struct rockchip_gpio_priv
*priv
= dev_get_priv(dev
);
117 /* This only supports RK3288 at present */
118 priv
->regs
= (struct rockchip_gpio_regs
*)dev_get_addr(dev
);
119 ret
= uclass_first_device(UCLASS_PINCTRL
, &priv
->pinctrl
);
125 uc_priv
->gpio_count
= ROCKCHIP_GPIOS_PER_BANK
;
126 end
= strrchr(dev
->name
, '@');
127 priv
->bank
= trailing_strtoln(dev
->name
, end
);
128 priv
->name
[0] = 'A' + priv
->bank
;
129 uc_priv
->bank_name
= priv
->name
;
134 static const struct dm_gpio_ops gpio_rockchip_ops
= {
135 .direction_input
= rockchip_gpio_direction_input
,
136 .direction_output
= rockchip_gpio_direction_output
,
137 .get_value
= rockchip_gpio_get_value
,
138 .set_value
= rockchip_gpio_set_value
,
139 .get_function
= rockchip_gpio_get_function
,
140 .xlate
= rockchip_gpio_xlate
,
143 static const struct udevice_id rockchip_gpio_ids
[] = {
144 { .compatible
= "rockchip,gpio-bank" },
148 U_BOOT_DRIVER(gpio_rockchip
) = {
149 .name
= "gpio_rockchip",
151 .of_match
= rockchip_gpio_ids
,
152 .ops
= &gpio_rockchip_ops
,
153 .priv_auto_alloc_size
= sizeof(struct rockchip_gpio_priv
),
154 .probe
= rockchip_gpio_probe
,