2 * NVIDIA Tegra20 GPIO handling.
3 * (C) Copyright 2010-2012
4 * NVIDIA Corporation <www.nvidia.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
11 * Tom Warren (twarren@nvidia.com)
20 #include <asm/bitops.h>
21 #include <asm/arch/tegra.h>
23 #include <dm/device-internal.h>
25 DECLARE_GLOBAL_DATA_PTR
;
34 struct tegra_gpio_platdata
{
35 struct gpio_ctlr_bank
*bank
;
36 const char *port_name
; /* Name of port, e.g. "B" */
37 int base_gpio
; /* Port number for this port (0, 1,.., n-1) */
40 /* Information about each port at run-time */
41 struct tegra_port_info
{
42 struct gpio_ctlr_bank
*bank
;
43 int base_gpio
; /* Port number for this port (0, 1,.., n-1) */
46 /* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */
47 static int get_config(unsigned gpio
)
49 struct gpio_ctlr
*ctlr
= (struct gpio_ctlr
*)NV_PA_GPIO_BASE
;
50 struct gpio_ctlr_bank
*bank
= &ctlr
->gpio_bank
[GPIO_BANK(gpio
)];
54 u
= readl(&bank
->gpio_config
[GPIO_PORT(gpio
)]);
55 type
= (u
>> GPIO_BIT(gpio
)) & 1;
57 debug("get_config: port = %d, bit = %d is %s\n",
58 GPIO_FULLPORT(gpio
), GPIO_BIT(gpio
), type
? "GPIO" : "SFPIO");
63 /* Config pin 'gpio' as GPIO or SFPIO, based on 'type' */
64 static void set_config(unsigned gpio
, int type
)
66 struct gpio_ctlr
*ctlr
= (struct gpio_ctlr
*)NV_PA_GPIO_BASE
;
67 struct gpio_ctlr_bank
*bank
= &ctlr
->gpio_bank
[GPIO_BANK(gpio
)];
70 debug("set_config: port = %d, bit = %d, %s\n",
71 GPIO_FULLPORT(gpio
), GPIO_BIT(gpio
), type
? "GPIO" : "SFPIO");
73 u
= readl(&bank
->gpio_config
[GPIO_PORT(gpio
)]);
75 u
|= 1 << GPIO_BIT(gpio
);
77 u
&= ~(1 << GPIO_BIT(gpio
));
78 writel(u
, &bank
->gpio_config
[GPIO_PORT(gpio
)]);
81 /* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
82 static int get_direction(unsigned gpio
)
84 struct gpio_ctlr
*ctlr
= (struct gpio_ctlr
*)NV_PA_GPIO_BASE
;
85 struct gpio_ctlr_bank
*bank
= &ctlr
->gpio_bank
[GPIO_BANK(gpio
)];
89 u
= readl(&bank
->gpio_dir_out
[GPIO_PORT(gpio
)]);
90 dir
= (u
>> GPIO_BIT(gpio
)) & 1;
92 debug("get_direction: port = %d, bit = %d, %s\n",
93 GPIO_FULLPORT(gpio
), GPIO_BIT(gpio
), dir
? "OUT" : "IN");
98 /* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
99 static void set_direction(unsigned gpio
, int output
)
101 struct gpio_ctlr
*ctlr
= (struct gpio_ctlr
*)NV_PA_GPIO_BASE
;
102 struct gpio_ctlr_bank
*bank
= &ctlr
->gpio_bank
[GPIO_BANK(gpio
)];
105 debug("set_direction: port = %d, bit = %d, %s\n",
106 GPIO_FULLPORT(gpio
), GPIO_BIT(gpio
), output
? "OUT" : "IN");
108 u
= readl(&bank
->gpio_dir_out
[GPIO_PORT(gpio
)]);
110 u
|= 1 << GPIO_BIT(gpio
);
112 u
&= ~(1 << GPIO_BIT(gpio
));
113 writel(u
, &bank
->gpio_dir_out
[GPIO_PORT(gpio
)]);
116 /* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
117 static void set_level(unsigned gpio
, int high
)
119 struct gpio_ctlr
*ctlr
= (struct gpio_ctlr
*)NV_PA_GPIO_BASE
;
120 struct gpio_ctlr_bank
*bank
= &ctlr
->gpio_bank
[GPIO_BANK(gpio
)];
123 debug("set_level: port = %d, bit %d == %d\n",
124 GPIO_FULLPORT(gpio
), GPIO_BIT(gpio
), high
);
126 u
= readl(&bank
->gpio_out
[GPIO_PORT(gpio
)]);
128 u
|= 1 << GPIO_BIT(gpio
);
130 u
&= ~(1 << GPIO_BIT(gpio
));
131 writel(u
, &bank
->gpio_out
[GPIO_PORT(gpio
)]);
134 /* set GPIO pin 'gpio' as an output, with polarity 'value' */
135 int tegra_spl_gpio_direction_output(int gpio
, int value
)
137 /* Configure as a GPIO */
140 /* Configure GPIO output value. */
141 set_level(gpio
, value
);
143 /* Configure GPIO direction as output. */
144 set_direction(gpio
, 1);
150 * Generic_GPIO primitives.
153 static int tegra_gpio_request(struct udevice
*dev
, unsigned offset
,
156 struct tegra_port_info
*state
= dev_get_priv(dev
);
158 /* Configure as a GPIO */
159 set_config(state
->base_gpio
+ offset
, 1);
164 /* set GPIO pin 'gpio' as an input */
165 static int tegra_gpio_direction_input(struct udevice
*dev
, unsigned offset
)
167 struct tegra_port_info
*state
= dev_get_priv(dev
);
169 /* Configure GPIO direction as input. */
170 set_direction(state
->base_gpio
+ offset
, 0);
175 /* set GPIO pin 'gpio' as an output, with polarity 'value' */
176 static int tegra_gpio_direction_output(struct udevice
*dev
, unsigned offset
,
179 struct tegra_port_info
*state
= dev_get_priv(dev
);
180 int gpio
= state
->base_gpio
+ offset
;
182 /* Configure GPIO output value. */
183 set_level(gpio
, value
);
185 /* Configure GPIO direction as output. */
186 set_direction(gpio
, 1);
191 /* read GPIO IN value of pin 'gpio' */
192 static int tegra_gpio_get_value(struct udevice
*dev
, unsigned offset
)
194 struct tegra_port_info
*state
= dev_get_priv(dev
);
195 int gpio
= state
->base_gpio
+ offset
;
198 debug("%s: pin = %d (port %d:bit %d)\n", __func__
,
199 gpio
, GPIO_FULLPORT(gpio
), GPIO_BIT(gpio
));
201 val
= readl(&state
->bank
->gpio_in
[GPIO_PORT(gpio
)]);
203 return (val
>> GPIO_BIT(gpio
)) & 1;
206 /* write GPIO OUT value to pin 'gpio' */
207 static int tegra_gpio_set_value(struct udevice
*dev
, unsigned offset
, int value
)
209 struct tegra_port_info
*state
= dev_get_priv(dev
);
210 int gpio
= state
->base_gpio
+ offset
;
212 debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
213 gpio
, GPIO_FULLPORT(gpio
), GPIO_BIT(gpio
), value
);
215 /* Configure GPIO output value. */
216 set_level(gpio
, value
);
221 void gpio_config_table(const struct tegra_gpio_config
*config
, int len
)
225 for (i
= 0; i
< len
; i
++) {
226 switch (config
[i
].init
) {
227 case TEGRA_GPIO_INIT_IN
:
228 gpio_direction_input(config
[i
].gpio
);
230 case TEGRA_GPIO_INIT_OUT0
:
231 gpio_direction_output(config
[i
].gpio
, 0);
233 case TEGRA_GPIO_INIT_OUT1
:
234 gpio_direction_output(config
[i
].gpio
, 1);
237 set_config(config
[i
].gpio
, 1);
241 static int tegra_gpio_get_function(struct udevice
*dev
, unsigned offset
)
243 struct tegra_port_info
*state
= dev_get_priv(dev
);
244 int gpio
= state
->base_gpio
+ offset
;
246 if (!get_config(gpio
))
248 else if (get_direction(gpio
))
254 static const struct dm_gpio_ops gpio_tegra_ops
= {
255 .request
= tegra_gpio_request
,
256 .direction_input
= tegra_gpio_direction_input
,
257 .direction_output
= tegra_gpio_direction_output
,
258 .get_value
= tegra_gpio_get_value
,
259 .set_value
= tegra_gpio_set_value
,
260 .get_function
= tegra_gpio_get_function
,
264 * Returns the name of a GPIO port
266 * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ...
268 * @base_port: Base port number (0, 1..n-1)
269 * @return allocated string containing the name
271 static char *gpio_port_name(int base_port
)
278 *s
++ = 'A' + (base_port
% 26);
287 static const struct udevice_id tegra_gpio_ids
[] = {
288 { .compatible
= "nvidia,tegra30-gpio" },
289 { .compatible
= "nvidia,tegra20-gpio" },
293 static int gpio_tegra_probe(struct udevice
*dev
)
295 struct gpio_dev_priv
*uc_priv
= dev
->uclass_priv
;
296 struct tegra_port_info
*priv
= dev
->priv
;
297 struct tegra_gpio_platdata
*plat
= dev
->platdata
;
299 /* Only child devices have ports */
303 priv
->bank
= plat
->bank
;
304 priv
->base_gpio
= plat
->base_gpio
;
306 uc_priv
->gpio_count
= TEGRA_GPIOS_PER_PORT
;
307 uc_priv
->bank_name
= plat
->port_name
;
313 * We have a top-level GPIO device with no actual GPIOs. It has a child
314 * device for each Tegra port.
316 static int gpio_tegra_bind(struct udevice
*parent
)
318 struct tegra_gpio_platdata
*plat
= parent
->platdata
;
319 struct gpio_ctlr
*ctlr
;
325 /* If this is a child device, there is nothing to do here */
330 * This driver does not make use of interrupts, other than to figure
331 * out the number of GPIO banks
333 if (!fdt_getprop(gd
->fdt_blob
, parent
->of_offset
, "interrupts", &len
))
335 bank_count
= len
/ 3 / sizeof(u32
);
336 ctlr
= (struct gpio_ctlr
*)fdtdec_get_addr(gd
->fdt_blob
,
337 parent
->of_offset
, "reg");
338 for (bank
= 0; bank
< bank_count
; bank
++) {
341 for (port
= 0; port
< TEGRA_PORTS_PER_BANK
; port
++) {
342 struct tegra_gpio_platdata
*plat
;
346 plat
= calloc(1, sizeof(*plat
));
349 plat
->bank
= &ctlr
->gpio_bank
[bank
];
350 base_port
= bank
* TEGRA_PORTS_PER_BANK
+ port
;
351 plat
->base_gpio
= TEGRA_GPIOS_PER_PORT
* base_port
;
352 plat
->port_name
= gpio_port_name(base_port
);
354 ret
= device_bind(parent
, parent
->driver
,
355 plat
->port_name
, plat
, -1, &dev
);
358 dev
->of_offset
= parent
->of_offset
;
365 U_BOOT_DRIVER(gpio_tegra
) = {
366 .name
= "gpio_tegra",
368 .of_match
= tegra_gpio_ids
,
369 .bind
= gpio_tegra_bind
,
370 .probe
= gpio_tegra_probe
,
371 .priv_auto_alloc_size
= sizeof(struct tegra_port_info
),
372 .ops
= &gpio_tegra_ops
,