2 * Copyright 2016 Freescale Semiconductors, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/imx_lpi2c.h>
13 #include <asm/arch/sys_proto.h>
18 DECLARE_GLOBAL_DATA_PTR
;
19 #define LPI2C_FIFO_SIZE 4
20 #define LPI2C_TIMEOUT_MS 100
22 /* Weak linked function for overridden by some SoC power function */
23 int __weak
init_i2c_power(unsigned i2c_num
)
28 static int imx_lpci2c_check_busy_bus(struct udevice
*bus
)
30 struct imx_lpi2c_reg
*regs
= (struct imx_lpi2c_reg
*)dev_get_addr(bus
);
31 lpi2c_status_t result
= LPI2C_SUCESS
;
34 status
= readl(®s
->msr
);
36 if ((status
& LPI2C_MSR_BBF_MASK
) && !(status
& LPI2C_MSR_MBF_MASK
))
42 static int imx_lpci2c_check_clear_error(struct udevice
*bus
)
44 struct imx_lpi2c_reg
*regs
= (struct imx_lpi2c_reg
*)dev_get_addr(bus
);
45 lpi2c_status_t result
= LPI2C_SUCESS
;
48 status
= readl(®s
->msr
);
49 /* errors to check for */
50 status
&= LPI2C_MSR_NDF_MASK
| LPI2C_MSR_ALF_MASK
|
51 LPI2C_MSR_FEF_MASK
| LPI2C_MSR_PLTF_MASK
;
54 if (status
& LPI2C_MSR_PLTF_MASK
)
55 result
= LPI2C_PIN_LOW_TIMEOUT_ERR
;
56 else if (status
& LPI2C_MSR_ALF_MASK
)
57 result
= LPI2C_ARB_LOST_ERR
;
58 else if (status
& LPI2C_MSR_NDF_MASK
)
59 result
= LPI2C_NAK_ERR
;
60 else if (status
& LPI2C_MSR_FEF_MASK
)
61 result
= LPI2C_FIFO_ERR
;
63 /* clear status flags */
64 writel(0x7f00, ®s
->msr
);
66 val
= readl(®s
->mcr
);
67 val
|= LPI2C_MCR_RRF_MASK
| LPI2C_MCR_RTF_MASK
;
68 writel(val
, ®s
->mcr
);
74 static int bus_i2c_wait_for_tx_ready(struct udevice
*bus
)
76 struct imx_lpi2c_reg
*regs
= (struct imx_lpi2c_reg
*)dev_get_addr(bus
);
77 lpi2c_status_t result
= LPI2C_SUCESS
;
79 ulong start_time
= get_timer(0);
82 txcount
= LPI2C_MFSR_TXCOUNT(readl(®s
->mfsr
));
83 txcount
= LPI2C_FIFO_SIZE
- txcount
;
84 result
= imx_lpci2c_check_clear_error(bus
);
86 debug("i2c: wait for tx ready: result 0x%x\n", result
);
89 if (get_timer(start_time
) > LPI2C_TIMEOUT_MS
) {
90 debug("i2c: wait for tx ready: timeout\n");
98 static int bus_i2c_send(struct udevice
*bus
, u8
*txbuf
, int len
)
100 struct imx_lpi2c_reg
*regs
= (struct imx_lpi2c_reg
*)dev_get_addr(bus
);
101 lpi2c_status_t result
= LPI2C_SUCESS
;
108 result
= bus_i2c_wait_for_tx_ready(bus
);
110 debug("i2c: send wait fot tx ready: %d\n", result
);
113 writel(*txbuf
++, ®s
->mtdr
);
119 static int bus_i2c_receive(struct udevice
*bus
, u8
*rxbuf
, int len
)
121 struct imx_lpi2c_reg
*regs
= (struct imx_lpi2c_reg
*)dev_get_addr(bus
);
122 lpi2c_status_t result
= LPI2C_SUCESS
;
124 ulong start_time
= get_timer(0);
130 result
= bus_i2c_wait_for_tx_ready(bus
);
132 debug("i2c: receive wait fot tx ready: %d\n", result
);
136 /* clear all status flags */
137 writel(0x7f00, ®s
->msr
);
138 /* send receive command */
139 val
= LPI2C_MTDR_CMD(0x1) | LPI2C_MTDR_DATA(len
- 1);
140 writel(val
, ®s
->mtdr
);
144 result
= imx_lpci2c_check_clear_error(bus
);
146 debug("i2c: receive check clear error: %d\n", result
);
149 if (get_timer(start_time
) > LPI2C_TIMEOUT_MS
) {
150 debug("i2c: receive mrdr: timeout\n");
153 val
= readl(®s
->mrdr
);
154 } while (val
& LPI2C_MRDR_RXEMPTY_MASK
);
155 *rxbuf
++ = LPI2C_MRDR_DATA(val
);
161 static int bus_i2c_start(struct udevice
*bus
, u8 addr
, u8 dir
)
163 struct imx_lpi2c_reg
*regs
= (struct imx_lpi2c_reg
*)dev_get_addr(bus
);
164 lpi2c_status_t result
= LPI2C_SUCESS
;
167 result
= imx_lpci2c_check_busy_bus(bus
);
169 debug("i2c: start check busy bus: 0x%x\n", result
);
172 /* clear all status flags */
173 writel(0x7f00, ®s
->msr
);
174 /* turn off auto-stop condition */
175 val
= readl(®s
->mcfgr1
) & ~LPI2C_MCFGR1_AUTOSTOP_MASK
;
176 writel(val
, ®s
->mcfgr1
);
177 /* wait tx fifo ready */
178 result
= bus_i2c_wait_for_tx_ready(bus
);
180 debug("i2c: start wait for tx ready: 0x%x\n", result
);
183 /* issue start command */
184 val
= LPI2C_MTDR_CMD(0x4) | (addr
<< 0x1) | dir
;
185 writel(val
, ®s
->mtdr
);
189 static int bus_i2c_stop(struct udevice
*bus
)
191 struct imx_lpi2c_reg
*regs
= (struct imx_lpi2c_reg
*)dev_get_addr(bus
);
192 lpi2c_status_t result
= LPI2C_SUCESS
;
195 result
= bus_i2c_wait_for_tx_ready(bus
);
197 debug("i2c: stop wait for tx ready: 0x%x\n", result
);
201 /* send stop command */
202 writel(LPI2C_MTDR_CMD(0x2), ®s
->mtdr
);
204 while (result
== LPI2C_SUCESS
) {
205 status
= readl(®s
->msr
);
206 result
= imx_lpci2c_check_clear_error(bus
);
207 /* stop detect flag */
208 if (status
& LPI2C_MSR_SDF_MASK
) {
209 /* clear stop flag */
210 status
&= LPI2C_MSR_SDF_MASK
;
211 writel(status
, ®s
->msr
);
219 static int bus_i2c_read(struct udevice
*bus
, u32 chip
, u8
*buf
, int len
)
221 lpi2c_status_t result
= LPI2C_SUCESS
;
223 result
= bus_i2c_start(bus
, chip
, 1);
226 result
= bus_i2c_receive(bus
, buf
, len
);
229 result
= bus_i2c_stop(bus
);
236 static int bus_i2c_write(struct udevice
*bus
, u32 chip
, u8
*buf
, int len
)
238 lpi2c_status_t result
= LPI2C_SUCESS
;
240 result
= bus_i2c_start(bus
, chip
, 0);
243 result
= bus_i2c_send(bus
, buf
, len
);
246 result
= bus_i2c_stop(bus
);
254 static int bus_i2c_set_bus_speed(struct udevice
*bus
, int speed
)
256 struct imx_lpi2c_reg
*regs
= (struct imx_lpi2c_reg
*)dev_get_addr(bus
);
258 u32 preescale
= 0, best_pre
= 0, clkhi
= 0;
259 u32 best_clkhi
= 0, abs_error
= 0, rate
;
260 u32 error
= 0xffffffff;
265 clock_rate
= imx_get_i2cclk(bus
->seq
+ 4);
269 mode
= (readl(®s
->mcr
) & LPI2C_MCR_MEN_MASK
) >> LPI2C_MCR_MEN_SHIFT
;
270 /* disable master mode */
271 val
= readl(®s
->mcr
) & ~LPI2C_MCR_MEN_MASK
;
272 writel(val
| LPI2C_MCR_MEN(0), ®s
->mcr
);
274 for (preescale
= 1; (preescale
<= 128) &&
275 (error
!= 0); preescale
= 2 * preescale
) {
276 for (clkhi
= 1; clkhi
< 32; clkhi
++) {
278 rate
= (clock_rate
/ preescale
) / (1 + 3 + 2 + 2 / preescale
);
280 rate
= (clock_rate
/ preescale
/ (3 * clkhi
+ 2 + 2 / preescale
));
282 abs_error
= speed
> rate
? speed
- rate
: rate
- speed
;
284 if (abs_error
< error
) {
285 best_pre
= preescale
;
294 /* Standard, fast, fast mode plus and ultra-fast transfers. */
295 val
= LPI2C_MCCR0_CLKHI(best_clkhi
);
297 val
|= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | LPI2C_MCCR0_DATAVD(1);
299 val
|= LPI2C_MCCR0_CLKLO(2 * best_clkhi
) | LPI2C_MCCR0_SETHOLD(best_clkhi
) |
300 LPI2C_MCCR0_DATAVD(best_clkhi
/ 2);
301 writel(val
, ®s
->mccr0
);
303 for (i
= 0; i
< 8; i
++) {
304 if (best_pre
== (1 << i
)) {
310 val
= readl(®s
->mcfgr1
) & ~LPI2C_MCFGR1_PRESCALE_MASK
;
311 writel(val
| LPI2C_MCFGR1_PRESCALE(best_pre
), ®s
->mcfgr1
);
314 val
= readl(®s
->mcr
) & ~LPI2C_MCR_MEN_MASK
;
315 writel(val
| LPI2C_MCR_MEN(1), ®s
->mcr
);
321 static int bus_i2c_init(struct udevice
*bus
, int speed
)
323 struct imx_lpi2c_reg
*regs
= (struct imx_lpi2c_reg
*)dev_get_addr(bus
);
327 /* reset peripheral */
328 writel(LPI2C_MCR_RST_MASK
, ®s
->mcr
);
329 writel(0x0, ®s
->mcr
);
330 /* Disable Dozen mode */
331 writel(LPI2C_MCR_DBGEN(0) | LPI2C_MCR_DOZEN(1), ®s
->mcr
);
332 /* host request disable, active high, external pin */
333 val
= readl(®s
->mcfgr0
);
334 val
&= (~(LPI2C_MCFGR0_HREN_MASK
| LPI2C_MCFGR0_HRPOL_MASK
|
335 LPI2C_MCFGR0_HRSEL_MASK
));
336 val
|= LPI2C_MCFGR0_HRPOL(0x1);
337 writel(val
, ®s
->mcfgr0
);
338 /* pincfg and ignore ack */
339 val
= readl(®s
->mcfgr1
);
340 val
&= ~(LPI2C_MCFGR1_PINCFG_MASK
| LPI2C_MCFGR1_IGNACK_MASK
);
341 val
|= LPI2C_MCFGR1_PINCFG(0x0); /* 2 pin open drain */
342 val
|= LPI2C_MCFGR1_IGNACK(0x0); /* ignore nack */
343 writel(val
, ®s
->mcfgr1
);
345 ret
= bus_i2c_set_bus_speed(bus
, speed
);
347 /* enable lpi2c in master mode */
348 val
= readl(®s
->mcr
) & ~LPI2C_MCR_MEN_MASK
;
349 writel(val
| LPI2C_MCR_MEN(1), ®s
->mcr
);
351 debug("i2c : controller bus %d, speed %d:\n", bus
->seq
, speed
);
356 static int imx_lpi2c_probe_chip(struct udevice
*bus
, u32 chip
,
359 lpi2c_status_t result
= LPI2C_SUCESS
;
361 result
= bus_i2c_start(bus
, chip
, 0);
364 bus_i2c_init(bus
, 100000);
368 result
= bus_i2c_stop(bus
);
370 bus_i2c_init(bus
, 100000);
377 static int imx_lpi2c_xfer(struct udevice
*bus
, struct i2c_msg
*msg
, int nmsgs
)
381 for (; nmsgs
> 0; nmsgs
--, msg
++) {
382 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg
->addr
, msg
->len
);
383 if (msg
->flags
& I2C_M_RD
)
384 ret
= bus_i2c_read(bus
, msg
->addr
, msg
->buf
,
387 ret
= bus_i2c_write(bus
, msg
->addr
, msg
->buf
,
395 debug("i2c_write: error sending\n");
400 static int imx_lpi2c_set_bus_speed(struct udevice
*bus
, unsigned int speed
)
402 return bus_i2c_set_bus_speed(bus
, speed
);
405 static int imx_lpi2c_probe(struct udevice
*bus
)
407 struct imx_lpi2c_bus
*i2c_bus
= dev_get_priv(bus
);
411 i2c_bus
->driver_data
= dev_get_driver_data(bus
);
413 addr
= dev_get_addr(bus
);
414 if (addr
== FDT_ADDR_T_NONE
)
417 i2c_bus
->base
= addr
;
418 i2c_bus
->index
= bus
->seq
;
421 /* power up i2c resource */
422 ret
= init_i2c_power(bus
->seq
+ 4);
424 debug("init_i2c_power err = %d\n", ret
);
428 /* Enable clk, only i2c4-7 can be handled by A7 core */
429 ret
= enable_i2c_clk(1, bus
->seq
+ 4);
433 ret
= bus_i2c_init(bus
, 100000);
437 debug("i2c : controller bus %d at %lu , speed %d: ",
438 bus
->seq
, i2c_bus
->base
,
444 static const struct dm_i2c_ops imx_lpi2c_ops
= {
445 .xfer
= imx_lpi2c_xfer
,
446 .probe_chip
= imx_lpi2c_probe_chip
,
447 .set_bus_speed
= imx_lpi2c_set_bus_speed
,
450 static const struct udevice_id imx_lpi2c_ids
[] = {
451 { .compatible
= "fsl,imx7ulp-lpi2c", },
455 U_BOOT_DRIVER(imx_lpi2c
) = {
458 .of_match
= imx_lpi2c_ids
,
459 .probe
= imx_lpi2c_probe
,
460 .priv_auto_alloc_size
= sizeof(struct imx_lpi2c_bus
),
461 .ops
= &imx_lpi2c_ops
,