]>
git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/misc/mxc_ocotp.c
2 * (C) Copyright 2013 ADVANSEE
3 * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
5 * Based on Dirk Behme's
6 * https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
7 * which is based on Freescale's
8 * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
10 * Copyright (C) 2011 Freescale Semiconductor, Inc.
12 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/errno.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/imx-regs.h>
22 #define BO_CTRL_WR_UNLOCK 16
23 #define BM_CTRL_WR_UNLOCK 0xffff0000
24 #define BV_CTRL_WR_UNLOCK_KEY 0x3e77
25 #define BM_CTRL_ERROR 0x00000200
26 #define BM_CTRL_BUSY 0x00000100
27 #define BO_CTRL_ADDR 0
29 #define BM_CTRL_ADDR 0x0000000f
30 #define BM_CTRL_RELOAD 0x00000400
32 #define BM_CTRL_ADDR 0x0000007f
36 #define BO_TIMING_FSOURCE 12
37 #define BM_TIMING_FSOURCE 0x0007f000
38 #define BV_TIMING_FSOURCE_NS 1001
39 #define BO_TIMING_PROG 0
40 #define BM_TIMING_PROG 0x00000fff
41 #define BV_TIMING_PROG_US 10
43 #define BO_TIMING_STROBE_READ 16
44 #define BM_TIMING_STROBE_READ 0x003f0000
45 #define BV_TIMING_STROBE_READ_NS 37
46 #define BO_TIMING_RELAX 12
47 #define BM_TIMING_RELAX 0x0000f000
48 #define BV_TIMING_RELAX_NS 17
49 #define BO_TIMING_STROBE_PROG 0
50 #define BM_TIMING_STROBE_PROG 0x00000fff
51 #define BV_TIMING_STROBE_PROG_US 10
54 #define BM_READ_CTRL_READ_FUSE 0x00000001
56 #define BF(value, field) (((value) << BO_##field) & BM_##field)
58 #define WRITE_POSTAMBLE_US 2
60 #if defined(CONFIG_MX6) || defined(CONFIG_VF610)
61 #define FUSE_BANK_SIZE 0x80
67 #elif defined CONFIG_MX7
68 #define FUSE_BANK_SIZE 0x40
71 #error "Unsupported architecture\n"
74 #if defined(CONFIG_MX6)
75 #include <asm/arch/sys_proto.h>
78 * There is a hole in shadow registers address map of size 0x100
79 * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL.
80 * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses,
81 * we should account for this hole in address space.
83 * Similar hole exists between bank 14 and bank 15 of size
84 * 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX.
85 * Note: iMX6SL has only 0-7 banks and there is no hole.
86 * Note: iMX6UL doesn't have this one.
88 * This function is to covert user input to physical bank index.
89 * Only needed when read fuse, because we use register offset, so
90 * need to calculate real register offset.
91 * When write, no need to consider hole, always use the bank/word
92 * index from fuse map.
94 u32
fuse_bank_physical(int index
)
100 } else if (is_mx6ul()) {
102 phy_index
= fuse_bank_physical(5) + (index
- 6) + 3;
107 phy_index
= fuse_bank_physical(14) + (index
- 15) + 2;
109 phy_index
= fuse_bank_physical(5) + (index
- 6) + 3;
116 u32
fuse_bank_physical(int index
)
122 static void wait_busy(struct ocotp_regs
*regs
, unsigned int delay_us
)
124 while (readl(®s
->ctrl
) & BM_CTRL_BUSY
)
128 static void clear_error(struct ocotp_regs
*regs
)
130 writel(BM_CTRL_ERROR
, ®s
->ctrl_clr
);
133 static int prepare_access(struct ocotp_regs
**regs
, u32 bank
, u32 word
,
134 int assert, const char *caller
)
136 *regs
= (struct ocotp_regs
*)OCOTP_BASE_ADDR
;
138 if (bank
>= FUSE_BANKS
||
139 word
>= ARRAY_SIZE((*regs
)->bank
[0].fuse_regs
) >> 2 ||
141 printf("mxc_ocotp %s(): Invalid argument\n", caller
);
153 static int finish_access(struct ocotp_regs
*regs
, const char *caller
)
157 err
= !!(readl(®s
->ctrl
) & BM_CTRL_ERROR
);
161 printf("mxc_ocotp %s(): Access protect error\n", caller
);
168 static int prepare_read(struct ocotp_regs
**regs
, u32 bank
, u32 word
, u32
*val
,
171 return prepare_access(regs
, bank
, word
, val
!= NULL
, caller
);
174 int fuse_read(u32 bank
, u32 word
, u32
*val
)
176 struct ocotp_regs
*regs
;
180 ret
= prepare_read(®s
, bank
, word
, val
, __func__
);
184 phy_bank
= fuse_bank_physical(bank
);
186 *val
= readl(®s
->bank
[phy_bank
].fuse_regs
[word
<< 2]);
188 return finish_access(regs
, __func__
);
192 static void set_timing(struct ocotp_regs
*regs
)
198 ipg_clk
= mxc_get_clock(MXC_IPG_CLK
);
200 fsource
= DIV_ROUND_UP((ipg_clk
/ 1000) * BV_TIMING_FSOURCE_NS
,
202 prog
= DIV_ROUND_CLOSEST(ipg_clk
* BV_TIMING_PROG_US
, 1000000) + 1;
204 timing
= BF(fsource
, TIMING_FSOURCE
) | BF(prog
, TIMING_PROG
);
206 clrsetbits_le32(®s
->timing
, BM_TIMING_FSOURCE
| BM_TIMING_PROG
,
210 static void set_timing(struct ocotp_regs
*regs
)
213 u32 relax
, strobe_read
, strobe_prog
;
216 ipg_clk
= mxc_get_clock(MXC_IPG_CLK
);
218 relax
= DIV_ROUND_UP(ipg_clk
* BV_TIMING_RELAX_NS
, 1000000000) - 1;
219 strobe_read
= DIV_ROUND_UP(ipg_clk
* BV_TIMING_STROBE_READ_NS
,
220 1000000000) + 2 * (relax
+ 1) - 1;
221 strobe_prog
= DIV_ROUND_CLOSEST(ipg_clk
* BV_TIMING_STROBE_PROG_US
,
222 1000000) + 2 * (relax
+ 1) - 1;
224 timing
= BF(strobe_read
, TIMING_STROBE_READ
) |
225 BF(relax
, TIMING_RELAX
) |
226 BF(strobe_prog
, TIMING_STROBE_PROG
);
228 clrsetbits_le32(®s
->timing
, BM_TIMING_STROBE_READ
| BM_TIMING_RELAX
|
229 BM_TIMING_STROBE_PROG
, timing
);
233 static void setup_direct_access(struct ocotp_regs
*regs
, u32 bank
, u32 word
,
236 u32 wr_unlock
= write
? BV_CTRL_WR_UNLOCK_KEY
: 0;
240 u32 addr
= bank
<< 3 | word
;
244 clrsetbits_le32(®s
->ctrl
, BM_CTRL_WR_UNLOCK
| BM_CTRL_ADDR
,
245 BF(wr_unlock
, CTRL_WR_UNLOCK
) |
246 BF(addr
, CTRL_ADDR
));
249 int fuse_sense(u32 bank
, u32 word
, u32
*val
)
251 struct ocotp_regs
*regs
;
254 ret
= prepare_read(®s
, bank
, word
, val
, __func__
);
258 setup_direct_access(regs
, bank
, word
, false);
259 writel(BM_READ_CTRL_READ_FUSE
, ®s
->read_ctrl
);
262 *val
= readl((®s
->read_fuse_data0
) + (word
<< 2));
264 *val
= readl(®s
->read_fuse_data
);
267 return finish_access(regs
, __func__
);
270 static int prepare_write(struct ocotp_regs
**regs
, u32 bank
, u32 word
,
273 return prepare_access(regs
, bank
, word
, true, caller
);
276 int fuse_prog(u32 bank
, u32 word
, u32 val
)
278 struct ocotp_regs
*regs
;
281 ret
= prepare_write(®s
, bank
, word
, __func__
);
285 setup_direct_access(regs
, bank
, word
, true);
289 writel(0, ®s
->data1
);
290 writel(0, ®s
->data2
);
291 writel(0, ®s
->data3
);
292 writel(val
, ®s
->data0
);
295 writel(val
, ®s
->data1
);
296 writel(0, ®s
->data2
);
297 writel(0, ®s
->data3
);
298 writel(0, ®s
->data0
);
301 writel(0, ®s
->data1
);
302 writel(val
, ®s
->data2
);
303 writel(0, ®s
->data3
);
304 writel(0, ®s
->data0
);
307 writel(0, ®s
->data1
);
308 writel(0, ®s
->data2
);
309 writel(val
, ®s
->data3
);
310 writel(0, ®s
->data0
);
313 wait_busy(regs
, BV_TIMING_PROG_US
);
315 writel(val
, ®s
->data
);
316 wait_busy(regs
, BV_TIMING_STROBE_PROG_US
);
318 udelay(WRITE_POSTAMBLE_US
);
320 return finish_access(regs
, __func__
);
323 int fuse_override(u32 bank
, u32 word
, u32 val
)
325 struct ocotp_regs
*regs
;
329 ret
= prepare_write(®s
, bank
, word
, __func__
);
333 phy_bank
= fuse_bank_physical(bank
);
335 writel(val
, ®s
->bank
[phy_bank
].fuse_regs
[word
<< 2]);
337 return finish_access(regs
, __func__
);