2 * ARM PrimeCell MultiMedia Card Interface - PL180
4 * Copyright (C) ST-Ericsson SA 2010
6 * Author: Ulf Hansson <ulf.hansson@stericsson.com>
7 * Author: Martin Lundholm <martin.xa.lundholm@stericsson.com>
8 * Ported to drivers/mmc/ by: Matt Waddel <matt.waddel@linaro.org>
10 * SPDX-License-Identifier: GPL-2.0+
20 #include "arm_pl180_mmci.h"
26 DECLARE_GLOBAL_DATA_PTR
;
28 #define MMC_CLOCK_MAX 48000000
29 #define MMC_CLOCK_MIN 400000
31 struct arm_pl180_mmc_plat
{
32 struct mmc_config cfg
;
37 static int wait_for_command_end(struct mmc
*dev
, struct mmc_cmd
*cmd
)
39 u32 hoststatus
, statusmask
;
40 struct pl180_mmc_host
*host
= dev
->priv
;
42 statusmask
= SDI_STA_CTIMEOUT
| SDI_STA_CCRCFAIL
;
43 if ((cmd
->resp_type
& MMC_RSP_PRESENT
))
44 statusmask
|= SDI_STA_CMDREND
;
46 statusmask
|= SDI_STA_CMDSENT
;
49 hoststatus
= readl(&host
->base
->status
) & statusmask
;
52 writel(statusmask
, &host
->base
->status_clear
);
53 if (hoststatus
& SDI_STA_CTIMEOUT
) {
54 debug("CMD%d time out\n", cmd
->cmdidx
);
56 } else if ((hoststatus
& SDI_STA_CCRCFAIL
) &&
57 (cmd
->resp_type
& MMC_RSP_CRC
)) {
58 printf("CMD%d CRC error\n", cmd
->cmdidx
);
62 if (cmd
->resp_type
& MMC_RSP_PRESENT
) {
63 cmd
->response
[0] = readl(&host
->base
->response0
);
64 cmd
->response
[1] = readl(&host
->base
->response1
);
65 cmd
->response
[2] = readl(&host
->base
->response2
);
66 cmd
->response
[3] = readl(&host
->base
->response3
);
67 debug("CMD%d response[0]:0x%08X, response[1]:0x%08X, "
68 "response[2]:0x%08X, response[3]:0x%08X\n",
69 cmd
->cmdidx
, cmd
->response
[0], cmd
->response
[1],
70 cmd
->response
[2], cmd
->response
[3]);
76 /* send command to the mmc card and wait for results */
77 static int do_command(struct mmc
*dev
, struct mmc_cmd
*cmd
)
81 struct pl180_mmc_host
*host
= dev
->priv
;
83 sdi_cmd
= ((cmd
->cmdidx
& SDI_CMD_CMDINDEX_MASK
) | SDI_CMD_CPSMEN
);
86 sdi_cmd
|= SDI_CMD_WAITRESP
;
87 if (cmd
->resp_type
& MMC_RSP_136
)
88 sdi_cmd
|= SDI_CMD_LONGRESP
;
91 writel((u32
)cmd
->cmdarg
, &host
->base
->argument
);
92 udelay(COMMAND_REG_DELAY
);
93 writel(sdi_cmd
, &host
->base
->command
);
94 result
= wait_for_command_end(dev
, cmd
);
96 /* After CMD2 set RCA to a none zero value. */
97 if ((result
== 0) && (cmd
->cmdidx
== MMC_CMD_ALL_SEND_CID
))
100 /* After CMD3 open drain is switched off and push pull is used. */
101 if ((result
== 0) && (cmd
->cmdidx
== MMC_CMD_SET_RELATIVE_ADDR
)) {
102 u32 sdi_pwr
= readl(&host
->base
->power
) & ~SDI_PWR_OPD
;
103 writel(sdi_pwr
, &host
->base
->power
);
109 static int read_bytes(struct mmc
*dev
, u32
*dest
, u32 blkcount
, u32 blksize
)
111 u32
*tempbuff
= dest
;
112 u64 xfercount
= blkcount
* blksize
;
113 struct pl180_mmc_host
*host
= dev
->priv
;
114 u32 status
, status_err
;
116 debug("read_bytes: blkcount=%u blksize=%u\n", blkcount
, blksize
);
118 status
= readl(&host
->base
->status
);
119 status_err
= status
& (SDI_STA_DCRCFAIL
| SDI_STA_DTIMEOUT
|
121 while ((!status_err
) && (xfercount
>= sizeof(u32
))) {
122 if (status
& SDI_STA_RXDAVL
) {
123 *(tempbuff
) = readl(&host
->base
->fifo
);
125 xfercount
-= sizeof(u32
);
127 status
= readl(&host
->base
->status
);
128 status_err
= status
& (SDI_STA_DCRCFAIL
| SDI_STA_DTIMEOUT
|
132 status_err
= status
&
133 (SDI_STA_DCRCFAIL
| SDI_STA_DTIMEOUT
| SDI_STA_DBCKEND
|
135 while (!status_err
) {
136 status
= readl(&host
->base
->status
);
137 status_err
= status
&
138 (SDI_STA_DCRCFAIL
| SDI_STA_DTIMEOUT
| SDI_STA_DBCKEND
|
142 if (status
& SDI_STA_DTIMEOUT
) {
143 printf("Read data timed out, xfercount: %llu, status: 0x%08X\n",
146 } else if (status
& SDI_STA_DCRCFAIL
) {
147 printf("Read data bytes CRC error: 0x%x\n", status
);
149 } else if (status
& SDI_STA_RXOVERR
) {
150 printf("Read data RX overflow error\n");
154 writel(SDI_ICR_MASK
, &host
->base
->status_clear
);
157 printf("Read data error, xfercount: %llu\n", xfercount
);
164 static int write_bytes(struct mmc
*dev
, u32
*src
, u32 blkcount
, u32 blksize
)
168 u64 xfercount
= blkcount
* blksize
;
169 struct pl180_mmc_host
*host
= dev
->priv
;
170 u32 status
, status_err
;
172 debug("write_bytes: blkcount=%u blksize=%u\n", blkcount
, blksize
);
174 status
= readl(&host
->base
->status
);
175 status_err
= status
& (SDI_STA_DCRCFAIL
| SDI_STA_DTIMEOUT
);
176 while (!status_err
&& xfercount
) {
177 if (status
& SDI_STA_TXFIFOBW
) {
178 if (xfercount
>= SDI_FIFO_BURST_SIZE
* sizeof(u32
)) {
179 for (i
= 0; i
< SDI_FIFO_BURST_SIZE
; i
++)
180 writel(*(tempbuff
+ i
),
182 tempbuff
+= SDI_FIFO_BURST_SIZE
;
183 xfercount
-= SDI_FIFO_BURST_SIZE
* sizeof(u32
);
185 while (xfercount
>= sizeof(u32
)) {
186 writel(*(tempbuff
), &host
->base
->fifo
);
188 xfercount
-= sizeof(u32
);
192 status
= readl(&host
->base
->status
);
193 status_err
= status
& (SDI_STA_DCRCFAIL
| SDI_STA_DTIMEOUT
);
196 status_err
= status
&
197 (SDI_STA_DCRCFAIL
| SDI_STA_DTIMEOUT
| SDI_STA_DBCKEND
);
198 while (!status_err
) {
199 status
= readl(&host
->base
->status
);
200 status_err
= status
&
201 (SDI_STA_DCRCFAIL
| SDI_STA_DTIMEOUT
| SDI_STA_DBCKEND
);
204 if (status
& SDI_STA_DTIMEOUT
) {
205 printf("Write data timed out, xfercount:%llu,status:0x%08X\n",
208 } else if (status
& SDI_STA_DCRCFAIL
) {
209 printf("Write data CRC error\n");
213 writel(SDI_ICR_MASK
, &host
->base
->status_clear
);
216 printf("Write data error, xfercount:%llu", xfercount
);
223 static int do_data_transfer(struct mmc
*dev
,
225 struct mmc_data
*data
)
227 int error
= -ETIMEDOUT
;
228 struct pl180_mmc_host
*host
= dev
->priv
;
231 u32 data_len
= (u32
) (data
->blocks
* data
->blocksize
);
233 if (!host
->version2
) {
234 blksz
= (ffs(data
->blocksize
) - 1);
235 data_ctrl
|= ((blksz
<< 4) & SDI_DCTRL_DBLKSIZE_MASK
);
237 blksz
= data
->blocksize
;
238 data_ctrl
|= (blksz
<< SDI_DCTRL_DBLOCKSIZE_V2_SHIFT
);
240 data_ctrl
|= SDI_DCTRL_DTEN
| SDI_DCTRL_BUSYMODE
;
242 writel(SDI_DTIMER_DEFAULT
, &host
->base
->datatimer
);
243 writel(data_len
, &host
->base
->datalength
);
244 udelay(DATA_REG_DELAY
);
246 if (data
->flags
& MMC_DATA_READ
) {
247 data_ctrl
|= SDI_DCTRL_DTDIR_IN
;
248 writel(data_ctrl
, &host
->base
->datactrl
);
250 error
= do_command(dev
, cmd
);
254 error
= read_bytes(dev
, (u32
*)data
->dest
, (u32
)data
->blocks
,
255 (u32
)data
->blocksize
);
256 } else if (data
->flags
& MMC_DATA_WRITE
) {
257 error
= do_command(dev
, cmd
);
261 writel(data_ctrl
, &host
->base
->datactrl
);
262 error
= write_bytes(dev
, (u32
*)data
->src
, (u32
)data
->blocks
,
263 (u32
)data
->blocksize
);
269 static int host_request(struct mmc
*dev
,
271 struct mmc_data
*data
)
276 result
= do_data_transfer(dev
, cmd
, data
);
278 result
= do_command(dev
, cmd
);
283 static int host_set_ios(struct mmc
*dev
)
285 struct pl180_mmc_host
*host
= dev
->priv
;
288 sdi_clkcr
= readl(&host
->base
->clock
);
290 /* Ramp up the clock rate */
295 if (dev
->clock
>= dev
->cfg
->f_max
) {
297 dev
->clock
= dev
->cfg
->f_max
;
299 clkdiv
= (host
->clock_in
/ dev
->clock
) - 2;
302 tmp_clock
= host
->clock_in
/ (clkdiv
+ 2);
303 while (tmp_clock
> dev
->clock
) {
305 tmp_clock
= host
->clock_in
/ (clkdiv
+ 2);
308 if (clkdiv
> SDI_CLKCR_CLKDIV_MASK
)
309 clkdiv
= SDI_CLKCR_CLKDIV_MASK
;
311 tmp_clock
= host
->clock_in
/ (clkdiv
+ 2);
312 dev
->clock
= tmp_clock
;
313 sdi_clkcr
&= ~(SDI_CLKCR_CLKDIV_MASK
);
317 /* Set the bus width */
318 if (dev
->bus_width
) {
321 switch (dev
->bus_width
) {
323 buswidth
|= SDI_CLKCR_WIDBUS_1
;
326 buswidth
|= SDI_CLKCR_WIDBUS_4
;
329 buswidth
|= SDI_CLKCR_WIDBUS_8
;
332 printf("Invalid bus width: %d\n", dev
->bus_width
);
335 sdi_clkcr
&= ~(SDI_CLKCR_WIDBUS_MASK
);
336 sdi_clkcr
|= buswidth
;
339 writel(sdi_clkcr
, &host
->base
->clock
);
340 udelay(CLK_CHANGE_DELAY
);
345 #ifndef CONFIG_DM_MMC
346 /* MMC uses open drain drivers in the enumeration phase */
347 static int mmc_host_reset(struct mmc
*dev
)
349 struct pl180_mmc_host
*host
= dev
->priv
;
351 writel(host
->pwr_init
, &host
->base
->power
);
356 static const struct mmc_ops arm_pl180_mmci_ops
= {
357 .send_cmd
= host_request
,
358 .set_ios
= host_set_ios
,
359 .init
= mmc_host_reset
,
364 * mmc_host_init - initialize the mmc controller.
365 * Set initial clock and power for mmc slot.
366 * Initialize mmc struct and register with mmc framework.
368 int arm_pl180_mmci_init(struct pl180_mmc_host
*host
, struct mmc
**mmc
)
372 writel(host
->pwr_init
, &host
->base
->power
);
373 writel(host
->clkdiv_init
, &host
->base
->clock
);
374 udelay(CLK_CHANGE_DELAY
);
376 /* Disable mmc interrupts */
377 sdi_u32
= readl(&host
->base
->mask0
) & ~SDI_MASK0_MASK
;
378 writel(sdi_u32
, &host
->base
->mask0
);
380 host
->cfg
.name
= host
->name
;
381 #ifndef CONFIG_DM_MMC
382 host
->cfg
.ops
= &arm_pl180_mmci_ops
;
384 /* TODO remove the duplicates */
385 host
->cfg
.host_caps
= host
->caps
;
386 host
->cfg
.voltages
= host
->voltages
;
387 host
->cfg
.f_min
= host
->clock_min
;
388 host
->cfg
.f_max
= host
->clock_max
;
389 if (host
->b_max
!= 0)
390 host
->cfg
.b_max
= host
->b_max
;
392 host
->cfg
.b_max
= CONFIG_SYS_MMC_MAX_BLK_COUNT
;
394 *mmc
= mmc_create(&host
->cfg
, host
);
398 debug("registered mmc interface number is:%d\n",
399 (*mmc
)->block_dev
.devnum
);
405 static int arm_pl180_mmc_probe(struct udevice
*dev
)
407 struct arm_pl180_mmc_plat
*pdata
= dev_get_platdata(dev
);
408 struct mmc_uclass_priv
*upriv
= dev_get_uclass_priv(dev
);
409 struct mmc
*mmc
= &pdata
->mmc
;
410 struct pl180_mmc_host
*host
= mmc
->priv
;
414 strcpy(host
->name
, "MMC");
415 host
->pwr_init
= INIT_PWR
;
416 host
->clkdiv_init
= SDI_CLKCR_CLKDIV_INIT_V1
| SDI_CLKCR_CLKEN
|
418 host
->voltages
= VOLTAGE_WINDOW_SD
;
420 host
->clock_in
= MMC_CLOCK_MAX
;
421 host
->clock_min
= MMC_CLOCK_MIN
;
422 host
->clock_max
= dev_read_u32_default(dev
, "max-frequency",
424 host
->version2
= dev_get_driver_data(dev
);
426 bus_width
= dev_read_u32_default(dev
, "bus-width", 1);
429 host
->caps
|= MMC_MODE_8BIT
;
430 /* Hosts capable of 8-bit transfers can also do 4 bits */
432 host
->caps
|= MMC_MODE_4BIT
;
437 dev_err(dev
, "Invalid bus-width value %u\n", bus_width
);
440 ret
= arm_pl180_mmci_init(host
, &mmc
);
442 dev_err(dev
, "arm_pl180_mmci init failed\n");
453 static int dm_host_request(struct udevice
*dev
, struct mmc_cmd
*cmd
,
454 struct mmc_data
*data
)
456 struct mmc
*mmc
= mmc_get_mmc_dev(dev
);
458 return host_request(mmc
, cmd
, data
);
461 static int dm_host_set_ios(struct udevice
*dev
)
463 struct mmc
*mmc
= mmc_get_mmc_dev(dev
);
465 return host_set_ios(mmc
);
468 static const struct dm_mmc_ops arm_pl180_dm_mmc_ops
= {
469 .send_cmd
= dm_host_request
,
470 .set_ios
= dm_host_set_ios
,
473 static int arm_pl180_mmc_ofdata_to_platdata(struct udevice
*dev
)
475 struct arm_pl180_mmc_plat
*pdata
= dev_get_platdata(dev
);
476 struct mmc
*mmc
= &pdata
->mmc
;
477 struct pl180_mmc_host
*host
= mmc
->priv
;
480 addr
= devfdt_get_addr(dev
);
481 if (addr
== FDT_ADDR_T_NONE
)
484 host
->base
= (void *)addr
;
489 static const struct udevice_id arm_pl180_mmc_match
[] = {
490 { .compatible
= "st,stm32f4xx-sdio", .data
= VERSION1
},
494 U_BOOT_DRIVER(arm_pl180_mmc
) = {
495 .name
= "arm_pl180_mmc",
497 .of_match
= arm_pl180_mmc_match
,
498 .ops
= &arm_pl180_dm_mmc_ops
,
499 .probe
= arm_pl180_mmc_probe
,
500 .ofdata_to_platdata
= arm_pl180_mmc_ofdata_to_platdata
,
501 .priv_auto_alloc_size
= sizeof(struct pl180_mmc_host
),
502 .platdata_auto_alloc_size
= sizeof(struct arm_pl180_mmc_plat
),