2 * Freescale i.MX28 SSP MMC driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
11 * Copyright 2007, Freescale Semiconductor, Inc
14 * Based vaguely on the pxa mmc code:
16 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
18 * SPDX-License-Identifier: GPL-2.0+
23 #include <linux/errno.h>
25 #include <asm/arch/clock.h>
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/mach-imx/dma.h>
29 #include <bouncebuf.h>
33 struct mxs_ssp_regs
*regs
;
35 int (*mmc_is_wp
)(int);
37 struct mxs_dma_desc
*desc
;
38 struct mmc_config cfg
; /* mmc configuration */
41 #define MXSMMC_MAX_TIMEOUT 10000
42 #define MXSMMC_SMALL_TRANSFER 512
44 static int mxsmmc_cd(struct mxsmmc_priv
*priv
)
46 struct mxs_ssp_regs
*ssp_regs
= priv
->regs
;
49 return priv
->mmc_cd(priv
->id
);
51 return !(readl(&ssp_regs
->hw_ssp_status
) & SSP_STATUS_CARD_DETECT
);
54 static int mxsmmc_send_cmd_pio(struct mxsmmc_priv
*priv
, struct mmc_data
*data
)
56 struct mxs_ssp_regs
*ssp_regs
= priv
->regs
;
58 int timeout
= MXSMMC_MAX_TIMEOUT
;
60 uint32_t data_count
= data
->blocksize
* data
->blocks
;
62 if (data
->flags
& MMC_DATA_READ
) {
63 data_ptr
= (uint32_t *)data
->dest
;
64 while (data_count
&& --timeout
) {
65 reg
= readl(&ssp_regs
->hw_ssp_status
);
66 if (!(reg
& SSP_STATUS_FIFO_EMPTY
)) {
67 *data_ptr
++ = readl(&ssp_regs
->hw_ssp_data
);
69 timeout
= MXSMMC_MAX_TIMEOUT
;
74 data_ptr
= (uint32_t *)data
->src
;
76 while (data_count
&& --timeout
) {
77 reg
= readl(&ssp_regs
->hw_ssp_status
);
78 if (!(reg
& SSP_STATUS_FIFO_FULL
)) {
79 writel(*data_ptr
++, &ssp_regs
->hw_ssp_data
);
81 timeout
= MXSMMC_MAX_TIMEOUT
;
87 return timeout
? 0 : -ECOMM
;
90 static int mxsmmc_send_cmd_dma(struct mxsmmc_priv
*priv
, struct mmc_data
*data
)
92 uint32_t data_count
= data
->blocksize
* data
->blocks
;
94 struct mxs_dma_desc
*desc
= priv
->desc
;
97 struct bounce_buffer bbstate
;
99 memset(desc
, 0, sizeof(struct mxs_dma_desc
));
100 desc
->address
= (dma_addr_t
)desc
;
102 if (data
->flags
& MMC_DATA_READ
) {
103 priv
->desc
->cmd
.data
= MXS_DMA_DESC_COMMAND_DMA_WRITE
;
105 flags
= GEN_BB_WRITE
;
107 priv
->desc
->cmd
.data
= MXS_DMA_DESC_COMMAND_DMA_READ
;
108 addr
= (void *)data
->src
;
112 bounce_buffer_start(&bbstate
, addr
, data_count
, flags
);
114 priv
->desc
->cmd
.address
= (dma_addr_t
)bbstate
.bounce_buffer
;
116 priv
->desc
->cmd
.data
|= MXS_DMA_DESC_IRQ
| MXS_DMA_DESC_DEC_SEM
|
117 (data_count
<< MXS_DMA_DESC_BYTES_OFFSET
);
119 dmach
= MXS_DMA_CHANNEL_AHB_APBH_SSP0
+ priv
->id
;
120 mxs_dma_desc_append(dmach
, priv
->desc
);
121 if (mxs_dma_go(dmach
)) {
122 bounce_buffer_stop(&bbstate
);
126 bounce_buffer_stop(&bbstate
);
132 * Sends a command out on the bus. Takes the mmc pointer,
133 * a command pointer, and an optional data pointer.
136 mxsmmc_send_cmd(struct mmc
*mmc
, struct mmc_cmd
*cmd
, struct mmc_data
*data
)
138 struct mxsmmc_priv
*priv
= mmc
->priv
;
139 struct mxs_ssp_regs
*ssp_regs
= priv
->regs
;
145 debug("MMC%d: CMD%d\n", mmc
->block_dev
.devnum
, cmd
->cmdidx
);
148 timeout
= MXSMMC_MAX_TIMEOUT
;
151 reg
= readl(&ssp_regs
->hw_ssp_status
);
153 (SSP_STATUS_BUSY
| SSP_STATUS_DATA_BUSY
|
154 SSP_STATUS_CMD_BUSY
))) {
160 printf("MMC%d: Bus busy timeout!\n", mmc
->block_dev
.devnum
);
164 /* See if card is present */
165 if (!mxsmmc_cd(priv
)) {
166 printf("MMC%d: No card detected!\n", mmc
->block_dev
.devnum
);
170 /* Start building CTRL0 contents */
171 ctrl0
= priv
->buswidth
;
174 if (!(cmd
->resp_type
& MMC_RSP_CRC
))
175 ctrl0
|= SSP_CTRL0_IGNORE_CRC
;
176 if (cmd
->resp_type
& MMC_RSP_PRESENT
) /* Need to get response */
177 ctrl0
|= SSP_CTRL0_GET_RESP
;
178 if (cmd
->resp_type
& MMC_RSP_136
) /* It's a 136 bits response */
179 ctrl0
|= SSP_CTRL0_LONG_RESP
;
181 if (data
&& (data
->blocksize
* data
->blocks
< MXSMMC_SMALL_TRANSFER
))
182 writel(SSP_CTRL1_DMA_ENABLE
, &ssp_regs
->hw_ssp_ctrl1_clr
);
184 writel(SSP_CTRL1_DMA_ENABLE
, &ssp_regs
->hw_ssp_ctrl1_set
);
187 reg
= readl(&ssp_regs
->hw_ssp_cmd0
);
188 reg
&= ~(SSP_CMD0_CMD_MASK
| SSP_CMD0_APPEND_8CYC
);
189 reg
|= cmd
->cmdidx
<< SSP_CMD0_CMD_OFFSET
;
190 if (cmd
->cmdidx
== MMC_CMD_STOP_TRANSMISSION
)
191 reg
|= SSP_CMD0_APPEND_8CYC
;
192 writel(reg
, &ssp_regs
->hw_ssp_cmd0
);
194 /* Command argument */
195 writel(cmd
->cmdarg
, &ssp_regs
->hw_ssp_cmd1
);
200 if (data
->flags
& MMC_DATA_READ
) {
201 ctrl0
|= SSP_CTRL0_READ
;
202 } else if (priv
->mmc_is_wp
&&
203 priv
->mmc_is_wp(mmc
->block_dev
.devnum
)) {
204 printf("MMC%d: Can not write a locked card!\n",
205 mmc
->block_dev
.devnum
);
209 ctrl0
|= SSP_CTRL0_DATA_XFER
;
211 reg
= data
->blocksize
* data
->blocks
;
212 #if defined(CONFIG_MX23)
213 ctrl0
|= reg
& SSP_CTRL0_XFER_COUNT_MASK
;
215 clrsetbits_le32(&ssp_regs
->hw_ssp_cmd0
,
216 SSP_CMD0_BLOCK_SIZE_MASK
| SSP_CMD0_BLOCK_COUNT_MASK
,
217 ((data
->blocks
- 1) << SSP_CMD0_BLOCK_COUNT_OFFSET
) |
218 ((ffs(data
->blocksize
) - 1) <<
219 SSP_CMD0_BLOCK_SIZE_OFFSET
));
220 #elif defined(CONFIG_MX28)
221 writel(reg
, &ssp_regs
->hw_ssp_xfer_size
);
223 reg
= ((data
->blocks
- 1) <<
224 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET
) |
225 ((ffs(data
->blocksize
) - 1) <<
226 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET
);
227 writel(reg
, &ssp_regs
->hw_ssp_block_size
);
231 /* Kick off the command */
232 ctrl0
|= SSP_CTRL0_WAIT_FOR_IRQ
| SSP_CTRL0_ENABLE
| SSP_CTRL0_RUN
;
233 writel(ctrl0
, &ssp_regs
->hw_ssp_ctrl0
);
235 /* Wait for the command to complete */
236 timeout
= MXSMMC_MAX_TIMEOUT
;
239 reg
= readl(&ssp_regs
->hw_ssp_status
);
240 if (!(reg
& SSP_STATUS_CMD_BUSY
))
245 printf("MMC%d: Command %d busy\n",
246 mmc
->block_dev
.devnum
, cmd
->cmdidx
);
250 /* Check command timeout */
251 if (reg
& SSP_STATUS_RESP_TIMEOUT
) {
252 printf("MMC%d: Command %d timeout (status 0x%08x)\n",
253 mmc
->block_dev
.devnum
, cmd
->cmdidx
, reg
);
257 /* Check command errors */
258 if (reg
& (SSP_STATUS_RESP_CRC_ERR
| SSP_STATUS_RESP_ERR
)) {
259 printf("MMC%d: Command %d error (status 0x%08x)!\n",
260 mmc
->block_dev
.devnum
, cmd
->cmdidx
, reg
);
264 /* Copy response to response buffer */
265 if (cmd
->resp_type
& MMC_RSP_136
) {
266 cmd
->response
[3] = readl(&ssp_regs
->hw_ssp_sdresp0
);
267 cmd
->response
[2] = readl(&ssp_regs
->hw_ssp_sdresp1
);
268 cmd
->response
[1] = readl(&ssp_regs
->hw_ssp_sdresp2
);
269 cmd
->response
[0] = readl(&ssp_regs
->hw_ssp_sdresp3
);
271 cmd
->response
[0] = readl(&ssp_regs
->hw_ssp_sdresp0
);
273 /* Return if no data to process */
277 if (data
->blocksize
* data
->blocks
< MXSMMC_SMALL_TRANSFER
) {
278 ret
= mxsmmc_send_cmd_pio(priv
, data
);
280 printf("MMC%d: Data timeout with command %d "
281 "(status 0x%08x)!\n",
282 mmc
->block_dev
.devnum
, cmd
->cmdidx
, reg
);
286 ret
= mxsmmc_send_cmd_dma(priv
, data
);
288 printf("MMC%d: DMA transfer failed\n",
289 mmc
->block_dev
.devnum
);
294 /* Check data errors */
295 reg
= readl(&ssp_regs
->hw_ssp_status
);
297 (SSP_STATUS_TIMEOUT
| SSP_STATUS_DATA_CRC_ERR
|
298 SSP_STATUS_FIFO_OVRFLW
| SSP_STATUS_FIFO_UNDRFLW
)) {
299 printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
300 mmc
->block_dev
.devnum
, cmd
->cmdidx
, reg
);
307 static int mxsmmc_set_ios(struct mmc
*mmc
)
309 struct mxsmmc_priv
*priv
= mmc
->priv
;
310 struct mxs_ssp_regs
*ssp_regs
= priv
->regs
;
312 /* Set the clock speed */
314 mxs_set_ssp_busclock(priv
->id
, mmc
->clock
/ 1000);
316 switch (mmc
->bus_width
) {
318 priv
->buswidth
= SSP_CTRL0_BUS_WIDTH_ONE_BIT
;
321 priv
->buswidth
= SSP_CTRL0_BUS_WIDTH_FOUR_BIT
;
324 priv
->buswidth
= SSP_CTRL0_BUS_WIDTH_EIGHT_BIT
;
328 /* Set the bus width */
329 clrsetbits_le32(&ssp_regs
->hw_ssp_ctrl0
,
330 SSP_CTRL0_BUS_WIDTH_MASK
, priv
->buswidth
);
332 debug("MMC%d: Set %d bits bus width\n",
333 mmc
->block_dev
.devnum
, mmc
->bus_width
);
338 static int mxsmmc_init(struct mmc
*mmc
)
340 struct mxsmmc_priv
*priv
= mmc
->priv
;
341 struct mxs_ssp_regs
*ssp_regs
= priv
->regs
;
344 mxs_reset_block(&ssp_regs
->hw_ssp_ctrl0_reg
);
346 /* Reconfigure the SSP block for MMC operation */
347 writel(SSP_CTRL1_SSP_MODE_SD_MMC
|
348 SSP_CTRL1_WORD_LENGTH_EIGHT_BITS
|
349 SSP_CTRL1_DMA_ENABLE
|
351 SSP_CTRL1_RECV_TIMEOUT_IRQ_EN
|
352 SSP_CTRL1_DATA_CRC_IRQ_EN
|
353 SSP_CTRL1_DATA_TIMEOUT_IRQ_EN
|
354 SSP_CTRL1_RESP_TIMEOUT_IRQ_EN
|
355 SSP_CTRL1_RESP_ERR_IRQ_EN
,
356 &ssp_regs
->hw_ssp_ctrl1_set
);
358 /* Set initial bit clock 400 KHz */
359 mxs_set_ssp_busclock(priv
->id
, 400);
361 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
362 writel(SSP_CMD0_CONT_CLKING_EN
, &ssp_regs
->hw_ssp_cmd0_set
);
364 writel(SSP_CMD0_CONT_CLKING_EN
, &ssp_regs
->hw_ssp_cmd0_clr
);
369 static const struct mmc_ops mxsmmc_ops
= {
370 .send_cmd
= mxsmmc_send_cmd
,
371 .set_ios
= mxsmmc_set_ios
,
375 int mxsmmc_initialize(bd_t
*bis
, int id
, int (*wp
)(int), int (*cd
)(int))
377 struct mmc
*mmc
= NULL
;
378 struct mxsmmc_priv
*priv
= NULL
;
380 const unsigned int mxsmmc_clk_id
= mxs_ssp_clock_by_bus(id
);
382 if (!mxs_ssp_bus_id_valid(id
))
385 priv
= malloc(sizeof(struct mxsmmc_priv
));
389 priv
->desc
= mxs_dma_desc_alloc();
395 ret
= mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0
+ id
);
399 priv
->mmc_is_wp
= wp
;
402 priv
->regs
= mxs_ssp_regs_by_bus(id
);
404 priv
->cfg
.name
= "MXS MMC";
405 priv
->cfg
.ops
= &mxsmmc_ops
;
407 priv
->cfg
.voltages
= MMC_VDD_32_33
| MMC_VDD_33_34
;
409 priv
->cfg
.host_caps
= MMC_MODE_4BIT
| MMC_MODE_8BIT
|
410 MMC_MODE_HS_52MHz
| MMC_MODE_HS
;
413 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
414 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
415 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
416 * CLOCK_RATE could be any integer from 0 to 255.
418 priv
->cfg
.f_min
= 400000;
419 priv
->cfg
.f_max
= mxc_get_clock(MXC_SSP0_CLK
+ mxsmmc_clk_id
) * 1000 / 2;
420 priv
->cfg
.b_max
= 0x20;
422 mmc
= mmc_create(&priv
->cfg
, priv
);
424 mxs_dma_desc_free(priv
->desc
);