drivers/mmc/sunxi_mmc.c

   1 /*
   2  * (C) Copyright 2007-2011
   3  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   4  * Aaron <leafy.myeh@allwinnertech.com>
   5  *
   6  * MMC driver for allwinner sunxi platform.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <errno.h>
  13 #include <malloc.h>
  14 #include <mmc.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/gpio.h>
  19 #include <asm/arch/mmc.h>
  20 #include <asm-generic/gpio.h>
  21
  22 struct sunxi_mmc_host {
  23         unsigned mmc_no;
  24         uint32_t *mclkreg;
  25         unsigned fatal_err;
  26         struct sunxi_mmc *reg;
  27         struct mmc_config cfg;
  28 };
  29
  30 /* support 4 mmc hosts */
  31 struct sunxi_mmc_host mmc_host[4];
  32
  33 static int sunxi_mmc_getcd_gpio(int sdc_no)
  34 {
  35         switch (sdc_no) {
  36         case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
  37         case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
  38         case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
  39         case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
  40         }
  41         return -EINVAL;
  42 }
  43
  44 static int mmc_resource_init(int sdc_no)
  45 {
  46         struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
  47         struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  48         int cd_pin, ret = 0;
  49
  50         debug("init mmc %d resource\n", sdc_no);
  51
  52         switch (sdc_no) {
  53         case 0:
  54                 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
  55                 mmchost->mclkreg = &ccm->sd0_clk_cfg;
  56                 break;
  57         case 1:
  58                 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
  59                 mmchost->mclkreg = &ccm->sd1_clk_cfg;
  60                 break;
  61         case 2:
  62                 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
  63                 mmchost->mclkreg = &ccm->sd2_clk_cfg;
  64                 break;
  65         case 3:
  66                 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
  67                 mmchost->mclkreg = &ccm->sd3_clk_cfg;
  68                 break;
  69         default:
  70                 printf("Wrong mmc number %d\n", sdc_no);
  71                 return -1;
  72         }
  73         mmchost->mmc_no = sdc_no;
  74
  75         cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
  76         if (cd_pin >= 0) {
  77                 ret = gpio_request(cd_pin, "mmc_cd");
  78                 if (!ret) {
  79                         sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
  80                         ret = gpio_direction_input(cd_pin);
  81                 }
  82         }
  83
  84         return ret;
  85 }
  86
  87 static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz)
  88 {
  89         unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
  90
  91         if (hz <= 24000000) {
  92                 pll = CCM_MMC_CTRL_OSCM24;
  93                 pll_hz = 24000000;
  94         } else {
  95 #ifdef CONFIG_MACH_SUN9I
  96                 pll = CCM_MMC_CTRL_PLL_PERIPH0;
  97                 pll_hz = clock_get_pll4_periph0();
  98 #else
  99                 pll = CCM_MMC_CTRL_PLL6;
 100                 pll_hz = clock_get_pll6();
 101 #endif
 102         }
 103
 104         div = pll_hz / hz;
 105         if (pll_hz % hz)
 106                 div++;
 107
 108         n = 0;
 109         while (div > 16) {
 110                 n++;
 111                 div = (div + 1) / 2;
 112         }
 113
 114         if (n > 3) {
 115                 printf("mmc %u error cannot set clock to %u\n",
 116                        mmchost->mmc_no, hz);
 117                 return -1;
 118         }
 119
 120         /* determine delays */
 121         if (hz <= 400000) {
 122                 oclk_dly = 0;
 123                 sclk_dly = 0;
 124         } else if (hz <= 25000000) {
 125                 oclk_dly = 0;
 126                 sclk_dly = 5;
 127 #ifdef CONFIG_MACH_SUN9I
 128         } else if (hz <= 50000000) {
 129                 oclk_dly = 5;
 130                 sclk_dly = 4;
 131         } else {
 132                 /* hz > 50000000 */
 133                 oclk_dly = 2;
 134                 sclk_dly = 4;
 135 #else
 136         } else if (hz <= 50000000) {
 137                 oclk_dly = 3;
 138                 sclk_dly = 4;
 139         } else {
 140                 /* hz > 50000000 */
 141                 oclk_dly = 1;
 142                 sclk_dly = 4;
 143 #endif
 144         }
 145
 146         writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) |
 147                CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
 148                CCM_MMC_CTRL_M(div), mmchost->mclkreg);
 149
 150         debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
 151               mmchost->mmc_no, hz, pll_hz, 1u << n, div,
 152               pll_hz / (1u << n) / div);
 153
 154         return 0;
 155 }
 156
 157 static int mmc_clk_io_on(int sdc_no)
 158 {
 159         struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
 160         struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 161
 162         debug("init mmc %d clock and io\n", sdc_no);
 163
 164         /* config ahb clock */
 165         setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
 166
 167 #ifdef CONFIG_SUNXI_GEN_SUN6I
 168         /* unassert reset */
 169         setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
 170 #endif
 171 #if defined(CONFIG_MACH_SUN9I)
 172         /* sun9i has a mmc-common module, also set the gate and reset there */
 173         writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
 174                SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
 175 #endif
 176
 177         return mmc_set_mod_clk(mmchost, 24000000);
 178 }
 179
 180 static int mmc_update_clk(struct mmc *mmc)
 181 {
 182         struct sunxi_mmc_host *mmchost = mmc->priv;
 183         unsigned int cmd;
 184         unsigned timeout_msecs = 2000;
 185
 186         cmd = SUNXI_MMC_CMD_START |
 187               SUNXI_MMC_CMD_UPCLK_ONLY |
 188               SUNXI_MMC_CMD_WAIT_PRE_OVER;
 189         writel(cmd, &mmchost->reg->cmd);
 190         while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) {
 191                 if (!timeout_msecs--)
 192                         return -1;
 193                 udelay(1000);
 194         }
 195
 196         /* clock update sets various irq status bits, clear these */
 197         writel(readl(&mmchost->reg->rint), &mmchost->reg->rint);
 198
 199         return 0;
 200 }
 201
 202 static int mmc_config_clock(struct mmc *mmc)
 203 {
 204         struct sunxi_mmc_host *mmchost = mmc->priv;
 205         unsigned rval = readl(&mmchost->reg->clkcr);
 206
 207         /* Disable Clock */
 208         rval &= ~SUNXI_MMC_CLK_ENABLE;
 209         writel(rval, &mmchost->reg->clkcr);
 210         if (mmc_update_clk(mmc))
 211                 return -1;
 212
 213         /* Set mod_clk to new rate */
 214         if (mmc_set_mod_clk(mmchost, mmc->clock))
 215                 return -1;
 216
 217         /* Clear internal divider */
 218         rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
 219         writel(rval, &mmchost->reg->clkcr);
 220
 221         /* Re-enable Clock */
 222         rval |= SUNXI_MMC_CLK_ENABLE;
 223         writel(rval, &mmchost->reg->clkcr);
 224         if (mmc_update_clk(mmc))
 225                 return -1;
 226
 227         return 0;
 228 }
 229
 230 static int sunxi_mmc_set_ios(struct mmc *mmc)
 231 {
 232         struct sunxi_mmc_host *mmchost = mmc->priv;
 233
 234         debug("set ios: bus_width: %x, clock: %d\n",
 235               mmc->bus_width, mmc->clock);
 236
 237         /* Change clock first */
 238         if (mmc->clock && mmc_config_clock(mmc) != 0) {
 239                 mmchost->fatal_err = 1;
 240                 return -EINVAL;
 241         }
 242
 243         /* Change bus width */
 244         if (mmc->bus_width == 8)
 245                 writel(0x2, &mmchost->reg->width);
 246         else if (mmc->bus_width == 4)
 247                 writel(0x1, &mmchost->reg->width);
 248         else
 249                 writel(0x0, &mmchost->reg->width);
 250
 251         return 0;
 252 }
 253
 254 static int sunxi_mmc_core_init(struct mmc *mmc)
 255 {
 256         struct sunxi_mmc_host *mmchost = mmc->priv;
 257
 258         /* Reset controller */
 259         writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
 260         udelay(1000);
 261
 262         return 0;
 263 }
 264
 265 static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
 266 {
 267         struct sunxi_mmc_host *mmchost = mmc->priv;
 268         const int reading = !!(data->flags & MMC_DATA_READ);
 269         const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
 270                                               SUNXI_MMC_STATUS_FIFO_FULL;
 271         unsigned i;
 272         unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
 273         unsigned byte_cnt = data->blocksize * data->blocks;
 274         unsigned timeout_usecs = (byte_cnt >> 8) * 1000;
 275         if (timeout_usecs < 2000000)
 276                 timeout_usecs = 2000000;
 277
 278         /* Always read / write data through the CPU */
 279         setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
 280
 281         for (i = 0; i < (byte_cnt >> 2); i++) {
 282                 while (readl(&mmchost->reg->status) & status_bit) {
 283                         if (!timeout_usecs--)
 284                                 return -1;
 285                         udelay(1);
 286                 }
 287
 288                 if (reading)
 289                         buff[i] = readl(&mmchost->reg->fifo);
 290                 else
 291                         writel(buff[i], &mmchost->reg->fifo);
 292         }
 293
 294         return 0;
 295 }
 296
 297 static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs,
 298                          unsigned int done_bit, const char *what)
 299 {
 300         struct sunxi_mmc_host *mmchost = mmc->priv;
 301         unsigned int status;
 302
 303         do {
 304                 status = readl(&mmchost->reg->rint);
 305                 if (!timeout_msecs-- ||
 306                     (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
 307                         debug("%s timeout %x\n", what,
 308                               status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
 309                         return -ETIMEDOUT;
 310                 }
 311                 udelay(1000);
 312         } while (!(status & done_bit));
 313
 314         return 0;
 315 }
 316
 317 static int sunxi_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 318                               struct mmc_data *data)
 319 {
 320         struct sunxi_mmc_host *mmchost = mmc->priv;
 321         unsigned int cmdval = SUNXI_MMC_CMD_START;
 322         unsigned int timeout_msecs;
 323         int error = 0;
 324         unsigned int status = 0;
 325         unsigned int bytecnt = 0;
 326
 327         if (mmchost->fatal_err)
 328                 return -1;
 329         if (cmd->resp_type & MMC_RSP_BUSY)
 330                 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
 331         if (cmd->cmdidx == 12)
 332                 return 0;
 333
 334         if (!cmd->cmdidx)
 335                 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
 336         if (cmd->resp_type & MMC_RSP_PRESENT)
 337                 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
 338         if (cmd->resp_type & MMC_RSP_136)
 339                 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
 340         if (cmd->resp_type & MMC_RSP_CRC)
 341                 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
 342
 343         if (data) {
 344                 if ((u32)(long)data->dest & 0x3) {
 345                         error = -1;
 346                         goto out;
 347                 }
 348
 349                 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
 350                 if (data->flags & MMC_DATA_WRITE)
 351                         cmdval |= SUNXI_MMC_CMD_WRITE;
 352                 if (data->blocks > 1)
 353                         cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
 354                 writel(data->blocksize, &mmchost->reg->blksz);
 355                 writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt);
 356         }
 357
 358         debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no,
 359               cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
 360         writel(cmd->cmdarg, &mmchost->reg->arg);
 361
 362         if (!data)
 363                 writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
 364
 365         /*
 366          * transfer data and check status
 367          * STATREG[2] : FIFO empty
 368          * STATREG[3] : FIFO full
 369          */
 370         if (data) {
 371                 int ret = 0;
 372
 373                 bytecnt = data->blocksize * data->blocks;
 374                 debug("trans data %d bytes\n", bytecnt);
 375                 writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
 376                 ret = mmc_trans_data_by_cpu(mmc, data);
 377                 if (ret) {
 378                         error = readl(&mmchost->reg->rint) & \
 379                                 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
 380                         error = -ETIMEDOUT;
 381                         goto out;
 382                 }
 383         }
 384
 385         error = mmc_rint_wait(mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
 386         if (error)
 387                 goto out;
 388
 389         if (data) {
 390                 timeout_msecs = 120;
 391                 debug("cacl timeout %x msec\n", timeout_msecs);
 392                 error = mmc_rint_wait(mmc, timeout_msecs,
 393                                       data->blocks > 1 ?
 394                                       SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
 395                                       SUNXI_MMC_RINT_DATA_OVER,
 396                                       "data");
 397                 if (error)
 398                         goto out;
 399         }
 400
 401         if (cmd->resp_type & MMC_RSP_BUSY) {
 402                 timeout_msecs = 2000;
 403                 do {
 404                         status = readl(&mmchost->reg->status);
 405                         if (!timeout_msecs--) {
 406                                 debug("busy timeout\n");
 407                                 error = -ETIMEDOUT;
 408                                 goto out;
 409                         }
 410                         udelay(1000);
 411                 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
 412         }
 413
 414         if (cmd->resp_type & MMC_RSP_136) {
 415                 cmd->response[0] = readl(&mmchost->reg->resp3);
 416                 cmd->response[1] = readl(&mmchost->reg->resp2);
 417                 cmd->response[2] = readl(&mmchost->reg->resp1);
 418                 cmd->response[3] = readl(&mmchost->reg->resp0);
 419                 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
 420                       cmd->response[3], cmd->response[2],
 421                       cmd->response[1], cmd->response[0]);
 422         } else {
 423                 cmd->response[0] = readl(&mmchost->reg->resp0);
 424                 debug("mmc resp 0x%08x\n", cmd->response[0]);
 425         }
 426 out:
 427         if (error < 0) {
 428                 writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
 429                 mmc_update_clk(mmc);
 430         }
 431         writel(0xffffffff, &mmchost->reg->rint);
 432         writel(readl(&mmchost->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
 433                &mmchost->reg->gctrl);
 434
 435         return error;
 436 }
 437
 438 static int sunxi_mmc_getcd(struct mmc *mmc)
 439 {
 440         struct sunxi_mmc_host *mmchost = mmc->priv;
 441         int cd_pin;
 442
 443         cd_pin = sunxi_mmc_getcd_gpio(mmchost->mmc_no);
 444         if (cd_pin < 0)
 445                 return 1;
 446
 447         return !gpio_get_value(cd_pin);
 448 }
 449
 450 static const struct mmc_ops sunxi_mmc_ops = {
 451         .send_cmd       = sunxi_mmc_send_cmd,
 452         .set_ios        = sunxi_mmc_set_ios,
 453         .init           = sunxi_mmc_core_init,
 454         .getcd          = sunxi_mmc_getcd,
 455 };
 456
 457 struct mmc *sunxi_mmc_init(int sdc_no)
 458 {
 459         struct mmc_config *cfg = &mmc_host[sdc_no].cfg;
 460
 461         memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host));
 462
 463         cfg->name = "SUNXI SD/MMC";
 464         cfg->ops  = &sunxi_mmc_ops;
 465
 466         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 467         cfg->host_caps = MMC_MODE_4BIT;
 468 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
 469         if (sdc_no == 2)
 470                 cfg->host_caps = MMC_MODE_8BIT;
 471 #endif
 472         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 473         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 474
 475         cfg->f_min = 400000;
 476         cfg->f_max = 52000000;
 477
 478         if (mmc_resource_init(sdc_no) != 0)
 479                 return NULL;
 480
 481         mmc_clk_io_on(sdc_no);
 482
 483         return mmc_create(cfg, &mmc_host[sdc_no]);
 484 }