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mmc: uniphier-sd: Factor out register IO
[people/ms/u-boot.git] / drivers / mmc / uniphier-sd.c
1 /*
2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <clk.h>
10 #include <fdtdec.h>
11 #include <mmc.h>
12 #include <dm.h>
13 #include <linux/compat.h>
14 #include <linux/dma-direction.h>
15 #include <linux/io.h>
16 #include <linux/sizes.h>
17 #include <asm/unaligned.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 #define UNIPHIER_SD_CMD 0x000 /* command */
22 #define UNIPHIER_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
23 #define UNIPHIER_SD_CMD_MULTI BIT(13) /* multiple block transfer */
24 #define UNIPHIER_SD_CMD_RD BIT(12) /* 1: read, 0: write */
25 #define UNIPHIER_SD_CMD_DATA BIT(11) /* data transfer */
26 #define UNIPHIER_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */
27 #define UNIPHIER_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */
28 #define UNIPHIER_SD_CMD_RSP_NONE (3 << 8)/* response: none */
29 #define UNIPHIER_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */
30 #define UNIPHIER_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */
31 #define UNIPHIER_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */
32 #define UNIPHIER_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */
33 #define UNIPHIER_SD_ARG 0x008 /* command argument */
34 #define UNIPHIER_SD_STOP 0x010 /* stop action control */
35 #define UNIPHIER_SD_STOP_SEC BIT(8) /* use sector count */
36 #define UNIPHIER_SD_STOP_STP BIT(0) /* issue CMD12 */
37 #define UNIPHIER_SD_SECCNT 0x014 /* sector counter */
38 #define UNIPHIER_SD_RSP10 0x018 /* response[39:8] */
39 #define UNIPHIER_SD_RSP32 0x020 /* response[71:40] */
40 #define UNIPHIER_SD_RSP54 0x028 /* response[103:72] */
41 #define UNIPHIER_SD_RSP76 0x030 /* response[127:104] */
42 #define UNIPHIER_SD_INFO1 0x038 /* IRQ status 1 */
43 #define UNIPHIER_SD_INFO1_CD BIT(5) /* state of card detect */
44 #define UNIPHIER_SD_INFO1_INSERT BIT(4) /* card inserted */
45 #define UNIPHIER_SD_INFO1_REMOVE BIT(3) /* card removed */
46 #define UNIPHIER_SD_INFO1_CMP BIT(2) /* data complete */
47 #define UNIPHIER_SD_INFO1_RSP BIT(0) /* response complete */
48 #define UNIPHIER_SD_INFO2 0x03c /* IRQ status 2 */
49 #define UNIPHIER_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */
50 #define UNIPHIER_SD_INFO2_CBSY BIT(14) /* command busy */
51 #define UNIPHIER_SD_INFO2_BWE BIT(9) /* write buffer ready */
52 #define UNIPHIER_SD_INFO2_BRE BIT(8) /* read buffer ready */
53 #define UNIPHIER_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */
54 #define UNIPHIER_SD_INFO2_ERR_RTO BIT(6) /* response time out */
55 #define UNIPHIER_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */
56 #define UNIPHIER_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */
57 #define UNIPHIER_SD_INFO2_ERR_TO BIT(3) /* time out error */
58 #define UNIPHIER_SD_INFO2_ERR_END BIT(2) /* END bit error */
59 #define UNIPHIER_SD_INFO2_ERR_CRC BIT(1) /* CRC error */
60 #define UNIPHIER_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */
61 #define UNIPHIER_SD_INFO1_MASK 0x040
62 #define UNIPHIER_SD_INFO2_MASK 0x044
63 #define UNIPHIER_SD_CLKCTL 0x048 /* clock divisor */
64 #define UNIPHIER_SD_CLKCTL_DIV_MASK 0x104ff
65 #define UNIPHIER_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */
66 #define UNIPHIER_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */
67 #define UNIPHIER_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */
68 #define UNIPHIER_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */
69 #define UNIPHIER_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */
70 #define UNIPHIER_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */
71 #define UNIPHIER_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */
72 #define UNIPHIER_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */
73 #define UNIPHIER_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
74 #define UNIPHIER_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */
75 #define UNIPHIER_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */
76 #define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */
77 #define UNIPHIER_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */
78 #define UNIPHIER_SD_SIZE 0x04c /* block size */
79 #define UNIPHIER_SD_OPTION 0x050
80 #define UNIPHIER_SD_OPTION_WIDTH_MASK (5 << 13)
81 #define UNIPHIER_SD_OPTION_WIDTH_1 (4 << 13)
82 #define UNIPHIER_SD_OPTION_WIDTH_4 (0 << 13)
83 #define UNIPHIER_SD_OPTION_WIDTH_8 (1 << 13)
84 #define UNIPHIER_SD_BUF 0x060 /* read/write buffer */
85 #define UNIPHIER_SD_EXTMODE 0x1b0
86 #define UNIPHIER_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */
87 #define UNIPHIER_SD_SOFT_RST 0x1c0
88 #define UNIPHIER_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */
89 #define UNIPHIER_SD_VERSION 0x1c4 /* version register */
90 #define UNIPHIER_SD_VERSION_IP 0xff /* IP version */
91 #define UNIPHIER_SD_HOST_MODE 0x1c8
92 #define UNIPHIER_SD_IF_MODE 0x1cc
93 #define UNIPHIER_SD_IF_MODE_DDR BIT(0) /* DDR mode */
94 #define UNIPHIER_SD_VOLT 0x1e4 /* voltage switch */
95 #define UNIPHIER_SD_VOLT_MASK (3 << 0)
96 #define UNIPHIER_SD_VOLT_OFF (0 << 0)
97 #define UNIPHIER_SD_VOLT_330 (1 << 0)/* 3.3V signal */
98 #define UNIPHIER_SD_VOLT_180 (2 << 0)/* 1.8V signal */
99 #define UNIPHIER_SD_DMA_MODE 0x410
100 #define UNIPHIER_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */
101 #define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */
102 #define UNIPHIER_SD_DMA_CTL 0x414
103 #define UNIPHIER_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */
104 #define UNIPHIER_SD_DMA_RST 0x418
105 #define UNIPHIER_SD_DMA_RST_RD BIT(9)
106 #define UNIPHIER_SD_DMA_RST_WR BIT(8)
107 #define UNIPHIER_SD_DMA_INFO1 0x420
108 #define UNIPHIER_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete*/
109 #define UNIPHIER_SD_DMA_INFO1_END_RD BIT(17) /* Don't use! Hardware bug */
110 #define UNIPHIER_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */
111 #define UNIPHIER_SD_DMA_INFO1_MASK 0x424
112 #define UNIPHIER_SD_DMA_INFO2 0x428
113 #define UNIPHIER_SD_DMA_INFO2_ERR_RD BIT(17)
114 #define UNIPHIER_SD_DMA_INFO2_ERR_WR BIT(16)
115 #define UNIPHIER_SD_DMA_INFO2_MASK 0x42c
116 #define UNIPHIER_SD_DMA_ADDR_L 0x440
117 #define UNIPHIER_SD_DMA_ADDR_H 0x444
118
119 /* alignment required by the DMA engine of this controller */
120 #define UNIPHIER_SD_DMA_MINALIGN 0x10
121
122 struct uniphier_sd_plat {
123 struct mmc_config cfg;
124 struct mmc mmc;
125 };
126
127 struct uniphier_sd_priv {
128 void __iomem *regbase;
129 unsigned long mclk;
130 unsigned int version;
131 u32 caps;
132 #define UNIPHIER_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */
133 #define UNIPHIER_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */
134 #define UNIPHIER_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */
135 };
136
137 static u32 uniphier_sd_readl(struct uniphier_sd_priv *priv, const u32 reg)
138 {
139 return readl(priv->regbase + reg);
140 }
141
142 static void uniphier_sd_writel(struct uniphier_sd_priv *priv,
143 const u32 val, const u32 reg)
144 {
145 writel(val, priv->regbase + reg);
146 }
147
148 static dma_addr_t __dma_map_single(void *ptr, size_t size,
149 enum dma_data_direction dir)
150 {
151 unsigned long addr = (unsigned long)ptr;
152
153 if (dir == DMA_FROM_DEVICE)
154 invalidate_dcache_range(addr, addr + size);
155 else
156 flush_dcache_range(addr, addr + size);
157
158 return addr;
159 }
160
161 static void __dma_unmap_single(dma_addr_t addr, size_t size,
162 enum dma_data_direction dir)
163 {
164 if (dir != DMA_TO_DEVICE)
165 invalidate_dcache_range(addr, addr + size);
166 }
167
168 static int uniphier_sd_check_error(struct udevice *dev)
169 {
170 struct uniphier_sd_priv *priv = dev_get_priv(dev);
171 u32 info2 = uniphier_sd_readl(priv, UNIPHIER_SD_INFO2);
172
173 if (info2 & UNIPHIER_SD_INFO2_ERR_RTO) {
174 /*
175 * TIMEOUT must be returned for unsupported command. Do not
176 * display error log since this might be a part of sequence to
177 * distinguish between SD and MMC.
178 */
179 return -ETIMEDOUT;
180 }
181
182 if (info2 & UNIPHIER_SD_INFO2_ERR_TO) {
183 dev_err(dev, "timeout error\n");
184 return -ETIMEDOUT;
185 }
186
187 if (info2 & (UNIPHIER_SD_INFO2_ERR_END | UNIPHIER_SD_INFO2_ERR_CRC |
188 UNIPHIER_SD_INFO2_ERR_IDX)) {
189 dev_err(dev, "communication out of sync\n");
190 return -EILSEQ;
191 }
192
193 if (info2 & (UNIPHIER_SD_INFO2_ERR_ILA | UNIPHIER_SD_INFO2_ERR_ILR |
194 UNIPHIER_SD_INFO2_ERR_ILW)) {
195 dev_err(dev, "illegal access\n");
196 return -EIO;
197 }
198
199 return 0;
200 }
201
202 static int uniphier_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
203 u32 flag)
204 {
205 struct uniphier_sd_priv *priv = dev_get_priv(dev);
206 long wait = 1000000;
207 int ret;
208
209 while (!(uniphier_sd_readl(priv, reg) & flag)) {
210 if (wait-- < 0) {
211 dev_err(dev, "timeout\n");
212 return -ETIMEDOUT;
213 }
214
215 ret = uniphier_sd_check_error(dev);
216 if (ret)
217 return ret;
218
219 udelay(1);
220 }
221
222 return 0;
223 }
224
225 static int uniphier_sd_pio_read_one_block(struct udevice *dev, u32 **pbuf,
226 uint blocksize)
227 {
228 struct uniphier_sd_priv *priv = dev_get_priv(dev);
229 int i, ret;
230
231 /* wait until the buffer is filled with data */
232 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2,
233 UNIPHIER_SD_INFO2_BRE);
234 if (ret)
235 return ret;
236
237 /*
238 * Clear the status flag _before_ read the buffer out because
239 * UNIPHIER_SD_INFO2_BRE is edge-triggered, not level-triggered.
240 */
241 uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
242
243 if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
244 for (i = 0; i < blocksize / 4; i++)
245 *(*pbuf)++ = uniphier_sd_readl(priv, UNIPHIER_SD_BUF);
246 } else {
247 for (i = 0; i < blocksize / 4; i++)
248 put_unaligned(uniphier_sd_readl(priv, UNIPHIER_SD_BUF),
249 (*pbuf)++);
250 }
251
252 return 0;
253 }
254
255 static int uniphier_sd_pio_write_one_block(struct udevice *dev,
256 const u32 **pbuf, uint blocksize)
257 {
258 struct uniphier_sd_priv *priv = dev_get_priv(dev);
259 int i, ret;
260
261 /* wait until the buffer becomes empty */
262 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2,
263 UNIPHIER_SD_INFO2_BWE);
264 if (ret)
265 return ret;
266
267 uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
268
269 if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
270 for (i = 0; i < blocksize / 4; i++)
271 uniphier_sd_writel(priv, *(*pbuf)++, UNIPHIER_SD_BUF);
272 } else {
273 for (i = 0; i < blocksize / 4; i++)
274 uniphier_sd_writel(priv, get_unaligned((*pbuf)++),
275 UNIPHIER_SD_BUF);
276 }
277
278 return 0;
279 }
280
281 static int uniphier_sd_pio_xfer(struct udevice *dev, struct mmc_data *data)
282 {
283 u32 *dest = (u32 *)data->dest;
284 const u32 *src = (const u32 *)data->src;
285 int i, ret;
286
287 for (i = 0; i < data->blocks; i++) {
288 if (data->flags & MMC_DATA_READ)
289 ret = uniphier_sd_pio_read_one_block(dev, &dest,
290 data->blocksize);
291 else
292 ret = uniphier_sd_pio_write_one_block(dev, &src,
293 data->blocksize);
294 if (ret)
295 return ret;
296 }
297
298 return 0;
299 }
300
301 static void uniphier_sd_dma_start(struct uniphier_sd_priv *priv,
302 dma_addr_t dma_addr)
303 {
304 u32 tmp;
305
306 uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO1);
307 uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO2);
308
309 /* enable DMA */
310 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE);
311 tmp |= UNIPHIER_SD_EXTMODE_DMA_EN;
312 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE);
313
314 uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_L);
315
316 /* suppress the warning "right shift count >= width of type" */
317 dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
318
319 uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_H);
320
321 uniphier_sd_writel(priv, UNIPHIER_SD_DMA_CTL_START, UNIPHIER_SD_DMA_CTL);
322 }
323
324 static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
325 unsigned int blocks)
326 {
327 struct uniphier_sd_priv *priv = dev_get_priv(dev);
328 long wait = 1000000 + 10 * blocks;
329
330 while (!(uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO1) & flag)) {
331 if (wait-- < 0) {
332 dev_err(dev, "timeout during DMA\n");
333 return -ETIMEDOUT;
334 }
335
336 udelay(10);
337 }
338
339 if (uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO2)) {
340 dev_err(dev, "error during DMA\n");
341 return -EIO;
342 }
343
344 return 0;
345 }
346
347 static int uniphier_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
348 {
349 struct uniphier_sd_priv *priv = dev_get_priv(dev);
350 size_t len = data->blocks * data->blocksize;
351 void *buf;
352 enum dma_data_direction dir;
353 dma_addr_t dma_addr;
354 u32 poll_flag, tmp;
355 int ret;
356
357 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE);
358
359 if (data->flags & MMC_DATA_READ) {
360 buf = data->dest;
361 dir = DMA_FROM_DEVICE;
362 poll_flag = UNIPHIER_SD_DMA_INFO1_END_RD2;
363 tmp |= UNIPHIER_SD_DMA_MODE_DIR_RD;
364 } else {
365 buf = (void *)data->src;
366 dir = DMA_TO_DEVICE;
367 poll_flag = UNIPHIER_SD_DMA_INFO1_END_WR;
368 tmp &= ~UNIPHIER_SD_DMA_MODE_DIR_RD;
369 }
370
371 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE);
372
373 dma_addr = __dma_map_single(buf, len, dir);
374
375 uniphier_sd_dma_start(priv, dma_addr);
376
377 ret = uniphier_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
378
379 __dma_unmap_single(dma_addr, len, dir);
380
381 return ret;
382 }
383
384 /* check if the address is DMA'able */
385 static bool uniphier_sd_addr_is_dmaable(unsigned long addr)
386 {
387 if (!IS_ALIGNED(addr, UNIPHIER_SD_DMA_MINALIGN))
388 return false;
389
390 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
391 defined(CONFIG_SPL_BUILD)
392 /*
393 * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
394 * of L2, which is unreachable from the DMA engine.
395 */
396 if (addr < CONFIG_SPL_STACK)
397 return false;
398 #endif
399
400 return true;
401 }
402
403 static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
404 struct mmc_data *data)
405 {
406 struct uniphier_sd_priv *priv = dev_get_priv(dev);
407 int ret;
408 u32 tmp;
409
410 if (uniphier_sd_readl(priv, UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) {
411 dev_err(dev, "command busy\n");
412 return -EBUSY;
413 }
414
415 /* clear all status flags */
416 uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO1);
417 uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
418
419 /* disable DMA once */
420 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE);
421 tmp &= ~UNIPHIER_SD_EXTMODE_DMA_EN;
422 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE);
423
424 uniphier_sd_writel(priv, cmd->cmdarg, UNIPHIER_SD_ARG);
425
426 tmp = cmd->cmdidx;
427
428 if (data) {
429 uniphier_sd_writel(priv, data->blocksize, UNIPHIER_SD_SIZE);
430 uniphier_sd_writel(priv, data->blocks, UNIPHIER_SD_SECCNT);
431
432 /* Do not send CMD12 automatically */
433 tmp |= UNIPHIER_SD_CMD_NOSTOP | UNIPHIER_SD_CMD_DATA;
434
435 if (data->blocks > 1)
436 tmp |= UNIPHIER_SD_CMD_MULTI;
437
438 if (data->flags & MMC_DATA_READ)
439 tmp |= UNIPHIER_SD_CMD_RD;
440 }
441
442 /*
443 * Do not use the response type auto-detection on this hardware.
444 * CMD8, for example, has different response types on SD and eMMC,
445 * while this controller always assumes the response type for SD.
446 * Set the response type manually.
447 */
448 switch (cmd->resp_type) {
449 case MMC_RSP_NONE:
450 tmp |= UNIPHIER_SD_CMD_RSP_NONE;
451 break;
452 case MMC_RSP_R1:
453 tmp |= UNIPHIER_SD_CMD_RSP_R1;
454 break;
455 case MMC_RSP_R1b:
456 tmp |= UNIPHIER_SD_CMD_RSP_R1B;
457 break;
458 case MMC_RSP_R2:
459 tmp |= UNIPHIER_SD_CMD_RSP_R2;
460 break;
461 case MMC_RSP_R3:
462 tmp |= UNIPHIER_SD_CMD_RSP_R3;
463 break;
464 default:
465 dev_err(dev, "unknown response type\n");
466 return -EINVAL;
467 }
468
469 dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
470 cmd->cmdidx, tmp, cmd->cmdarg);
471 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CMD);
472
473 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1,
474 UNIPHIER_SD_INFO1_RSP);
475 if (ret)
476 return ret;
477
478 if (cmd->resp_type & MMC_RSP_136) {
479 u32 rsp_127_104 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP76);
480 u32 rsp_103_72 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP54);
481 u32 rsp_71_40 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP32);
482 u32 rsp_39_8 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10);
483
484 cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
485 ((rsp_103_72 & 0xff000000) >> 24);
486 cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) |
487 ((rsp_71_40 & 0xff000000) >> 24);
488 cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) |
489 ((rsp_39_8 & 0xff000000) >> 24);
490 cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
491 } else {
492 /* bit 39-8 */
493 cmd->response[0] = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10);
494 }
495
496 if (data) {
497 /* use DMA if the HW supports it and the buffer is aligned */
498 if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL &&
499 uniphier_sd_addr_is_dmaable((long)data->src))
500 ret = uniphier_sd_dma_xfer(dev, data);
501 else
502 ret = uniphier_sd_pio_xfer(dev, data);
503
504 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1,
505 UNIPHIER_SD_INFO1_CMP);
506 if (ret)
507 return ret;
508 }
509
510 return ret;
511 }
512
513 static int uniphier_sd_set_bus_width(struct uniphier_sd_priv *priv,
514 struct mmc *mmc)
515 {
516 u32 val, tmp;
517
518 switch (mmc->bus_width) {
519 case 1:
520 val = UNIPHIER_SD_OPTION_WIDTH_1;
521 break;
522 case 4:
523 val = UNIPHIER_SD_OPTION_WIDTH_4;
524 break;
525 case 8:
526 val = UNIPHIER_SD_OPTION_WIDTH_8;
527 break;
528 default:
529 return -EINVAL;
530 }
531
532 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_OPTION);
533 tmp &= ~UNIPHIER_SD_OPTION_WIDTH_MASK;
534 tmp |= val;
535 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_OPTION);
536
537 return 0;
538 }
539
540 static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv *priv,
541 struct mmc *mmc)
542 {
543 u32 tmp;
544
545 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_IF_MODE);
546 if (mmc->ddr_mode)
547 tmp |= UNIPHIER_SD_IF_MODE_DDR;
548 else
549 tmp &= ~UNIPHIER_SD_IF_MODE_DDR;
550 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_IF_MODE);
551 }
552
553 static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv,
554 struct mmc *mmc)
555 {
556 unsigned int divisor;
557 u32 val, tmp;
558
559 if (!mmc->clock)
560 return;
561
562 divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
563
564 if (divisor <= 1)
565 val = UNIPHIER_SD_CLKCTL_DIV1;
566 else if (divisor <= 2)
567 val = UNIPHIER_SD_CLKCTL_DIV2;
568 else if (divisor <= 4)
569 val = UNIPHIER_SD_CLKCTL_DIV4;
570 else if (divisor <= 8)
571 val = UNIPHIER_SD_CLKCTL_DIV8;
572 else if (divisor <= 16)
573 val = UNIPHIER_SD_CLKCTL_DIV16;
574 else if (divisor <= 32)
575 val = UNIPHIER_SD_CLKCTL_DIV32;
576 else if (divisor <= 64)
577 val = UNIPHIER_SD_CLKCTL_DIV64;
578 else if (divisor <= 128)
579 val = UNIPHIER_SD_CLKCTL_DIV128;
580 else if (divisor <= 256)
581 val = UNIPHIER_SD_CLKCTL_DIV256;
582 else if (divisor <= 512 || !(priv->caps & UNIPHIER_SD_CAP_DIV1024))
583 val = UNIPHIER_SD_CLKCTL_DIV512;
584 else
585 val = UNIPHIER_SD_CLKCTL_DIV1024;
586
587 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_CLKCTL);
588 if (tmp & UNIPHIER_SD_CLKCTL_SCLKEN &&
589 (tmp & UNIPHIER_SD_CLKCTL_DIV_MASK) == val)
590 return;
591
592 /* stop the clock before changing its rate to avoid a glitch signal */
593 tmp &= ~UNIPHIER_SD_CLKCTL_SCLKEN;
594 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
595
596 tmp &= ~UNIPHIER_SD_CLKCTL_DIV_MASK;
597 tmp |= val | UNIPHIER_SD_CLKCTL_OFFEN;
598 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
599
600 tmp |= UNIPHIER_SD_CLKCTL_SCLKEN;
601 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
602
603 udelay(1000);
604 }
605
606 static int uniphier_sd_set_ios(struct udevice *dev)
607 {
608 struct uniphier_sd_priv *priv = dev_get_priv(dev);
609 struct mmc *mmc = mmc_get_mmc_dev(dev);
610 int ret;
611
612 dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
613 mmc->clock, mmc->ddr_mode, mmc->bus_width);
614
615 ret = uniphier_sd_set_bus_width(priv, mmc);
616 if (ret)
617 return ret;
618 uniphier_sd_set_ddr_mode(priv, mmc);
619 uniphier_sd_set_clk_rate(priv, mmc);
620
621 return 0;
622 }
623
624 static int uniphier_sd_get_cd(struct udevice *dev)
625 {
626 struct uniphier_sd_priv *priv = dev_get_priv(dev);
627
628 if (priv->caps & UNIPHIER_SD_CAP_NONREMOVABLE)
629 return 1;
630
631 return !!(uniphier_sd_readl(priv, UNIPHIER_SD_INFO1) &
632 UNIPHIER_SD_INFO1_CD);
633 }
634
635 static const struct dm_mmc_ops uniphier_sd_ops = {
636 .send_cmd = uniphier_sd_send_cmd,
637 .set_ios = uniphier_sd_set_ios,
638 .get_cd = uniphier_sd_get_cd,
639 };
640
641 static void uniphier_sd_host_init(struct uniphier_sd_priv *priv)
642 {
643 u32 tmp;
644
645 /* soft reset of the host */
646 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_SOFT_RST);
647 tmp &= ~UNIPHIER_SD_SOFT_RST_RSTX;
648 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST);
649 tmp |= UNIPHIER_SD_SOFT_RST_RSTX;
650 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST);
651
652 /* FIXME: implement eMMC hw_reset */
653
654 uniphier_sd_writel(priv, UNIPHIER_SD_STOP_SEC, UNIPHIER_SD_STOP);
655
656 /*
657 * Connected to 32bit AXI.
658 * This register dropped backward compatibility at version 0x10.
659 * Write an appropriate value depending on the IP version.
660 */
661 uniphier_sd_writel(priv, priv->version >= 0x10 ? 0x00000101 : 0x00000000,
662 UNIPHIER_SD_HOST_MODE);
663
664 if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL) {
665 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE);
666 tmp |= UNIPHIER_SD_DMA_MODE_ADDR_INC;
667 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE);
668 }
669 }
670
671 static int uniphier_sd_bind(struct udevice *dev)
672 {
673 struct uniphier_sd_plat *plat = dev_get_platdata(dev);
674
675 return mmc_bind(dev, &plat->mmc, &plat->cfg);
676 }
677
678 static int uniphier_sd_probe(struct udevice *dev)
679 {
680 struct uniphier_sd_plat *plat = dev_get_platdata(dev);
681 struct uniphier_sd_priv *priv = dev_get_priv(dev);
682 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
683 fdt_addr_t base;
684 struct clk clk;
685 int ret;
686
687 base = devfdt_get_addr(dev);
688 if (base == FDT_ADDR_T_NONE)
689 return -EINVAL;
690
691 priv->regbase = devm_ioremap(dev, base, SZ_2K);
692 if (!priv->regbase)
693 return -ENOMEM;
694
695 ret = clk_get_by_index(dev, 0, &clk);
696 if (ret < 0) {
697 dev_err(dev, "failed to get host clock\n");
698 return ret;
699 }
700
701 /* set to max rate */
702 priv->mclk = clk_set_rate(&clk, ULONG_MAX);
703 if (IS_ERR_VALUE(priv->mclk)) {
704 dev_err(dev, "failed to set rate for host clock\n");
705 clk_free(&clk);
706 return priv->mclk;
707 }
708
709 ret = clk_enable(&clk);
710 clk_free(&clk);
711 if (ret) {
712 dev_err(dev, "failed to enable host clock\n");
713 return ret;
714 }
715
716 plat->cfg.name = dev->name;
717 plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
718
719 switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
720 1)) {
721 case 8:
722 plat->cfg.host_caps |= MMC_MODE_8BIT;
723 break;
724 case 4:
725 plat->cfg.host_caps |= MMC_MODE_4BIT;
726 break;
727 case 1:
728 break;
729 default:
730 dev_err(dev, "Invalid \"bus-width\" value\n");
731 return -EINVAL;
732 }
733
734 if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
735 NULL))
736 priv->caps |= UNIPHIER_SD_CAP_NONREMOVABLE;
737
738 priv->version = uniphier_sd_readl(priv, UNIPHIER_SD_VERSION) &
739 UNIPHIER_SD_VERSION_IP;
740 dev_dbg(dev, "version %x\n", priv->version);
741 if (priv->version >= 0x10) {
742 priv->caps |= UNIPHIER_SD_CAP_DMA_INTERNAL;
743 priv->caps |= UNIPHIER_SD_CAP_DIV1024;
744 }
745
746 uniphier_sd_host_init(priv);
747
748 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
749 plat->cfg.f_min = priv->mclk /
750 (priv->caps & UNIPHIER_SD_CAP_DIV1024 ? 1024 : 512);
751 plat->cfg.f_max = priv->mclk;
752 plat->cfg.b_max = U32_MAX; /* max value of UNIPHIER_SD_SECCNT */
753
754 upriv->mmc = &plat->mmc;
755
756 return 0;
757 }
758
759 static const struct udevice_id uniphier_sd_match[] = {
760 { .compatible = "socionext,uniphier-sdhc" },
761 { /* sentinel */ }
762 };
763
764 U_BOOT_DRIVER(uniphier_mmc) = {
765 .name = "uniphier-mmc",
766 .id = UCLASS_MMC,
767 .of_match = uniphier_sd_match,
768 .bind = uniphier_sd_bind,
769 .probe = uniphier_sd_probe,
770 .priv_auto_alloc_size = sizeof(struct uniphier_sd_priv),
771 .platdata_auto_alloc_size = sizeof(struct uniphier_sd_plat),
772 .ops = &uniphier_sd_ops,
773 };
"Das U-Boot" Source Tree