2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
8 * Add Programmable Multibit ECC support for various AT91 SoC
9 * (C) Copyright 2012 ATMEL, Hong Xu
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/gpio.h>
21 #include <linux/mtd/nand_ecc.h>
23 #ifdef CONFIG_ATMEL_NAND_HWECC
25 /* Register access macros */
26 #define ecc_readl(add, reg) \
27 readl(add + ATMEL_ECC_##reg)
28 #define ecc_writel(add, reg, value) \
29 writel((value), add + ATMEL_ECC_##reg)
31 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
33 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
35 #ifdef CONFIG_SPL_BUILD
36 #undef CONFIG_SYS_NAND_ONFI_DETECTION
39 struct atmel_nand_host
{
40 struct pmecc_regs __iomem
*pmecc
;
41 struct pmecc_errloc_regs __iomem
*pmerrloc
;
42 void __iomem
*pmecc_rom_base
;
45 u16 pmecc_sector_size
;
46 u32 pmecc_index_table_offset
;
49 int pmecc_bytes_per_sector
;
50 int pmecc_sector_number
;
51 int pmecc_degree
; /* Degree of remainders */
52 int pmecc_cw_len
; /* Length of codeword */
54 /* lookup table for alpha_to and index_of */
55 void __iomem
*pmecc_alpha_to
;
56 void __iomem
*pmecc_index_of
;
58 /* data for pmecc computation */
60 int16_t *pmecc_partial_syn
;
62 int16_t *pmecc_lmu
; /* polynomal order */
68 static struct atmel_nand_host pmecc_host
;
69 static struct nand_ecclayout atmel_pmecc_oobinfo
;
72 * Return number of ecc bytes per sector according to sector size and
73 * correction capability
75 * Following table shows what at91 PMECC supported:
76 * Correction Capability Sector_512_bytes Sector_1024_bytes
77 * ===================== ================ =================
78 * 2-bits 4-bytes 4-bytes
79 * 4-bits 7-bytes 7-bytes
80 * 8-bits 13-bytes 14-bytes
81 * 12-bits 20-bytes 21-bytes
82 * 24-bits 39-bytes 42-bytes
83 * 32-bits 52-bytes 56-bytes
85 static int pmecc_get_ecc_bytes(int cap
, int sector_size
)
87 int m
= 12 + sector_size
/ 512;
88 return (m
* cap
+ 7) / 8;
91 static void pmecc_config_ecc_layout(struct nand_ecclayout
*layout
,
92 int oobsize
, int ecc_len
)
96 layout
->eccbytes
= ecc_len
;
98 /* ECC will occupy the last ecc_len bytes continuously */
99 for (i
= 0; i
< ecc_len
; i
++)
100 layout
->eccpos
[i
] = oobsize
- ecc_len
+ i
;
102 layout
->oobfree
[0].offset
= 2;
103 layout
->oobfree
[0].length
=
104 oobsize
- ecc_len
- layout
->oobfree
[0].offset
;
107 static void __iomem
*pmecc_get_alpha_to(struct atmel_nand_host
*host
)
111 table_size
= host
->pmecc_sector_size
== 512 ?
112 PMECC_INDEX_TABLE_SIZE_512
: PMECC_INDEX_TABLE_SIZE_1024
;
114 /* the ALPHA lookup table is right behind the INDEX lookup table. */
115 return host
->pmecc_rom_base
+ host
->pmecc_index_table_offset
+
116 table_size
* sizeof(int16_t);
119 static void pmecc_data_free(struct atmel_nand_host
*host
)
121 free(host
->pmecc_partial_syn
);
122 free(host
->pmecc_si
);
123 free(host
->pmecc_lmu
);
124 free(host
->pmecc_smu
);
125 free(host
->pmecc_mu
);
126 free(host
->pmecc_dmu
);
127 free(host
->pmecc_delta
);
130 static int pmecc_data_alloc(struct atmel_nand_host
*host
)
132 const int cap
= host
->pmecc_corr_cap
;
135 size
= (2 * cap
+ 1) * sizeof(int16_t);
136 host
->pmecc_partial_syn
= malloc(size
);
137 host
->pmecc_si
= malloc(size
);
138 host
->pmecc_lmu
= malloc((cap
+ 1) * sizeof(int16_t));
139 host
->pmecc_smu
= malloc((cap
+ 2) * size
);
141 size
= (cap
+ 1) * sizeof(int);
142 host
->pmecc_mu
= malloc(size
);
143 host
->pmecc_dmu
= malloc(size
);
144 host
->pmecc_delta
= malloc(size
);
146 if (host
->pmecc_partial_syn
&&
156 pmecc_data_free(host
);
161 static void pmecc_gen_syndrome(struct mtd_info
*mtd
, int sector
)
163 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
164 struct atmel_nand_host
*host
= nand_get_controller_data(nand_chip
);
168 /* Fill odd syndromes */
169 for (i
= 0; i
< host
->pmecc_corr_cap
; i
++) {
170 value
= pmecc_readl(host
->pmecc
, rem_port
[sector
].rem
[i
/ 2]);
174 host
->pmecc_partial_syn
[(2 * i
) + 1] = (int16_t)value
;
178 static void pmecc_substitute(struct mtd_info
*mtd
)
180 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
181 struct atmel_nand_host
*host
= nand_get_controller_data(nand_chip
);
182 int16_t __iomem
*alpha_to
= host
->pmecc_alpha_to
;
183 int16_t __iomem
*index_of
= host
->pmecc_index_of
;
184 int16_t *partial_syn
= host
->pmecc_partial_syn
;
185 const int cap
= host
->pmecc_corr_cap
;
189 /* si[] is a table that holds the current syndrome value,
190 * an element of that table belongs to the field
194 memset(&si
[1], 0, sizeof(int16_t) * (2 * cap
- 1));
196 /* Computation 2t syndromes based on S(x) */
198 for (i
= 1; i
< 2 * cap
; i
+= 2) {
199 for (j
= 0; j
< host
->pmecc_degree
; j
++) {
200 if (partial_syn
[i
] & (0x1 << j
))
201 si
[i
] = readw(alpha_to
+ i
* j
) ^ si
[i
];
204 /* Even syndrome = (Odd syndrome) ** 2 */
205 for (i
= 2, j
= 1; j
<= cap
; i
= ++j
<< 1) {
211 tmp
= readw(index_of
+ si
[j
]);
212 tmp
= (tmp
* 2) % host
->pmecc_cw_len
;
213 si
[i
] = readw(alpha_to
+ tmp
);
219 * This function defines a Berlekamp iterative procedure for
220 * finding the value of the error location polynomial.
221 * The input is si[], initialize by pmecc_substitute().
222 * The output is smu[][].
224 * This function is written according to chip datasheet Chapter:
225 * Find the Error Location Polynomial Sigma(x) of Section:
226 * Programmable Multibit ECC Control (PMECC).
228 static void pmecc_get_sigma(struct mtd_info
*mtd
)
230 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
231 struct atmel_nand_host
*host
= nand_get_controller_data(nand_chip
);
233 int16_t *lmu
= host
->pmecc_lmu
;
234 int16_t *si
= host
->pmecc_si
;
235 int *mu
= host
->pmecc_mu
;
236 int *dmu
= host
->pmecc_dmu
; /* Discrepancy */
237 int *delta
= host
->pmecc_delta
; /* Delta order */
238 int cw_len
= host
->pmecc_cw_len
;
239 const int16_t cap
= host
->pmecc_corr_cap
;
240 const int num
= 2 * cap
+ 1;
241 int16_t __iomem
*index_of
= host
->pmecc_index_of
;
242 int16_t __iomem
*alpha_to
= host
->pmecc_alpha_to
;
244 uint32_t dmu_0_count
, tmp
;
245 int16_t *smu
= host
->pmecc_smu
;
247 /* index of largest delta */
252 /* Init the Sigma(x) */
253 memset(smu
, 0, sizeof(int16_t) * ARRAY_SIZE(smu
));
264 /* discrepancy set to 1 */
266 /* polynom order set to 0 */
268 /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
275 /* Sigma(x) set to 1 */
278 /* discrepancy set to S1 */
281 /* polynom order set to 0 */
284 /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
287 for (i
= 1; i
<= cap
; i
++) {
289 /* Begin Computing Sigma (Mu+1) and L(mu) */
290 /* check if discrepancy is set to 0 */
294 tmp
= ((cap
- (lmu
[i
] >> 1) - 1) / 2);
295 if ((cap
- (lmu
[i
] >> 1) - 1) & 0x1)
300 if (dmu_0_count
== tmp
) {
301 for (j
= 0; j
<= (lmu
[i
] >> 1) + 1; j
++)
302 smu
[(cap
+ 1) * num
+ j
] =
305 lmu
[cap
+ 1] = lmu
[i
];
310 for (j
= 0; j
<= lmu
[i
] >> 1; j
++)
311 smu
[(i
+ 1) * num
+ j
] = smu
[i
* num
+ j
];
313 /* copy previous polynom order to the next */
318 /* find largest delta with dmu != 0 */
319 for (j
= 0; j
< i
; j
++) {
320 if ((dmu
[j
]) && (delta
[j
] > largest
)) {
326 /* compute difference */
327 diff
= (mu
[i
] - mu
[ro
]);
329 /* Compute degree of the new smu polynomial */
330 if ((lmu
[i
] >> 1) > ((lmu
[ro
] >> 1) + diff
))
333 lmu
[i
+ 1] = ((lmu
[ro
] >> 1) + diff
) * 2;
335 /* Init smu[i+1] with 0 */
336 for (k
= 0; k
< num
; k
++)
337 smu
[(i
+ 1) * num
+ k
] = 0;
339 /* Compute smu[i+1] */
340 for (k
= 0; k
<= lmu
[ro
] >> 1; k
++) {
343 if (!(smu
[ro
* num
+ k
] && dmu
[i
]))
345 a
= readw(index_of
+ dmu
[i
]);
346 b
= readw(index_of
+ dmu
[ro
]);
347 c
= readw(index_of
+ smu
[ro
* num
+ k
]);
348 tmp
= a
+ (cw_len
- b
) + c
;
349 a
= readw(alpha_to
+ tmp
% cw_len
);
350 smu
[(i
+ 1) * num
+ (k
+ diff
)] = a
;
353 for (k
= 0; k
<= lmu
[i
] >> 1; k
++)
354 smu
[(i
+ 1) * num
+ k
] ^= smu
[i
* num
+ k
];
357 /* End Computing Sigma (Mu+1) and L(mu) */
358 /* In either case compute delta */
359 delta
[i
+ 1] = (mu
[i
+ 1] * 2 - lmu
[i
+ 1]) >> 1;
361 /* Do not compute discrepancy for the last iteration */
365 for (k
= 0; k
<= (lmu
[i
+ 1] >> 1); k
++) {
368 dmu
[i
+ 1] = si
[tmp
+ 3];
369 } else if (smu
[(i
+ 1) * num
+ k
] && si
[tmp
+ 3 - k
]) {
372 smu
[(i
+ 1) * num
+ k
]);
373 b
= si
[2 * (i
- 1) + 3 - k
];
374 c
= readw(index_of
+ b
);
377 dmu
[i
+ 1] = readw(alpha_to
+ tmp
) ^
384 static int pmecc_err_location(struct mtd_info
*mtd
)
386 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
387 struct atmel_nand_host
*host
= nand_get_controller_data(nand_chip
);
388 const int cap
= host
->pmecc_corr_cap
;
389 const int num
= 2 * cap
+ 1;
390 int sector_size
= host
->pmecc_sector_size
;
391 int err_nbr
= 0; /* number of error */
392 int roots_nbr
; /* number of roots */
395 int16_t *smu
= host
->pmecc_smu
;
396 int timeout
= PMECC_MAX_TIMEOUT_US
;
398 pmecc_writel(host
->pmerrloc
, eldis
, PMERRLOC_DISABLE
);
400 for (i
= 0; i
<= host
->pmecc_lmu
[cap
+ 1] >> 1; i
++) {
401 pmecc_writel(host
->pmerrloc
, sigma
[i
],
402 smu
[(cap
+ 1) * num
+ i
]);
406 val
= PMERRLOC_ELCFG_NUM_ERRORS(err_nbr
- 1);
407 if (sector_size
== 1024)
408 val
|= PMERRLOC_ELCFG_SECTOR_1024
;
410 pmecc_writel(host
->pmerrloc
, elcfg
, val
);
411 pmecc_writel(host
->pmerrloc
, elen
,
412 sector_size
* 8 + host
->pmecc_degree
* cap
);
415 if (pmecc_readl(host
->pmerrloc
, elisr
) & PMERRLOC_CALC_DONE
)
422 dev_err(host
->dev
, "atmel_nand : Timeout to calculate PMECC error location\n");
426 roots_nbr
= (pmecc_readl(host
->pmerrloc
, elisr
) & PMERRLOC_ERR_NUM_MASK
)
428 /* Number of roots == degree of smu hence <= cap */
429 if (roots_nbr
== host
->pmecc_lmu
[cap
+ 1] >> 1)
432 /* Number of roots does not match the degree of smu
433 * unable to correct error */
437 static void pmecc_correct_data(struct mtd_info
*mtd
, uint8_t *buf
, uint8_t *ecc
,
438 int sector_num
, int extra_bytes
, int err_nbr
)
440 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
441 struct atmel_nand_host
*host
= nand_get_controller_data(nand_chip
);
443 int byte_pos
, bit_pos
, sector_size
, pos
;
447 sector_size
= host
->pmecc_sector_size
;
450 tmp
= pmecc_readl(host
->pmerrloc
, el
[i
]) - 1;
454 if (byte_pos
>= (sector_size
+ extra_bytes
))
455 BUG(); /* should never happen */
457 if (byte_pos
< sector_size
) {
458 err_byte
= *(buf
+ byte_pos
);
459 *(buf
+ byte_pos
) ^= (1 << bit_pos
);
461 pos
= sector_num
* host
->pmecc_sector_size
+ byte_pos
;
462 dev_dbg(host
->dev
, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
463 pos
, bit_pos
, err_byte
, *(buf
+ byte_pos
));
465 /* Bit flip in OOB area */
466 tmp
= sector_num
* host
->pmecc_bytes_per_sector
467 + (byte_pos
- sector_size
);
469 ecc
[tmp
] ^= (1 << bit_pos
);
471 pos
= tmp
+ nand_chip
->ecc
.layout
->eccpos
[0];
472 dev_dbg(host
->dev
, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
473 pos
, bit_pos
, err_byte
, ecc
[tmp
]);
483 static int pmecc_correction(struct mtd_info
*mtd
, u32 pmecc_stat
, uint8_t *buf
,
486 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
487 struct atmel_nand_host
*host
= nand_get_controller_data(nand_chip
);
488 int i
, err_nbr
, eccbytes
;
491 /* SAMA5D4 PMECC IP can correct errors for all 0xff page */
492 if (host
->pmecc_version
>= PMECC_VERSION_SAMA5D4
)
495 eccbytes
= nand_chip
->ecc
.bytes
;
496 for (i
= 0; i
< eccbytes
; i
++)
499 /* Erased page, return OK */
503 for (i
= 0; i
< host
->pmecc_sector_number
; i
++) {
505 if (pmecc_stat
& 0x1) {
506 buf_pos
= buf
+ i
* host
->pmecc_sector_size
;
508 pmecc_gen_syndrome(mtd
, i
);
509 pmecc_substitute(mtd
);
510 pmecc_get_sigma(mtd
);
512 err_nbr
= pmecc_err_location(mtd
);
514 dev_err(host
->dev
, "PMECC: Too many errors\n");
515 mtd
->ecc_stats
.failed
++;
518 pmecc_correct_data(mtd
, buf_pos
, ecc
, i
,
519 host
->pmecc_bytes_per_sector
, err_nbr
);
520 mtd
->ecc_stats
.corrected
+= err_nbr
;
529 static int atmel_nand_pmecc_read_page(struct mtd_info
*mtd
,
530 struct nand_chip
*chip
, uint8_t *buf
, int oob_required
, int page
)
532 struct atmel_nand_host
*host
= nand_get_controller_data(chip
);
533 int eccsize
= chip
->ecc
.size
;
534 uint8_t *oob
= chip
->oob_poi
;
535 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
537 int timeout
= PMECC_MAX_TIMEOUT_US
;
539 pmecc_writel(host
->pmecc
, ctrl
, PMECC_CTRL_RST
);
540 pmecc_writel(host
->pmecc
, ctrl
, PMECC_CTRL_DISABLE
);
541 pmecc_writel(host
->pmecc
, cfg
, ((pmecc_readl(host
->pmecc
, cfg
))
542 & ~PMECC_CFG_WRITE_OP
) | PMECC_CFG_AUTO_ENABLE
);
544 pmecc_writel(host
->pmecc
, ctrl
, PMECC_CTRL_ENABLE
);
545 pmecc_writel(host
->pmecc
, ctrl
, PMECC_CTRL_DATA
);
547 chip
->read_buf(mtd
, buf
, eccsize
);
548 chip
->read_buf(mtd
, oob
, mtd
->oobsize
);
551 if (!(pmecc_readl(host
->pmecc
, sr
) & PMECC_SR_BUSY
))
558 dev_err(host
->dev
, "atmel_nand : Timeout to read PMECC page\n");
562 stat
= pmecc_readl(host
->pmecc
, isr
);
564 if (pmecc_correction(mtd
, stat
, buf
, &oob
[eccpos
[0]]) != 0)
570 static int atmel_nand_pmecc_write_page(struct mtd_info
*mtd
,
571 struct nand_chip
*chip
, const uint8_t *buf
,
572 int oob_required
, int page
)
574 struct atmel_nand_host
*host
= nand_get_controller_data(chip
);
575 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
577 int timeout
= PMECC_MAX_TIMEOUT_US
;
579 pmecc_writel(host
->pmecc
, ctrl
, PMECC_CTRL_RST
);
580 pmecc_writel(host
->pmecc
, ctrl
, PMECC_CTRL_DISABLE
);
582 pmecc_writel(host
->pmecc
, cfg
, (pmecc_readl(host
->pmecc
, cfg
) |
583 PMECC_CFG_WRITE_OP
) & ~PMECC_CFG_AUTO_ENABLE
);
585 pmecc_writel(host
->pmecc
, ctrl
, PMECC_CTRL_ENABLE
);
586 pmecc_writel(host
->pmecc
, ctrl
, PMECC_CTRL_DATA
);
588 chip
->write_buf(mtd
, (u8
*)buf
, mtd
->writesize
);
591 if (!(pmecc_readl(host
->pmecc
, sr
) & PMECC_SR_BUSY
))
598 dev_err(host
->dev
, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
602 for (i
= 0; i
< host
->pmecc_sector_number
; i
++) {
603 for (j
= 0; j
< host
->pmecc_bytes_per_sector
; j
++) {
606 pos
= i
* host
->pmecc_bytes_per_sector
+ j
;
607 chip
->oob_poi
[eccpos
[pos
]] =
608 pmecc_readb(host
->pmecc
, ecc_port
[i
].ecc
[j
]);
611 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
616 static void atmel_pmecc_core_init(struct mtd_info
*mtd
)
618 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
619 struct atmel_nand_host
*host
= nand_get_controller_data(nand_chip
);
621 struct nand_ecclayout
*ecc_layout
;
623 pmecc_writel(host
->pmecc
, ctrl
, PMECC_CTRL_RST
);
624 pmecc_writel(host
->pmecc
, ctrl
, PMECC_CTRL_DISABLE
);
626 switch (host
->pmecc_corr_cap
) {
628 val
= PMECC_CFG_BCH_ERR2
;
631 val
= PMECC_CFG_BCH_ERR4
;
634 val
= PMECC_CFG_BCH_ERR8
;
637 val
= PMECC_CFG_BCH_ERR12
;
640 val
= PMECC_CFG_BCH_ERR24
;
643 val
= PMECC_CFG_BCH_ERR32
;
647 if (host
->pmecc_sector_size
== 512)
648 val
|= PMECC_CFG_SECTOR512
;
649 else if (host
->pmecc_sector_size
== 1024)
650 val
|= PMECC_CFG_SECTOR1024
;
652 switch (host
->pmecc_sector_number
) {
654 val
|= PMECC_CFG_PAGE_1SECTOR
;
657 val
|= PMECC_CFG_PAGE_2SECTORS
;
660 val
|= PMECC_CFG_PAGE_4SECTORS
;
663 val
|= PMECC_CFG_PAGE_8SECTORS
;
667 val
|= (PMECC_CFG_READ_OP
| PMECC_CFG_SPARE_DISABLE
668 | PMECC_CFG_AUTO_DISABLE
);
669 pmecc_writel(host
->pmecc
, cfg
, val
);
671 ecc_layout
= nand_chip
->ecc
.layout
;
672 pmecc_writel(host
->pmecc
, sarea
, mtd
->oobsize
- 1);
673 pmecc_writel(host
->pmecc
, saddr
, ecc_layout
->eccpos
[0]);
674 pmecc_writel(host
->pmecc
, eaddr
,
675 ecc_layout
->eccpos
[ecc_layout
->eccbytes
- 1]);
676 /* See datasheet about PMECC Clock Control Register */
677 pmecc_writel(host
->pmecc
, clk
, PMECC_CLK_133MHZ
);
678 pmecc_writel(host
->pmecc
, idr
, 0xff);
679 pmecc_writel(host
->pmecc
, ctrl
, PMECC_CTRL_ENABLE
);
682 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
684 * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
685 * pmecc_corr_cap or pmecc_sector_size is 0, then set it as
686 * ONFI ECC parameters.
687 * @host: point to an atmel_nand_host structure.
688 * if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
689 * if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
690 * @chip: point to an nand_chip structure.
691 * @cap: store the ONFI ECC correct bits capbility
692 * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
694 * Return 0 if success. otherwise return the error code.
696 static int pmecc_choose_ecc(struct atmel_nand_host
*host
,
697 struct nand_chip
*chip
,
698 int *cap
, int *sector_size
)
700 /* Get ECC requirement from ONFI parameters */
701 *cap
= *sector_size
= 0;
702 if (chip
->onfi_version
) {
703 *cap
= chip
->ecc_strength_ds
;
704 *sector_size
= chip
->ecc_step_ds
;
705 MTDDEBUG(MTD_DEBUG_LEVEL1
, "ONFI params, minimum required ECC: %d bits in %d bytes\n",
709 if (*cap
== 0 && *sector_size
== 0) {
710 /* Non-ONFI compliant */
711 dev_info(host
->dev
, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes\n");
716 /* If head file doesn't specify then use the one in ONFI parameters */
717 if (host
->pmecc_corr_cap
== 0) {
718 /* use the most fitable ecc bits (the near bigger one ) */
720 host
->pmecc_corr_cap
= 2;
722 host
->pmecc_corr_cap
= 4;
724 host
->pmecc_corr_cap
= 8;
726 host
->pmecc_corr_cap
= 12;
728 host
->pmecc_corr_cap
= 24;
730 #ifdef CONFIG_SAMA5D2
731 host
->pmecc_corr_cap
= 32;
733 host
->pmecc_corr_cap
= 24;
736 if (host
->pmecc_sector_size
== 0) {
737 /* use the most fitable sector size (the near smaller one ) */
738 if (*sector_size
>= 1024)
739 host
->pmecc_sector_size
= 1024;
740 else if (*sector_size
>= 512)
741 host
->pmecc_sector_size
= 512;
749 #if defined(NO_GALOIS_TABLE_IN_ROM)
750 static uint16_t *pmecc_galois_table
;
751 static inline int deg(unsigned int poly
)
753 /* polynomial degree is the most-significant bit index */
754 return fls(poly
) - 1;
757 static int build_gf_tables(int mm
, unsigned int poly
,
758 int16_t *index_of
, int16_t *alpha_to
)
760 unsigned int i
, x
= 1;
761 const unsigned int k
= 1 << deg(poly
);
762 unsigned int nn
= (1 << mm
) - 1;
764 /* primitive polynomial must be of degree m */
768 for (i
= 0; i
< nn
; i
++) {
772 /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
785 static uint16_t *create_lookup_table(int sector_size
)
787 int degree
= (sector_size
== 512) ?
788 PMECC_GF_DIMENSION_13
:
789 PMECC_GF_DIMENSION_14
;
790 unsigned int poly
= (sector_size
== 512) ?
791 PMECC_GF_13_PRIMITIVE_POLY
:
792 PMECC_GF_14_PRIMITIVE_POLY
;
793 int table_size
= (sector_size
== 512) ?
794 PMECC_INDEX_TABLE_SIZE_512
:
795 PMECC_INDEX_TABLE_SIZE_1024
;
797 int16_t *addr
= kzalloc(2 * table_size
* sizeof(uint16_t), GFP_KERNEL
);
798 if (addr
&& build_gf_tables(degree
, poly
, addr
, addr
+ table_size
))
801 return (uint16_t *)addr
;
805 static int atmel_pmecc_nand_init_params(struct nand_chip
*nand
,
806 struct mtd_info
*mtd
)
808 struct atmel_nand_host
*host
;
809 int cap
, sector_size
;
812 nand_set_controller_data(nand
, host
);
814 nand
->ecc
.mode
= NAND_ECC_HW
;
815 nand
->ecc
.calculate
= NULL
;
816 nand
->ecc
.correct
= NULL
;
817 nand
->ecc
.hwctl
= NULL
;
819 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
820 host
->pmecc_corr_cap
= host
->pmecc_sector_size
= 0;
822 #ifdef CONFIG_PMECC_CAP
823 host
->pmecc_corr_cap
= CONFIG_PMECC_CAP
;
825 #ifdef CONFIG_PMECC_SECTOR_SIZE
826 host
->pmecc_sector_size
= CONFIG_PMECC_SECTOR_SIZE
;
828 /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
829 * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
832 if (pmecc_choose_ecc(host
, nand
, &cap
, §or_size
)) {
833 dev_err(host
->dev
, "Required ECC %d bits in %d bytes not supported!\n",
838 if (cap
> host
->pmecc_corr_cap
)
839 dev_info(host
->dev
, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
840 host
->pmecc_corr_cap
, cap
);
841 if (sector_size
< host
->pmecc_sector_size
)
842 dev_info(host
->dev
, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
843 host
->pmecc_sector_size
, sector_size
);
844 #else /* CONFIG_SYS_NAND_ONFI_DETECTION */
845 host
->pmecc_corr_cap
= CONFIG_PMECC_CAP
;
846 host
->pmecc_sector_size
= CONFIG_PMECC_SECTOR_SIZE
;
849 cap
= host
->pmecc_corr_cap
;
850 sector_size
= host
->pmecc_sector_size
;
852 /* TODO: need check whether cap & sector_size is validate */
853 #if defined(NO_GALOIS_TABLE_IN_ROM)
855 * As pmecc_rom_base is the begin of the gallois field table, So the
856 * index offset just set as 0.
858 host
->pmecc_index_table_offset
= 0;
860 if (host
->pmecc_sector_size
== 512)
861 host
->pmecc_index_table_offset
= ATMEL_PMECC_INDEX_OFFSET_512
;
863 host
->pmecc_index_table_offset
= ATMEL_PMECC_INDEX_OFFSET_1024
;
866 MTDDEBUG(MTD_DEBUG_LEVEL1
,
867 "Initialize PMECC params, cap: %d, sector: %d\n",
870 host
->pmecc
= (struct pmecc_regs __iomem
*) ATMEL_BASE_PMECC
;
871 host
->pmerrloc
= (struct pmecc_errloc_regs __iomem
*)
873 #if defined(NO_GALOIS_TABLE_IN_ROM)
874 pmecc_galois_table
= create_lookup_table(host
->pmecc_sector_size
);
875 if (!pmecc_galois_table
) {
876 dev_err(host
->dev
, "out of memory\n");
880 host
->pmecc_rom_base
= (void __iomem
*)pmecc_galois_table
;
882 host
->pmecc_rom_base
= (void __iomem
*) ATMEL_BASE_ROM
;
885 /* ECC is calculated for the whole page (1 step) */
886 nand
->ecc
.size
= mtd
->writesize
;
888 /* set ECC page size and oob layout */
889 switch (mtd
->writesize
) {
893 host
->pmecc_degree
= (sector_size
== 512) ?
894 PMECC_GF_DIMENSION_13
: PMECC_GF_DIMENSION_14
;
895 host
->pmecc_cw_len
= (1 << host
->pmecc_degree
) - 1;
896 host
->pmecc_sector_number
= mtd
->writesize
/ sector_size
;
897 host
->pmecc_bytes_per_sector
= pmecc_get_ecc_bytes(
899 host
->pmecc_alpha_to
= pmecc_get_alpha_to(host
);
900 host
->pmecc_index_of
= host
->pmecc_rom_base
+
901 host
->pmecc_index_table_offset
;
904 nand
->ecc
.bytes
= host
->pmecc_bytes_per_sector
*
905 host
->pmecc_sector_number
;
907 if (nand
->ecc
.bytes
> MTD_MAX_ECCPOS_ENTRIES_LARGE
) {
908 dev_err(host
->dev
, "too large eccpos entries. max support ecc.bytes is %d\n",
909 MTD_MAX_ECCPOS_ENTRIES_LARGE
);
913 if (nand
->ecc
.bytes
> mtd
->oobsize
- PMECC_OOB_RESERVED_BYTES
) {
914 dev_err(host
->dev
, "No room for ECC bytes\n");
917 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo
,
920 nand
->ecc
.layout
= &atmel_pmecc_oobinfo
;
925 dev_err(host
->dev
, "Unsupported page size for PMECC, use Software ECC\n");
927 /* page size not handled by HW ECC */
928 /* switching back to soft ECC */
929 nand
->ecc
.mode
= NAND_ECC_SOFT
;
930 nand
->ecc
.read_page
= NULL
;
931 nand
->ecc
.postpad
= 0;
932 nand
->ecc
.prepad
= 0;
937 /* Allocate data for PMECC computation */
938 if (pmecc_data_alloc(host
)) {
939 dev_err(host
->dev
, "Cannot allocate memory for PMECC computation!\n");
943 nand
->options
|= NAND_NO_SUBPAGE_WRITE
;
944 nand
->ecc
.read_page
= atmel_nand_pmecc_read_page
;
945 nand
->ecc
.write_page
= atmel_nand_pmecc_write_page
;
946 nand
->ecc
.strength
= cap
;
948 /* Check the PMECC ip version */
949 host
->pmecc_version
= pmecc_readl(host
->pmerrloc
, version
);
950 dev_dbg(host
->dev
, "PMECC IP version is: %x\n", host
->pmecc_version
);
952 atmel_pmecc_core_init(mtd
);
959 /* oob layout for large page size
960 * bad block info is on bytes 0 and 1
961 * the bytes have to be consecutives to avoid
962 * several NAND_CMD_RNDOUT during read
964 static struct nand_ecclayout atmel_oobinfo_large
= {
966 .eccpos
= {60, 61, 62, 63},
972 /* oob layout for small page size
973 * bad block info is on bytes 4 and 5
974 * the bytes have to be consecutives to avoid
975 * several NAND_CMD_RNDOUT during read
977 static struct nand_ecclayout atmel_oobinfo_small
= {
979 .eccpos
= {0, 1, 2, 3},
988 * function called after a write
990 * mtd: MTD block structure
991 * dat: raw data (unused)
992 * ecc_code: buffer for ECC
994 static int atmel_nand_calculate(struct mtd_info
*mtd
,
995 const u_char
*dat
, unsigned char *ecc_code
)
997 unsigned int ecc_value
;
999 /* get the first 2 ECC bytes */
1000 ecc_value
= ecc_readl(CONFIG_SYS_NAND_ECC_BASE
, PR
);
1002 ecc_code
[0] = ecc_value
& 0xFF;
1003 ecc_code
[1] = (ecc_value
>> 8) & 0xFF;
1005 /* get the last 2 ECC bytes */
1006 ecc_value
= ecc_readl(CONFIG_SYS_NAND_ECC_BASE
, NPR
) & ATMEL_ECC_NPARITY
;
1008 ecc_code
[2] = ecc_value
& 0xFF;
1009 ecc_code
[3] = (ecc_value
>> 8) & 0xFF;
1015 * HW ECC read page function
1017 * mtd: mtd info structure
1018 * chip: nand chip info structure
1019 * buf: buffer to store read data
1020 * oob_required: caller expects OOB data read to chip->oob_poi
1022 static int atmel_nand_read_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1023 uint8_t *buf
, int oob_required
, int page
)
1025 int eccsize
= chip
->ecc
.size
;
1026 int eccbytes
= chip
->ecc
.bytes
;
1027 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1029 uint8_t *oob
= chip
->oob_poi
;
1034 chip
->read_buf(mtd
, p
, eccsize
);
1036 /* move to ECC position if needed */
1037 if (eccpos
[0] != 0) {
1038 /* This only works on large pages
1039 * because the ECC controller waits for
1040 * NAND_CMD_RNDOUTSTART after the
1042 * anyway, for small pages, the eccpos[0] == 0
1044 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1045 mtd
->writesize
+ eccpos
[0], -1);
1048 /* the ECC controller needs to read the ECC just after the data */
1049 ecc_pos
= oob
+ eccpos
[0];
1050 chip
->read_buf(mtd
, ecc_pos
, eccbytes
);
1052 /* check if there's an error */
1053 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
1056 mtd
->ecc_stats
.failed
++;
1058 mtd
->ecc_stats
.corrected
+= stat
;
1060 /* get back to oob start (end of page) */
1061 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, mtd
->writesize
, -1);
1064 chip
->read_buf(mtd
, oob
, mtd
->oobsize
);
1072 * function called after a read
1074 * mtd: MTD block structure
1075 * dat: raw data read from the chip
1076 * read_ecc: ECC from the chip (unused)
1079 * Detect and correct a 1 bit error for a page
1081 static int atmel_nand_correct(struct mtd_info
*mtd
, u_char
*dat
,
1082 u_char
*read_ecc
, u_char
*isnull
)
1084 struct nand_chip
*nand_chip
= mtd_to_nand(mtd
);
1085 unsigned int ecc_status
;
1086 unsigned int ecc_word
, ecc_bit
;
1088 /* get the status from the Status Register */
1089 ecc_status
= ecc_readl(CONFIG_SYS_NAND_ECC_BASE
, SR
);
1091 /* if there's no error */
1092 if (likely(!(ecc_status
& ATMEL_ECC_RECERR
)))
1095 /* get error bit offset (4 bits) */
1096 ecc_bit
= ecc_readl(CONFIG_SYS_NAND_ECC_BASE
, PR
) & ATMEL_ECC_BITADDR
;
1097 /* get word address (12 bits) */
1098 ecc_word
= ecc_readl(CONFIG_SYS_NAND_ECC_BASE
, PR
) & ATMEL_ECC_WORDADDR
;
1101 /* if there are multiple errors */
1102 if (ecc_status
& ATMEL_ECC_MULERR
) {
1103 /* check if it is a freshly erased block
1104 * (filled with 0xff) */
1105 if ((ecc_bit
== ATMEL_ECC_BITADDR
)
1106 && (ecc_word
== (ATMEL_ECC_WORDADDR
>> 4))) {
1107 /* the block has just been erased, return OK */
1110 /* it doesn't seems to be a freshly
1112 * We can't correct so many errors */
1113 dev_warn(host
->dev
, "atmel_nand : multiple errors detected."
1114 " Unable to correct.\n");
1118 /* if there's a single bit error : we can correct it */
1119 if (ecc_status
& ATMEL_ECC_ECCERR
) {
1120 /* there's nothing much to do here.
1121 * the bit error is on the ECC itself.
1123 dev_warn(host
->dev
, "atmel_nand : one bit error on ECC code."
1124 " Nothing to correct\n");
1128 dev_warn(host
->dev
, "atmel_nand : one bit error on data."
1129 " (word offset in the page :"
1130 " 0x%x bit offset : 0x%x)\n",
1132 /* correct the error */
1133 if (nand_chip
->options
& NAND_BUSWIDTH_16
) {
1135 ((unsigned short *) dat
)[ecc_word
] ^= (1 << ecc_bit
);
1138 dat
[ecc_word
] ^= (1 << ecc_bit
);
1140 dev_warn(host
->dev
, "atmel_nand : error corrected\n");
1145 * Enable HW ECC : unused on most chips
1147 static void atmel_nand_hwctl(struct mtd_info
*mtd
, int mode
)
1151 int atmel_hwecc_nand_init_param(struct nand_chip
*nand
, struct mtd_info
*mtd
)
1153 nand
->ecc
.mode
= NAND_ECC_HW
;
1154 nand
->ecc
.calculate
= atmel_nand_calculate
;
1155 nand
->ecc
.correct
= atmel_nand_correct
;
1156 nand
->ecc
.hwctl
= atmel_nand_hwctl
;
1157 nand
->ecc
.read_page
= atmel_nand_read_page
;
1158 nand
->ecc
.bytes
= 4;
1159 nand
->ecc
.strength
= 4;
1161 if (nand
->ecc
.mode
== NAND_ECC_HW
) {
1162 /* ECC is calculated for the whole page (1 step) */
1163 nand
->ecc
.size
= mtd
->writesize
;
1165 /* set ECC page size and oob layout */
1166 switch (mtd
->writesize
) {
1168 nand
->ecc
.layout
= &atmel_oobinfo_small
;
1169 ecc_writel(CONFIG_SYS_NAND_ECC_BASE
, MR
,
1170 ATMEL_ECC_PAGESIZE_528
);
1173 nand
->ecc
.layout
= &atmel_oobinfo_large
;
1174 ecc_writel(CONFIG_SYS_NAND_ECC_BASE
, MR
,
1175 ATMEL_ECC_PAGESIZE_1056
);
1178 nand
->ecc
.layout
= &atmel_oobinfo_large
;
1179 ecc_writel(CONFIG_SYS_NAND_ECC_BASE
, MR
,
1180 ATMEL_ECC_PAGESIZE_2112
);
1183 nand
->ecc
.layout
= &atmel_oobinfo_large
;
1184 ecc_writel(CONFIG_SYS_NAND_ECC_BASE
, MR
,
1185 ATMEL_ECC_PAGESIZE_4224
);
1188 /* page size not handled by HW ECC */
1189 /* switching back to soft ECC */
1190 nand
->ecc
.mode
= NAND_ECC_SOFT
;
1191 nand
->ecc
.calculate
= NULL
;
1192 nand
->ecc
.correct
= NULL
;
1193 nand
->ecc
.hwctl
= NULL
;
1194 nand
->ecc
.read_page
= NULL
;
1195 nand
->ecc
.postpad
= 0;
1196 nand
->ecc
.prepad
= 0;
1197 nand
->ecc
.bytes
= 0;
1205 #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1207 #endif /* CONFIG_ATMEL_NAND_HWECC */
1209 static void at91_nand_hwcontrol(struct mtd_info
*mtd
,
1210 int cmd
, unsigned int ctrl
)
1212 struct nand_chip
*this = mtd_to_nand(mtd
);
1214 if (ctrl
& NAND_CTRL_CHANGE
) {
1215 ulong IO_ADDR_W
= (ulong
) this->IO_ADDR_W
;
1216 IO_ADDR_W
&= ~(CONFIG_SYS_NAND_MASK_ALE
1217 | CONFIG_SYS_NAND_MASK_CLE
);
1219 if (ctrl
& NAND_CLE
)
1220 IO_ADDR_W
|= CONFIG_SYS_NAND_MASK_CLE
;
1221 if (ctrl
& NAND_ALE
)
1222 IO_ADDR_W
|= CONFIG_SYS_NAND_MASK_ALE
;
1224 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
1225 gpio_set_value(CONFIG_SYS_NAND_ENABLE_PIN
, !(ctrl
& NAND_NCE
));
1227 this->IO_ADDR_W
= (void *) IO_ADDR_W
;
1230 if (cmd
!= NAND_CMD_NONE
)
1231 writeb(cmd
, this->IO_ADDR_W
);
1234 #ifdef CONFIG_SYS_NAND_READY_PIN
1235 static int at91_nand_ready(struct mtd_info
*mtd
)
1237 return gpio_get_value(CONFIG_SYS_NAND_READY_PIN
);
1241 #ifdef CONFIG_SPL_BUILD
1242 /* The following code is for SPL */
1243 static struct mtd_info
*mtd
;
1244 static struct nand_chip nand_chip
;
1246 static int nand_command(int block
, int page
, uint32_t offs
, u8 cmd
)
1248 struct nand_chip
*this = mtd_to_nand(mtd
);
1249 int page_addr
= page
+ block
* CONFIG_SYS_NAND_PAGE_COUNT
;
1250 void (*hwctrl
)(struct mtd_info
*mtd
, int cmd
,
1251 unsigned int ctrl
) = this->cmd_ctrl
;
1253 while (!this->dev_ready(mtd
))
1256 if (cmd
== NAND_CMD_READOOB
) {
1257 offs
+= CONFIG_SYS_NAND_PAGE_SIZE
;
1258 cmd
= NAND_CMD_READ0
;
1261 hwctrl(mtd
, cmd
, NAND_CTRL_CLE
| NAND_CTRL_CHANGE
);
1263 if ((this->options
& NAND_BUSWIDTH_16
) && !nand_opcode_8bits(cmd
))
1266 hwctrl(mtd
, offs
& 0xff, NAND_CTRL_ALE
| NAND_CTRL_CHANGE
);
1267 hwctrl(mtd
, (offs
>> 8) & 0xff, NAND_CTRL_ALE
);
1268 hwctrl(mtd
, (page_addr
& 0xff), NAND_CTRL_ALE
);
1269 hwctrl(mtd
, ((page_addr
>> 8) & 0xff), NAND_CTRL_ALE
);
1270 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1271 hwctrl(mtd
, (page_addr
>> 16) & 0x0f, NAND_CTRL_ALE
);
1273 hwctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
1275 hwctrl(mtd
, NAND_CMD_READSTART
, NAND_CTRL_CLE
| NAND_CTRL_CHANGE
);
1276 hwctrl(mtd
, NAND_CMD_NONE
, NAND_NCE
| NAND_CTRL_CHANGE
);
1278 while (!this->dev_ready(mtd
))
1284 static int nand_is_bad_block(int block
)
1286 struct nand_chip
*this = mtd_to_nand(mtd
);
1288 nand_command(block
, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS
, NAND_CMD_READOOB
);
1290 if (this->options
& NAND_BUSWIDTH_16
) {
1291 if (readw(this->IO_ADDR_R
) != 0xffff)
1294 if (readb(this->IO_ADDR_R
) != 0xff)
1301 #ifdef CONFIG_SPL_NAND_ECC
1302 static int nand_ecc_pos
[] = CONFIG_SYS_NAND_ECCPOS
;
1303 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
1304 CONFIG_SYS_NAND_ECCSIZE)
1305 #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
1307 static int nand_read_page(int block
, int page
, void *dst
)
1309 struct nand_chip
*this = mtd_to_nand(mtd
);
1310 u_char ecc_calc
[ECCTOTAL
];
1311 u_char ecc_code
[ECCTOTAL
];
1312 u_char oob_data
[CONFIG_SYS_NAND_OOBSIZE
];
1313 int eccsize
= CONFIG_SYS_NAND_ECCSIZE
;
1314 int eccbytes
= CONFIG_SYS_NAND_ECCBYTES
;
1315 int eccsteps
= ECCSTEPS
;
1318 nand_command(block
, page
, 0, NAND_CMD_READ0
);
1320 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
) {
1321 if (this->ecc
.mode
!= NAND_ECC_SOFT
)
1322 this->ecc
.hwctl(mtd
, NAND_ECC_READ
);
1323 this->read_buf(mtd
, p
, eccsize
);
1324 this->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
1326 this->read_buf(mtd
, oob_data
, CONFIG_SYS_NAND_OOBSIZE
);
1328 for (i
= 0; i
< ECCTOTAL
; i
++)
1329 ecc_code
[i
] = oob_data
[nand_ecc_pos
[i
]];
1331 eccsteps
= ECCSTEPS
;
1334 for (i
= 0; eccsteps
; eccsteps
--, i
+= eccbytes
, p
+= eccsize
)
1335 this->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
1340 int spl_nand_erase_one(int block
, int page
)
1342 struct nand_chip
*this = mtd_to_nand(mtd
);
1343 void (*hwctrl
)(struct mtd_info
*mtd
, int cmd
,
1344 unsigned int ctrl
) = this->cmd_ctrl
;
1347 if (nand_chip
.select_chip
)
1348 nand_chip
.select_chip(mtd
, 0);
1350 page_addr
= page
+ block
* CONFIG_SYS_NAND_PAGE_COUNT
;
1351 hwctrl(mtd
, NAND_CMD_ERASE1
, NAND_CTRL_CLE
| NAND_CTRL_CHANGE
);
1353 hwctrl(mtd
, (page_addr
& 0xff), NAND_CTRL_ALE
| NAND_CTRL_CHANGE
);
1354 hwctrl(mtd
, ((page_addr
>> 8) & 0xff),
1355 NAND_CTRL_ALE
| NAND_CTRL_CHANGE
);
1356 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1357 /* One more address cycle for devices > 128MiB */
1358 hwctrl(mtd
, (page_addr
>> 16) & 0x0f,
1359 NAND_CTRL_ALE
| NAND_CTRL_CHANGE
);
1361 hwctrl(mtd
, NAND_CMD_ERASE2
, NAND_CTRL_CLE
| NAND_CTRL_CHANGE
);
1363 while (!this->dev_ready(mtd
))
1371 static int nand_read_page(int block
, int page
, void *dst
)
1373 struct nand_chip
*this = mtd_to_nand(mtd
);
1375 nand_command(block
, page
, 0, NAND_CMD_READ0
);
1376 atmel_nand_pmecc_read_page(mtd
, this, dst
, 0, page
);
1380 #endif /* CONFIG_SPL_NAND_ECC */
1382 int nand_spl_load_image(uint32_t offs
, unsigned int size
, void *dst
)
1384 unsigned int block
, lastblock
;
1387 block
= offs
/ CONFIG_SYS_NAND_BLOCK_SIZE
;
1388 lastblock
= (offs
+ size
- 1) / CONFIG_SYS_NAND_BLOCK_SIZE
;
1389 page
= (offs
% CONFIG_SYS_NAND_BLOCK_SIZE
) / CONFIG_SYS_NAND_PAGE_SIZE
;
1391 while (block
<= lastblock
) {
1392 if (!nand_is_bad_block(block
)) {
1393 while (page
< CONFIG_SYS_NAND_PAGE_COUNT
) {
1394 nand_read_page(block
, page
, dst
);
1395 dst
+= CONFIG_SYS_NAND_PAGE_SIZE
;
1410 int at91_nand_wait_ready(struct mtd_info
*mtd
)
1412 struct nand_chip
*this = mtd_to_nand(mtd
);
1414 udelay(this->chip_delay
);
1419 int board_nand_init(struct nand_chip
*nand
)
1423 nand
->ecc
.mode
= NAND_ECC_SOFT
;
1424 #ifdef CONFIG_SYS_NAND_DBW_16
1425 nand
->options
= NAND_BUSWIDTH_16
;
1426 nand
->read_buf
= nand_read_buf16
;
1428 nand
->read_buf
= nand_read_buf
;
1430 nand
->cmd_ctrl
= at91_nand_hwcontrol
;
1431 #ifdef CONFIG_SYS_NAND_READY_PIN
1432 nand
->dev_ready
= at91_nand_ready
;
1434 nand
->dev_ready
= at91_nand_wait_ready
;
1436 nand
->chip_delay
= 20;
1437 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1438 nand
->bbt_options
|= NAND_BBT_USE_FLASH
;
1441 #ifdef CONFIG_ATMEL_NAND_HWECC
1442 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1443 ret
= atmel_pmecc_nand_init_params(nand
, mtd
);
1450 void nand_init(void)
1452 mtd
= &nand_chip
.mtd
;
1453 mtd
->writesize
= CONFIG_SYS_NAND_PAGE_SIZE
;
1454 mtd
->oobsize
= CONFIG_SYS_NAND_OOBSIZE
;
1455 nand_chip
.IO_ADDR_R
= (void __iomem
*)CONFIG_SYS_NAND_BASE
;
1456 nand_chip
.IO_ADDR_W
= (void __iomem
*)CONFIG_SYS_NAND_BASE
;
1457 board_nand_init(&nand_chip
);
1459 #ifdef CONFIG_SPL_NAND_ECC
1460 if (nand_chip
.ecc
.mode
== NAND_ECC_SOFT
) {
1461 nand_chip
.ecc
.calculate
= nand_calculate_ecc
;
1462 nand_chip
.ecc
.correct
= nand_correct_data
;
1466 if (nand_chip
.select_chip
)
1467 nand_chip
.select_chip(mtd
, 0);
1470 void nand_deselect(void)
1472 if (nand_chip
.select_chip
)
1473 nand_chip
.select_chip(mtd
, -1);
1478 #ifndef CONFIG_SYS_NAND_BASE_LIST
1479 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1481 static struct nand_chip nand_chip
[CONFIG_SYS_MAX_NAND_DEVICE
];
1482 static ulong base_addr
[CONFIG_SYS_MAX_NAND_DEVICE
] = CONFIG_SYS_NAND_BASE_LIST
;
1484 int atmel_nand_chip_init(int devnum
, ulong base_addr
)
1487 struct nand_chip
*nand
= &nand_chip
[devnum
];
1488 struct mtd_info
*mtd
= nand_to_mtd(nand
);
1490 nand
->IO_ADDR_R
= nand
->IO_ADDR_W
= (void __iomem
*)base_addr
;
1492 #ifdef CONFIG_NAND_ECC_BCH
1493 nand
->ecc
.mode
= NAND_ECC_SOFT_BCH
;
1495 nand
->ecc
.mode
= NAND_ECC_SOFT
;
1497 #ifdef CONFIG_SYS_NAND_DBW_16
1498 nand
->options
= NAND_BUSWIDTH_16
;
1500 nand
->cmd_ctrl
= at91_nand_hwcontrol
;
1501 #ifdef CONFIG_SYS_NAND_READY_PIN
1502 nand
->dev_ready
= at91_nand_ready
;
1504 nand
->chip_delay
= 75;
1505 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1506 nand
->bbt_options
|= NAND_BBT_USE_FLASH
;
1509 ret
= nand_scan_ident(mtd
, CONFIG_SYS_NAND_MAX_CHIPS
, NULL
);
1513 #ifdef CONFIG_ATMEL_NAND_HWECC
1514 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1515 ret
= atmel_pmecc_nand_init_params(nand
, mtd
);
1517 ret
= atmel_hwecc_nand_init_param(nand
, mtd
);
1523 ret
= nand_scan_tail(mtd
);
1525 nand_register(devnum
, mtd
);
1530 void board_nand_init(void)
1533 for (i
= 0; i
< CONFIG_SYS_MAX_NAND_DEVICE
; i
++)
1534 if (atmel_nand_chip_init(i
, base_addr
[i
]))
1535 dev_err(host
->dev
, "atmel_nand: Fail to initialize #%d chip",
1538 #endif /* CONFIG_SPL_BUILD */