]>
git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/mtd/nand/kmeter1_nand.c
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de
5 * SPDX-License-Identifier: GPL-2.0+
12 #define CONFIG_NAND_MODE_REG (void *)(CONFIG_SYS_NAND_BASE + 0x20000)
13 #define CONFIG_NAND_DATA_REG (void *)(CONFIG_SYS_NAND_BASE + 0x30000)
15 #define read_mode() in_8(CONFIG_NAND_MODE_REG)
16 #define write_mode(val) out_8(CONFIG_NAND_MODE_REG, val)
17 #define read_data() in_8(CONFIG_NAND_DATA_REG)
18 #define write_data(val) out_8(CONFIG_NAND_DATA_REG, val)
20 #define KPN_RDY2 (1 << 7)
21 #define KPN_RDY1 (1 << 6)
22 #define KPN_WPN (1 << 4)
23 #define KPN_CE2N (1 << 3)
24 #define KPN_CE1N (1 << 2)
25 #define KPN_ALE (1 << 1)
26 #define KPN_CLE (1 << 0)
28 #define KPN_DEFAULT_CHIP_DELAY 50
30 static int kpn_chip_ready(void)
32 if (read_mode() & KPN_RDY1
)
38 static void kpn_wait_rdy(void)
42 while (--cnt
&& !kpn_chip_ready())
46 printf ("timeout while waiting for RDY\n");
49 static void kpn_nand_hwcontrol(struct mtd_info
*mtd
, int cmd
, unsigned int ctrl
)
51 u8 reg_val
= read_mode();
53 if (ctrl
& NAND_CTRL_CHANGE
) {
54 reg_val
= reg_val
& ~(KPN_ALE
+ KPN_CLE
);
57 reg_val
= reg_val
| KPN_CLE
;
59 reg_val
= reg_val
| KPN_ALE
;
61 reg_val
= reg_val
& ~KPN_CE1N
;
63 reg_val
= reg_val
| KPN_CE1N
;
67 if (cmd
!= NAND_CMD_NONE
)
70 /* wait until flash is ready */
74 static u_char
kpn_nand_read_byte(struct mtd_info
*mtd
)
79 static void kpn_nand_write_buf(struct mtd_info
*mtd
, const u_char
*buf
, int len
)
83 for (i
= 0; i
< len
; i
++) {
89 static void kpn_nand_read_buf(struct mtd_info
*mtd
, u_char
*buf
, int len
)
93 for (i
= 0; i
< len
; i
++)
97 static int kpn_nand_dev_ready(struct mtd_info
*mtd
)
104 int board_nand_init(struct nand_chip
*nand
)
106 #if defined(CONFIG_NAND_ECC_BCH)
107 nand
->ecc
.mode
= NAND_ECC_SOFT_BCH
;
109 nand
->ecc
.mode
= NAND_ECC_SOFT
;
112 /* Reference hardware control function */
113 nand
->cmd_ctrl
= kpn_nand_hwcontrol
;
114 nand
->read_byte
= kpn_nand_read_byte
;
115 nand
->write_buf
= kpn_nand_write_buf
;
116 nand
->read_buf
= kpn_nand_read_buf
;
117 nand
->dev_ready
= kpn_nand_dev_ready
;
118 nand
->chip_delay
= KPN_DEFAULT_CHIP_DELAY
;
120 /* reset mode register */
121 write_mode(KPN_CE1N
+ KPN_CE2N
+ KPN_WPN
);