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[people/ms/u-boot.git] / drivers / mtd / nand / tegra_nand.c
1 /*
2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
4 * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
5 * (C) Copyright 2006 DENX Software Engineering
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #include <common.h>
11 #include <asm/io.h>
12 #include <nand.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/funcmux.h>
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/errno.h>
17 #include <asm/gpio.h>
18 #include <fdtdec.h>
19 #include "tegra_nand.h"
20
21 DECLARE_GLOBAL_DATA_PTR;
22
23 #define NAND_CMD_TIMEOUT_MS 10
24
25 #define SKIPPED_SPARE_BYTES 4
26
27 /* ECC bytes to be generated for tag data */
28 #define TAG_ECC_BYTES 4
29
30 /* 64 byte oob block info for large page (== 2KB) device
31 *
32 * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
33 * Skipped bytes(4)
34 * Main area Ecc(36)
35 * Tag data(20)
36 * Tag data Ecc(4)
37 *
38 * Yaffs2 will use 16 tag bytes.
39 */
40 static struct nand_ecclayout eccoob = {
41 .eccbytes = 36,
42 .eccpos = {
43 4, 5, 6, 7, 8, 9, 10, 11, 12,
44 13, 14, 15, 16, 17, 18, 19, 20, 21,
45 22, 23, 24, 25, 26, 27, 28, 29, 30,
46 31, 32, 33, 34, 35, 36, 37, 38, 39,
47 },
48 .oobavail = 20,
49 .oobfree = {
50 {
51 .offset = 40,
52 .length = 20,
53 },
54 }
55 };
56
57 enum {
58 ECC_OK,
59 ECC_TAG_ERROR = 1 << 0,
60 ECC_DATA_ERROR = 1 << 1
61 };
62
63 /* Timing parameters */
64 enum {
65 FDT_NAND_MAX_TRP_TREA,
66 FDT_NAND_TWB,
67 FDT_NAND_MAX_TCR_TAR_TRR,
68 FDT_NAND_TWHR,
69 FDT_NAND_MAX_TCS_TCH_TALS_TALH,
70 FDT_NAND_TWH,
71 FDT_NAND_TWP,
72 FDT_NAND_TRH,
73 FDT_NAND_TADL,
74
75 FDT_NAND_TIMING_COUNT
76 };
77
78 /* Information about an attached NAND chip */
79 struct fdt_nand {
80 struct nand_ctlr *reg;
81 int enabled; /* 1 to enable, 0 to disable */
82 struct fdt_gpio_state wp_gpio; /* write-protect GPIO */
83 s32 width; /* bit width, normally 8 */
84 u32 timing[FDT_NAND_TIMING_COUNT];
85 };
86
87 struct nand_drv {
88 struct nand_ctlr *reg;
89
90 /*
91 * When running in PIO mode to get READ ID bytes from register
92 * RESP_0, we need this variable as an index to know which byte in
93 * register RESP_0 should be read.
94 * Because common code in nand_base.c invokes read_byte function two
95 * times for NAND_CMD_READID.
96 * And our controller returns 4 bytes at once in register RESP_0.
97 */
98 int pio_byte_index;
99 struct fdt_nand config;
100 };
101
102 static struct nand_drv nand_ctrl;
103 static struct mtd_info *our_mtd;
104 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
105
106 #ifdef CONFIG_SYS_DCACHE_OFF
107 static inline void dma_prepare(void *start, unsigned long length,
108 int is_writing)
109 {
110 }
111 #else
112 /**
113 * Prepare for a DMA transaction
114 *
115 * For a write we flush out our data. For a read we invalidate, since we
116 * need to do this before we read from the buffer after the DMA has
117 * completed, so may as well do it now.
118 *
119 * @param start Start address for DMA buffer (should be cache-aligned)
120 * @param length Length of DMA buffer in bytes
121 * @param is_writing 0 if reading, non-zero if writing
122 */
123 static void dma_prepare(void *start, unsigned long length, int is_writing)
124 {
125 unsigned long addr = (unsigned long)start;
126
127 length = ALIGN(length, ARCH_DMA_MINALIGN);
128 if (is_writing)
129 flush_dcache_range(addr, addr + length);
130 else
131 invalidate_dcache_range(addr, addr + length);
132 }
133 #endif
134
135 /**
136 * Wait for command completion
137 *
138 * @param reg nand_ctlr structure
139 * @return
140 * 1 - Command completed
141 * 0 - Timeout
142 */
143 static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
144 {
145 u32 reg_val;
146 int running;
147 int i;
148
149 for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) {
150 if ((readl(&reg->command) & CMD_GO) ||
151 !(readl(&reg->status) & STATUS_RBSY0) ||
152 !(readl(&reg->isr) & ISR_IS_CMD_DONE)) {
153 udelay(1);
154 continue;
155 }
156 reg_val = readl(&reg->dma_mst_ctrl);
157 /*
158 * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE
159 * is set, that means DMA engine is running.
160 *
161 * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE
162 * is cleared, indicating DMA transfer completion.
163 */
164 running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE |
165 DMA_MST_CTRL_EN_B_ENABLE);
166 if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE))
167 return 1;
168 udelay(1);
169 }
170 return 0;
171 }
172
173 /**
174 * Read one byte from the chip
175 *
176 * @param mtd MTD device structure
177 * @return data byte
178 *
179 * Read function for 8bit bus-width
180 */
181 static uint8_t read_byte(struct mtd_info *mtd)
182 {
183 struct nand_chip *chip = mtd->priv;
184 u32 dword_read;
185 struct nand_drv *info;
186
187 info = (struct nand_drv *)chip->priv;
188
189 /* In PIO mode, only 4 bytes can be transferred with single CMD_GO. */
190 if (info->pio_byte_index > 3) {
191 info->pio_byte_index = 0;
192 writel(CMD_GO | CMD_PIO
193 | CMD_RX | CMD_CE0,
194 &info->reg->command);
195 if (!nand_waitfor_cmd_completion(info->reg))
196 printf("Command timeout\n");
197 }
198
199 dword_read = readl(&info->reg->resp);
200 dword_read = dword_read >> (8 * info->pio_byte_index);
201 info->pio_byte_index++;
202 return (uint8_t)dword_read;
203 }
204
205 /**
206 * Read len bytes from the chip into a buffer
207 *
208 * @param mtd MTD device structure
209 * @param buf buffer to store data to
210 * @param len number of bytes to read
211 *
212 * Read function for 8bit bus-width
213 */
214 static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
215 {
216 int i, s;
217 unsigned int reg;
218 struct nand_chip *chip = mtd->priv;
219 struct nand_drv *info = (struct nand_drv *)chip->priv;
220
221 for (i = 0; i < len; i += 4) {
222 s = (len - i) > 4 ? 4 : len - i;
223 writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 |
224 ((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO,
225 &info->reg->command);
226 if (!nand_waitfor_cmd_completion(info->reg))
227 puts("Command timeout during read_buf\n");
228 reg = readl(&info->reg->resp);
229 memcpy(buf + i, &reg, s);
230 }
231 }
232
233 /**
234 * Check NAND status to see if it is ready or not
235 *
236 * @param mtd MTD device structure
237 * @return
238 * 1 - ready
239 * 0 - not ready
240 */
241 static int nand_dev_ready(struct mtd_info *mtd)
242 {
243 struct nand_chip *chip = mtd->priv;
244 int reg_val;
245 struct nand_drv *info;
246
247 info = (struct nand_drv *)chip->priv;
248
249 reg_val = readl(&info->reg->status);
250 if (reg_val & STATUS_RBSY0)
251 return 1;
252 else
253 return 0;
254 }
255
256 /* Dummy implementation: we don't support multiple chips */
257 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
258 {
259 switch (chipnr) {
260 case -1:
261 case 0:
262 break;
263
264 default:
265 BUG();
266 }
267 }
268
269 /**
270 * Clear all interrupt status bits
271 *
272 * @param reg nand_ctlr structure
273 */
274 static void nand_clear_interrupt_status(struct nand_ctlr *reg)
275 {
276 u32 reg_val;
277
278 /* Clear interrupt status */
279 reg_val = readl(&reg->isr);
280 writel(reg_val, &reg->isr);
281 }
282
283 /**
284 * Send command to NAND device
285 *
286 * @param mtd MTD device structure
287 * @param command the command to be sent
288 * @param column the column address for this command, -1 if none
289 * @param page_addr the page address for this command, -1 if none
290 */
291 static void nand_command(struct mtd_info *mtd, unsigned int command,
292 int column, int page_addr)
293 {
294 struct nand_chip *chip = mtd->priv;
295 struct nand_drv *info;
296
297 info = (struct nand_drv *)chip->priv;
298
299 /*
300 * Write out the command to the device.
301 *
302 * Only command NAND_CMD_RESET or NAND_CMD_READID will come
303 * here before mtd->writesize is initialized.
304 */
305
306 /* Emulate NAND_CMD_READOOB */
307 if (command == NAND_CMD_READOOB) {
308 assert(mtd->writesize != 0);
309 column += mtd->writesize;
310 command = NAND_CMD_READ0;
311 }
312
313 /* Adjust columns for 16 bit bus-width */
314 if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
315 column >>= 1;
316
317 nand_clear_interrupt_status(info->reg);
318
319 /* Stop DMA engine, clear DMA completion status */
320 writel(DMA_MST_CTRL_EN_A_DISABLE
321 | DMA_MST_CTRL_EN_B_DISABLE
322 | DMA_MST_CTRL_IS_DMA_DONE,
323 &info->reg->dma_mst_ctrl);
324
325 /*
326 * Program and erase have their own busy handlers
327 * status and sequential in needs no delay
328 */
329 switch (command) {
330 case NAND_CMD_READID:
331 writel(NAND_CMD_READID, &info->reg->cmd_reg1);
332 writel(column & 0xFF, &info->reg->addr_reg1);
333 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_PIO
334 | CMD_RX |
335 ((4 - 1) << CMD_TRANS_SIZE_SHIFT)
336 | CMD_CE0,
337 &info->reg->command);
338 info->pio_byte_index = 0;
339 break;
340 case NAND_CMD_PARAM:
341 writel(NAND_CMD_PARAM, &info->reg->cmd_reg1);
342 writel(column & 0xFF, &info->reg->addr_reg1);
343 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
344 &info->reg->command);
345 break;
346 case NAND_CMD_READ0:
347 writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
348 writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
349 writel((page_addr << 16) | (column & 0xFFFF),
350 &info->reg->addr_reg1);
351 writel(page_addr >> 16, &info->reg->addr_reg2);
352 return;
353 case NAND_CMD_SEQIN:
354 writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1);
355 writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2);
356 writel((page_addr << 16) | (column & 0xFFFF),
357 &info->reg->addr_reg1);
358 writel(page_addr >> 16,
359 &info->reg->addr_reg2);
360 return;
361 case NAND_CMD_PAGEPROG:
362 return;
363 case NAND_CMD_ERASE1:
364 writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1);
365 writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2);
366 writel(page_addr, &info->reg->addr_reg1);
367 writel(CMD_GO | CMD_CLE | CMD_ALE |
368 CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3,
369 &info->reg->command);
370 break;
371 case NAND_CMD_ERASE2:
372 return;
373 case NAND_CMD_STATUS:
374 writel(NAND_CMD_STATUS, &info->reg->cmd_reg1);
375 writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX
376 | ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
377 | CMD_CE0,
378 &info->reg->command);
379 info->pio_byte_index = 0;
380 break;
381 case NAND_CMD_RESET:
382 writel(NAND_CMD_RESET, &info->reg->cmd_reg1);
383 writel(CMD_GO | CMD_CLE | CMD_CE0,
384 &info->reg->command);
385 break;
386 case NAND_CMD_RNDOUT:
387 default:
388 printf("%s: Unsupported command %d\n", __func__, command);
389 return;
390 }
391 if (!nand_waitfor_cmd_completion(info->reg))
392 printf("Command 0x%02X timeout\n", command);
393 }
394
395 /**
396 * Check whether the pointed buffer are all 0xff (blank).
397 *
398 * @param buf data buffer for blank check
399 * @param len length of the buffer in byte
400 * @return
401 * 1 - blank
402 * 0 - non-blank
403 */
404 static int blank_check(u8 *buf, int len)
405 {
406 int i;
407
408 for (i = 0; i < len; i++)
409 if (buf[i] != 0xFF)
410 return 0;
411 return 1;
412 }
413
414 /**
415 * After a DMA transfer for read, we call this function to see whether there
416 * is any uncorrectable error on the pointed data buffer or oob buffer.
417 *
418 * @param reg nand_ctlr structure
419 * @param databuf data buffer
420 * @param a_len data buffer length
421 * @param oobbuf oob buffer
422 * @param b_len oob buffer length
423 * @return
424 * ECC_OK - no ECC error or correctable ECC error
425 * ECC_TAG_ERROR - uncorrectable tag ECC error
426 * ECC_DATA_ERROR - uncorrectable data ECC error
427 * ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error
428 */
429 static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf,
430 int a_len, u8 *oobbuf, int b_len)
431 {
432 int return_val = ECC_OK;
433 u32 reg_val;
434
435 if (!(readl(&reg->isr) & ISR_IS_ECC_ERR))
436 return ECC_OK;
437
438 /*
439 * Area A is used for the data block (databuf). Area B is used for
440 * the spare block (oobbuf)
441 */
442 reg_val = readl(&reg->dec_status);
443 if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) {
444 reg_val = readl(&reg->bch_dec_status_buf);
445 /*
446 * If uncorrectable error occurs on data area, then see whether
447 * they are all FF. If all are FF, it's a blank page.
448 * Not error.
449 */
450 if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) &&
451 !blank_check(databuf, a_len))
452 return_val |= ECC_DATA_ERROR;
453 }
454
455 if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) {
456 reg_val = readl(&reg->bch_dec_status_buf);
457 /*
458 * If uncorrectable error occurs on tag area, then see whether
459 * they are all FF. If all are FF, it's a blank page.
460 * Not error.
461 */
462 if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) &&
463 !blank_check(oobbuf, b_len))
464 return_val |= ECC_TAG_ERROR;
465 }
466
467 return return_val;
468 }
469
470 /**
471 * Set GO bit to send command to device
472 *
473 * @param reg nand_ctlr structure
474 */
475 static void start_command(struct nand_ctlr *reg)
476 {
477 u32 reg_val;
478
479 reg_val = readl(&reg->command);
480 reg_val |= CMD_GO;
481 writel(reg_val, &reg->command);
482 }
483
484 /**
485 * Clear command GO bit, DMA GO bit, and DMA completion status
486 *
487 * @param reg nand_ctlr structure
488 */
489 static void stop_command(struct nand_ctlr *reg)
490 {
491 /* Stop command */
492 writel(0, &reg->command);
493
494 /* Stop DMA engine and clear DMA completion status */
495 writel(DMA_MST_CTRL_GO_DISABLE
496 | DMA_MST_CTRL_IS_DMA_DONE,
497 &reg->dma_mst_ctrl);
498 }
499
500 /**
501 * Set up NAND bus width and page size
502 *
503 * @param info nand_info structure
504 * @param *reg_val address of reg_val
505 * @return 0 if ok, -1 on error
506 */
507 static int set_bus_width_page_size(struct fdt_nand *config,
508 u32 *reg_val)
509 {
510 if (config->width == 8)
511 *reg_val = CFG_BUS_WIDTH_8BIT;
512 else if (config->width == 16)
513 *reg_val = CFG_BUS_WIDTH_16BIT;
514 else {
515 debug("%s: Unsupported bus width %d\n", __func__,
516 config->width);
517 return -1;
518 }
519
520 if (our_mtd->writesize == 512)
521 *reg_val |= CFG_PAGE_SIZE_512;
522 else if (our_mtd->writesize == 2048)
523 *reg_val |= CFG_PAGE_SIZE_2048;
524 else if (our_mtd->writesize == 4096)
525 *reg_val |= CFG_PAGE_SIZE_4096;
526 else {
527 debug("%s: Unsupported page size %d\n", __func__,
528 our_mtd->writesize);
529 return -1;
530 }
531
532 return 0;
533 }
534
535 /**
536 * Page read/write function
537 *
538 * @param mtd mtd info structure
539 * @param chip nand chip info structure
540 * @param buf data buffer
541 * @param page page number
542 * @param with_ecc 1 to enable ECC, 0 to disable ECC
543 * @param is_writing 0 for read, 1 for write
544 * @return 0 when successfully completed
545 * -EIO when command timeout
546 */
547 static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
548 uint8_t *buf, int page, int with_ecc, int is_writing)
549 {
550 u32 reg_val;
551 int tag_size;
552 struct nand_oobfree *free = chip->ecc.layout->oobfree;
553 /* 4*128=512 (byte) is the value that our HW can support. */
554 ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128);
555 char *tag_ptr;
556 struct nand_drv *info;
557 struct fdt_nand *config;
558
559 if ((uintptr_t)buf & 0x03) {
560 printf("buf %p has to be 4-byte aligned\n", buf);
561 return -EINVAL;
562 }
563
564 info = (struct nand_drv *)chip->priv;
565 config = &info->config;
566 if (set_bus_width_page_size(config, &reg_val))
567 return -EINVAL;
568
569 /* Need to be 4-byte aligned */
570 tag_ptr = (char *)tag_buf;
571
572 stop_command(info->reg);
573
574 writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
575 writel(virt_to_phys(buf), &info->reg->data_block_ptr);
576
577 if (with_ecc) {
578 writel(virt_to_phys(tag_ptr), &info->reg->tag_ptr);
579 if (is_writing)
580 memcpy(tag_ptr, chip->oob_poi + free->offset,
581 chip->ecc.layout->oobavail +
582 TAG_ECC_BYTES);
583 } else {
584 writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr);
585 }
586
587 /* Set ECC selection, configure ECC settings */
588 if (with_ecc) {
589 tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
590 reg_val |= (CFG_SKIP_SPARE_SEL_4
591 | CFG_SKIP_SPARE_ENABLE
592 | CFG_HW_ECC_CORRECTION_ENABLE
593 | CFG_ECC_EN_TAG_DISABLE
594 | CFG_HW_ECC_SEL_RS
595 | CFG_HW_ECC_ENABLE
596 | CFG_TVAL4
597 | (tag_size - 1));
598
599 if (!is_writing)
600 tag_size += SKIPPED_SPARE_BYTES;
601 dma_prepare(tag_ptr, tag_size, is_writing);
602 } else {
603 tag_size = mtd->oobsize;
604 reg_val |= (CFG_SKIP_SPARE_DISABLE
605 | CFG_HW_ECC_CORRECTION_DISABLE
606 | CFG_ECC_EN_TAG_DISABLE
607 | CFG_HW_ECC_DISABLE
608 | (tag_size - 1));
609 dma_prepare(chip->oob_poi, tag_size, is_writing);
610 }
611 writel(reg_val, &info->reg->config);
612
613 dma_prepare(buf, 1 << chip->page_shift, is_writing);
614
615 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
616
617 writel(tag_size - 1, &info->reg->dma_cfg_b);
618
619 nand_clear_interrupt_status(info->reg);
620
621 reg_val = CMD_CLE | CMD_ALE
622 | CMD_SEC_CMD
623 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
624 | CMD_A_VALID
625 | CMD_B_VALID
626 | (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT)
627 | CMD_CE0;
628 if (!is_writing)
629 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
630 else
631 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
632 writel(reg_val, &info->reg->command);
633
634 /* Setup DMA engine */
635 reg_val = DMA_MST_CTRL_GO_ENABLE
636 | DMA_MST_CTRL_BURST_8WORDS
637 | DMA_MST_CTRL_EN_A_ENABLE
638 | DMA_MST_CTRL_EN_B_ENABLE;
639
640 if (!is_writing)
641 reg_val |= DMA_MST_CTRL_DIR_READ;
642 else
643 reg_val |= DMA_MST_CTRL_DIR_WRITE;
644
645 writel(reg_val, &info->reg->dma_mst_ctrl);
646
647 start_command(info->reg);
648
649 if (!nand_waitfor_cmd_completion(info->reg)) {
650 if (!is_writing)
651 printf("Read Page 0x%X timeout ", page);
652 else
653 printf("Write Page 0x%X timeout ", page);
654 if (with_ecc)
655 printf("with ECC");
656 else
657 printf("without ECC");
658 printf("\n");
659 return -EIO;
660 }
661
662 if (with_ecc && !is_writing) {
663 memcpy(chip->oob_poi, tag_ptr,
664 SKIPPED_SPARE_BYTES);
665 memcpy(chip->oob_poi + free->offset,
666 tag_ptr + SKIPPED_SPARE_BYTES,
667 chip->ecc.layout->oobavail);
668 reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf,
669 1 << chip->page_shift,
670 (u8 *)(tag_ptr + SKIPPED_SPARE_BYTES),
671 chip->ecc.layout->oobavail);
672 if (reg_val & ECC_TAG_ERROR)
673 printf("Read Page 0x%X tag ECC error\n", page);
674 if (reg_val & ECC_DATA_ERROR)
675 printf("Read Page 0x%X data ECC error\n",
676 page);
677 if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR))
678 return -EIO;
679 }
680 return 0;
681 }
682
683 /**
684 * Hardware ecc based page read function
685 *
686 * @param mtd mtd info structure
687 * @param chip nand chip info structure
688 * @param buf buffer to store read data
689 * @param page page number to read
690 * @return 0 when successfully completed
691 * -EIO when command timeout
692 */
693 static int nand_read_page_hwecc(struct mtd_info *mtd,
694 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
695 {
696 return nand_rw_page(mtd, chip, buf, page, 1, 0);
697 }
698
699 /**
700 * Hardware ecc based page write function
701 *
702 * @param mtd mtd info structure
703 * @param chip nand chip info structure
704 * @param buf data buffer
705 */
706 static int nand_write_page_hwecc(struct mtd_info *mtd,
707 struct nand_chip *chip, const uint8_t *buf, int oob_required)
708 {
709 int page;
710 struct nand_drv *info;
711
712 info = (struct nand_drv *)chip->priv;
713
714 page = (readl(&info->reg->addr_reg1) >> 16) |
715 (readl(&info->reg->addr_reg2) << 16);
716
717 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
718 return 0;
719 }
720
721
722 /**
723 * Read raw page data without ecc
724 *
725 * @param mtd mtd info structure
726 * @param chip nand chip info structure
727 * @param buf buffer to store read data
728 * @param page page number to read
729 * @return 0 when successfully completed
730 * -EINVAL when chip->oob_poi is not double-word aligned
731 * -EIO when command timeout
732 */
733 static int nand_read_page_raw(struct mtd_info *mtd,
734 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
735 {
736 return nand_rw_page(mtd, chip, buf, page, 0, 0);
737 }
738
739 /**
740 * Raw page write function
741 *
742 * @param mtd mtd info structure
743 * @param chip nand chip info structure
744 * @param buf data buffer
745 */
746 static int nand_write_page_raw(struct mtd_info *mtd,
747 struct nand_chip *chip, const uint8_t *buf, int oob_required)
748 {
749 int page;
750 struct nand_drv *info;
751
752 info = (struct nand_drv *)chip->priv;
753 page = (readl(&info->reg->addr_reg1) >> 16) |
754 (readl(&info->reg->addr_reg2) << 16);
755
756 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
757 return 0;
758 }
759
760 /**
761 * OOB data read/write function
762 *
763 * @param mtd mtd info structure
764 * @param chip nand chip info structure
765 * @param page page number to read
766 * @param with_ecc 1 to enable ECC, 0 to disable ECC
767 * @param is_writing 0 for read, 1 for write
768 * @return 0 when successfully completed
769 * -EINVAL when chip->oob_poi is not double-word aligned
770 * -EIO when command timeout
771 */
772 static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
773 int page, int with_ecc, int is_writing)
774 {
775 u32 reg_val;
776 int tag_size;
777 struct nand_oobfree *free = chip->ecc.layout->oobfree;
778 struct nand_drv *info;
779
780 if (((int)chip->oob_poi) & 0x03)
781 return -EINVAL;
782 info = (struct nand_drv *)chip->priv;
783 if (set_bus_width_page_size(&info->config, &reg_val))
784 return -EINVAL;
785
786 stop_command(info->reg);
787
788 writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr);
789
790 /* Set ECC selection */
791 tag_size = mtd->oobsize;
792 if (with_ecc)
793 reg_val |= CFG_ECC_EN_TAG_ENABLE;
794 else
795 reg_val |= (CFG_ECC_EN_TAG_DISABLE);
796
797 reg_val |= ((tag_size - 1) |
798 CFG_SKIP_SPARE_DISABLE |
799 CFG_HW_ECC_CORRECTION_DISABLE |
800 CFG_HW_ECC_DISABLE);
801 writel(reg_val, &info->reg->config);
802
803 dma_prepare(chip->oob_poi, tag_size, is_writing);
804
805 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
806
807 if (is_writing && with_ecc)
808 tag_size -= TAG_ECC_BYTES;
809
810 writel(tag_size - 1, &info->reg->dma_cfg_b);
811
812 nand_clear_interrupt_status(info->reg);
813
814 reg_val = CMD_CLE | CMD_ALE
815 | CMD_SEC_CMD
816 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
817 | CMD_B_VALID
818 | CMD_CE0;
819 if (!is_writing)
820 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
821 else
822 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
823 writel(reg_val, &info->reg->command);
824
825 /* Setup DMA engine */
826 reg_val = DMA_MST_CTRL_GO_ENABLE
827 | DMA_MST_CTRL_BURST_8WORDS
828 | DMA_MST_CTRL_EN_B_ENABLE;
829 if (!is_writing)
830 reg_val |= DMA_MST_CTRL_DIR_READ;
831 else
832 reg_val |= DMA_MST_CTRL_DIR_WRITE;
833
834 writel(reg_val, &info->reg->dma_mst_ctrl);
835
836 start_command(info->reg);
837
838 if (!nand_waitfor_cmd_completion(info->reg)) {
839 if (!is_writing)
840 printf("Read OOB of Page 0x%X timeout\n", page);
841 else
842 printf("Write OOB of Page 0x%X timeout\n", page);
843 return -EIO;
844 }
845
846 if (with_ecc && !is_writing) {
847 reg_val = (u32)check_ecc_error(info->reg, 0, 0,
848 (u8 *)(chip->oob_poi + free->offset),
849 chip->ecc.layout->oobavail);
850 if (reg_val & ECC_TAG_ERROR)
851 printf("Read OOB of Page 0x%X tag ECC error\n", page);
852 }
853 return 0;
854 }
855
856 /**
857 * OOB data read function
858 *
859 * @param mtd mtd info structure
860 * @param chip nand chip info structure
861 * @param page page number to read
862 */
863 static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
864 int page)
865 {
866 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
867 nand_rw_oob(mtd, chip, page, 0, 0);
868 return 0;
869 }
870
871 /**
872 * OOB data write function
873 *
874 * @param mtd mtd info structure
875 * @param chip nand chip info structure
876 * @param page page number to write
877 * @return 0 when successfully completed
878 * -EINVAL when chip->oob_poi is not double-word aligned
879 * -EIO when command timeout
880 */
881 static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
882 int page)
883 {
884 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
885
886 return nand_rw_oob(mtd, chip, page, 0, 1);
887 }
888
889 /**
890 * Set up NAND memory timings according to the provided parameters
891 *
892 * @param timing Timing parameters
893 * @param reg NAND controller register address
894 */
895 static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],
896 struct nand_ctlr *reg)
897 {
898 u32 reg_val, clk_rate, clk_period, time_val;
899
900 clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH,
901 CLOCK_ID_PERIPH) / 1000000;
902 clk_period = 1000 / clk_rate;
903 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
904 TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK;
905 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) <<
906 TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK;
907 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period;
908 if (time_val > 2)
909 reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) &
910 TIMING_TCR_TAR_TRR_CNT_MASK;
911 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) <<
912 TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK;
913 time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period;
914 if (time_val > 1)
915 reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) &
916 TIMING_TCS_CNT_MASK;
917 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) <<
918 TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK;
919 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) <<
920 TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK;
921 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) <<
922 TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK;
923 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
924 TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK;
925 writel(reg_val, &reg->timing);
926
927 reg_val = 0;
928 time_val = timing[FDT_NAND_TADL] / clk_period;
929 if (time_val > 2)
930 reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK;
931 writel(reg_val, &reg->timing2);
932 }
933
934 /**
935 * Decode NAND parameters from the device tree
936 *
937 * @param blob Device tree blob
938 * @param node Node containing "nand-flash" compatble node
939 * @return 0 if ok, -ve on error (FDT_ERR_...)
940 */
941 static int fdt_decode_nand(const void *blob, int node, struct fdt_nand *config)
942 {
943 int err;
944
945 config->reg = (struct nand_ctlr *)fdtdec_get_addr(blob, node, "reg");
946 config->enabled = fdtdec_get_is_enabled(blob, node);
947 config->width = fdtdec_get_int(blob, node, "nvidia,nand-width", 8);
948 err = fdtdec_decode_gpio(blob, node, "nvidia,wp-gpios",
949 &config->wp_gpio);
950 if (err)
951 return err;
952 err = fdtdec_get_int_array(blob, node, "nvidia,timing",
953 config->timing, FDT_NAND_TIMING_COUNT);
954 if (err < 0)
955 return err;
956
957 /* Now look up the controller and decode that */
958 node = fdt_next_node(blob, node, NULL);
959 if (node < 0)
960 return node;
961
962 return 0;
963 }
964
965 /**
966 * Board-specific NAND initialization
967 *
968 * @param nand nand chip info structure
969 * @return 0, after initialized, -1 on error
970 */
971 int tegra_nand_init(struct nand_chip *nand, int devnum)
972 {
973 struct nand_drv *info = &nand_ctrl;
974 struct fdt_nand *config = &info->config;
975 int node, ret;
976
977 node = fdtdec_next_compatible(gd->fdt_blob, 0,
978 COMPAT_NVIDIA_TEGRA20_NAND);
979 if (node < 0)
980 return -1;
981 if (fdt_decode_nand(gd->fdt_blob, node, config)) {
982 printf("Could not decode nand-flash in device tree\n");
983 return -1;
984 }
985 if (!config->enabled)
986 return -1;
987 info->reg = config->reg;
988 nand->ecc.mode = NAND_ECC_HW;
989 nand->ecc.layout = &eccoob;
990
991 nand->options = LP_OPTIONS;
992 nand->cmdfunc = nand_command;
993 nand->read_byte = read_byte;
994 nand->read_buf = read_buf;
995 nand->ecc.read_page = nand_read_page_hwecc;
996 nand->ecc.write_page = nand_write_page_hwecc;
997 nand->ecc.read_page_raw = nand_read_page_raw;
998 nand->ecc.write_page_raw = nand_write_page_raw;
999 nand->ecc.read_oob = nand_read_oob;
1000 nand->ecc.write_oob = nand_write_oob;
1001 nand->ecc.strength = 1;
1002 nand->select_chip = nand_select_chip;
1003 nand->dev_ready = nand_dev_ready;
1004 nand->priv = &nand_ctrl;
1005
1006 /* Adjust controller clock rate */
1007 clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000);
1008
1009 /* Adjust timing for NAND device */
1010 setup_timing(config->timing, info->reg);
1011
1012 fdtdec_setup_gpio(&config->wp_gpio);
1013 gpio_direction_output(config->wp_gpio.gpio, 1);
1014
1015 our_mtd = &nand_info[devnum];
1016 our_mtd->priv = nand;
1017 ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1018 if (ret)
1019 return ret;
1020
1021 nand->ecc.size = our_mtd->writesize;
1022 nand->ecc.bytes = our_mtd->oobsize;
1023
1024 ret = nand_scan_tail(our_mtd);
1025 if (ret)
1026 return ret;
1027
1028 ret = nand_register(devnum);
1029 if (ret)
1030 return ret;
1031
1032 return 0;
1033 }
1034
1035 void board_nand_init(void)
1036 {
1037 struct nand_chip *nand = &nand_chip[0];
1038
1039 if (tegra_nand_init(nand, 0))
1040 puts("Tegra NAND init failed\n");
1041 }
"Das U-Boot" Source Tree