2 * Atheros AR71xx / AR9xxx GMAC driver
4 * Copyright (C) 2016 Marek Vasut <marex@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
14 #include <linux/compiler.h>
15 #include <linux/err.h>
16 #include <linux/mii.h>
20 #include <mach/ath79.h>
22 DECLARE_GLOBAL_DATA_PTR
;
29 #define AG7XXX_ETH_CFG1 0x00
30 #define AG7XXX_ETH_CFG1_SOFT_RST BIT(31)
31 #define AG7XXX_ETH_CFG1_RX_RST BIT(19)
32 #define AG7XXX_ETH_CFG1_TX_RST BIT(18)
33 #define AG7XXX_ETH_CFG1_LOOPBACK BIT(8)
34 #define AG7XXX_ETH_CFG1_RX_EN BIT(2)
35 #define AG7XXX_ETH_CFG1_TX_EN BIT(0)
37 #define AG7XXX_ETH_CFG2 0x04
38 #define AG7XXX_ETH_CFG2_IF_1000 BIT(9)
39 #define AG7XXX_ETH_CFG2_IF_10_100 BIT(8)
40 #define AG7XXX_ETH_CFG2_IF_SPEED_MASK (3 << 8)
41 #define AG7XXX_ETH_CFG2_HUGE_FRAME_EN BIT(5)
42 #define AG7XXX_ETH_CFG2_LEN_CHECK BIT(4)
43 #define AG7XXX_ETH_CFG2_PAD_CRC_EN BIT(2)
44 #define AG7XXX_ETH_CFG2_FDX BIT(0)
46 #define AG7XXX_ETH_MII_MGMT_CFG 0x20
47 #define AG7XXX_ETH_MII_MGMT_CFG_RESET BIT(31)
49 #define AG7XXX_ETH_MII_MGMT_CMD 0x24
50 #define AG7XXX_ETH_MII_MGMT_CMD_READ 0x1
52 #define AG7XXX_ETH_MII_MGMT_ADDRESS 0x28
53 #define AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT 8
55 #define AG7XXX_ETH_MII_MGMT_CTRL 0x2c
57 #define AG7XXX_ETH_MII_MGMT_STATUS 0x30
59 #define AG7XXX_ETH_MII_MGMT_IND 0x34
60 #define AG7XXX_ETH_MII_MGMT_IND_INVALID BIT(2)
61 #define AG7XXX_ETH_MII_MGMT_IND_BUSY BIT(0)
63 #define AG7XXX_ETH_ADDR1 0x40
64 #define AG7XXX_ETH_ADDR2 0x44
66 #define AG7XXX_ETH_FIFO_CFG_0 0x48
67 #define AG7XXX_ETH_FIFO_CFG_1 0x4c
68 #define AG7XXX_ETH_FIFO_CFG_2 0x50
69 #define AG7XXX_ETH_FIFO_CFG_3 0x54
70 #define AG7XXX_ETH_FIFO_CFG_4 0x58
71 #define AG7XXX_ETH_FIFO_CFG_5 0x5c
73 #define AG7XXX_ETH_DMA_TX_CTRL 0x180
74 #define AG7XXX_ETH_DMA_TX_CTRL_TXE BIT(0)
76 #define AG7XXX_ETH_DMA_TX_DESC 0x184
78 #define AG7XXX_ETH_DMA_TX_STATUS 0x188
80 #define AG7XXX_ETH_DMA_RX_CTRL 0x18c
81 #define AG7XXX_ETH_DMA_RX_CTRL_RXE BIT(0)
83 #define AG7XXX_ETH_DMA_RX_DESC 0x190
85 #define AG7XXX_ETH_DMA_RX_STATUS 0x194
87 /* Custom register at 0x18070000 */
88 #define AG7XXX_GMAC_ETH_CFG 0x00
89 #define AG7XXX_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
90 #define AG7XXX_ETH_CFG_SW_PHY_SWAP BIT(7)
91 #define AG7XXX_ETH_CFG_SW_ONLY_MODE BIT(6)
92 #define AG7XXX_ETH_CFG_GE0_ERR_EN BIT(5)
93 #define AG7XXX_ETH_CFG_MII_GE0_SLAVE BIT(4)
94 #define AG7XXX_ETH_CFG_MII_GE0_MASTER BIT(3)
95 #define AG7XXX_ETH_CFG_GMII_GE0 BIT(2)
96 #define AG7XXX_ETH_CFG_MII_GE0 BIT(1)
97 #define AG7XXX_ETH_CFG_RGMII_GE0 BIT(0)
99 #define CONFIG_TX_DESCR_NUM 8
100 #define CONFIG_RX_DESCR_NUM 8
101 #define CONFIG_ETH_BUFSIZE 2048
102 #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
103 #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
105 /* DMA descriptor. */
106 struct ag7xxx_dma_desc
{
108 #define AG7XXX_DMADESC_IS_EMPTY BIT(31)
109 #define AG7XXX_DMADESC_FTPP_OVERRIDE_OFFSET 16
110 #define AG7XXX_DMADESC_PKT_SIZE_OFFSET 0
111 #define AG7XXX_DMADESC_PKT_SIZE_MASK 0xfff
117 struct ar7xxx_eth_priv
{
118 struct ag7xxx_dma_desc tx_mac_descrtable
[CONFIG_TX_DESCR_NUM
];
119 struct ag7xxx_dma_desc rx_mac_descrtable
[CONFIG_RX_DESCR_NUM
];
120 char txbuffs
[TX_TOTAL_BUFSIZE
] __aligned(ARCH_DMA_MINALIGN
);
121 char rxbuffs
[RX_TOTAL_BUFSIZE
] __aligned(ARCH_DMA_MINALIGN
);
124 void __iomem
*phyregs
;
126 struct eth_device
*dev
;
127 struct phy_device
*phydev
;
133 enum ag7xxx_model model
;
137 * Switch and MDIO access
139 static int ag7xxx_switch_read(struct mii_dev
*bus
, int addr
, int reg
, u16
*val
)
141 struct ar7xxx_eth_priv
*priv
= bus
->priv
;
142 void __iomem
*regs
= priv
->phyregs
;
145 writel(0x0, regs
+ AG7XXX_ETH_MII_MGMT_CMD
);
146 writel((addr
<< AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT
) | reg
,
147 regs
+ AG7XXX_ETH_MII_MGMT_ADDRESS
);
148 writel(AG7XXX_ETH_MII_MGMT_CMD_READ
,
149 regs
+ AG7XXX_ETH_MII_MGMT_CMD
);
151 ret
= wait_for_bit("ag7xxx", regs
+ AG7XXX_ETH_MII_MGMT_IND
,
152 AG7XXX_ETH_MII_MGMT_IND_BUSY
, 0, 1000, 0);
156 *val
= readl(regs
+ AG7XXX_ETH_MII_MGMT_STATUS
) & 0xffff;
157 writel(0x0, regs
+ AG7XXX_ETH_MII_MGMT_CMD
);
162 static int ag7xxx_switch_write(struct mii_dev
*bus
, int addr
, int reg
, u16 val
)
164 struct ar7xxx_eth_priv
*priv
= bus
->priv
;
165 void __iomem
*regs
= priv
->phyregs
;
168 writel((addr
<< AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT
) | reg
,
169 regs
+ AG7XXX_ETH_MII_MGMT_ADDRESS
);
170 writel(val
, regs
+ AG7XXX_ETH_MII_MGMT_CTRL
);
172 ret
= wait_for_bit("ag7xxx", regs
+ AG7XXX_ETH_MII_MGMT_IND
,
173 AG7XXX_ETH_MII_MGMT_IND_BUSY
, 0, 1000, 0);
178 static int ag7xxx_switch_reg_read(struct mii_dev
*bus
, int reg
, u32
*val
)
180 struct ar7xxx_eth_priv
*priv
= bus
->priv
;
188 if (priv
->model
== AG7XXX_MODEL_AG933X
) {
191 } else if (priv
->model
== AG7XXX_MODEL_AG934X
) {
197 ret
= ag7xxx_switch_write(bus
, phy_addr
, reg_addr
, reg
>> 9);
201 phy_temp
= ((reg
>> 6) & 0x7) | 0x10;
202 reg_temp
= (reg
>> 1) & 0x1e;
205 ret
= ag7xxx_switch_read(bus
, phy_temp
, reg_temp
| 0, &rv
);
210 ret
= ag7xxx_switch_read(bus
, phy_temp
, reg_temp
| 1, &rv
);
218 static int ag7xxx_switch_reg_write(struct mii_dev
*bus
, int reg
, u32 val
)
220 struct ar7xxx_eth_priv
*priv
= bus
->priv
;
227 if (priv
->model
== AG7XXX_MODEL_AG933X
) {
230 } else if (priv
->model
== AG7XXX_MODEL_AG934X
) {
236 ret
= ag7xxx_switch_write(bus
, phy_addr
, reg_addr
, reg
>> 9);
240 phy_temp
= ((reg
>> 6) & 0x7) | 0x10;
241 reg_temp
= (reg
>> 1) & 0x1e;
244 * The switch on AR933x has some special register behavior, which
245 * expects particular write order of their nibbles:
246 * 0x40 ..... MSB first, LSB second
247 * 0x50 ..... MSB first, LSB second
248 * 0x98 ..... LSB first, MSB second
249 * others ... don't care
251 if ((priv
->model
== AG7XXX_MODEL_AG933X
) && (reg
== 0x98)) {
252 ret
= ag7xxx_switch_write(bus
, phy_temp
, reg_temp
| 0, val
& 0xffff);
256 ret
= ag7xxx_switch_write(bus
, phy_temp
, reg_temp
| 1, val
>> 16);
260 ret
= ag7xxx_switch_write(bus
, phy_temp
, reg_temp
| 1, val
>> 16);
264 ret
= ag7xxx_switch_write(bus
, phy_temp
, reg_temp
| 0, val
& 0xffff);
272 static u16
ag7xxx_mdio_rw(struct mii_dev
*bus
, int addr
, int reg
, u32 val
)
276 /* Dummy read followed by PHY read/write command. */
277 ag7xxx_switch_reg_read(bus
, 0x98, &data
);
278 data
= val
| (reg
<< 16) | (addr
<< 21) | BIT(30) | BIT(31);
279 ag7xxx_switch_reg_write(bus
, 0x98, data
);
281 /* Wait for operation to finish */
283 ag7xxx_switch_reg_read(bus
, 0x98, &data
);
284 } while (data
& BIT(31));
286 return data
& 0xffff;
289 static int ag7xxx_mdio_read(struct mii_dev
*bus
, int addr
, int devad
, int reg
)
291 return ag7xxx_mdio_rw(bus
, addr
, reg
, BIT(27));
294 static int ag7xxx_mdio_write(struct mii_dev
*bus
, int addr
, int devad
, int reg
,
297 ag7xxx_mdio_rw(bus
, addr
, reg
, val
);
304 static void ag7xxx_dma_clean_tx(struct udevice
*dev
)
306 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
307 struct ag7xxx_dma_desc
*curr
, *next
;
311 for (i
= 0; i
< CONFIG_TX_DESCR_NUM
; i
++) {
312 curr
= &priv
->tx_mac_descrtable
[i
];
313 next
= &priv
->tx_mac_descrtable
[(i
+ 1) % CONFIG_TX_DESCR_NUM
];
315 curr
->data_addr
= virt_to_phys(&priv
->txbuffs
[i
* CONFIG_ETH_BUFSIZE
]);
316 curr
->config
= AG7XXX_DMADESC_IS_EMPTY
;
317 curr
->next_desc
= virt_to_phys(next
);
320 priv
->tx_currdescnum
= 0;
322 /* Cache: Flush descriptors, don't care about buffers. */
323 start
= (u32
)(&priv
->tx_mac_descrtable
[0]);
324 end
= start
+ sizeof(priv
->tx_mac_descrtable
);
325 flush_dcache_range(start
, end
);
328 static void ag7xxx_dma_clean_rx(struct udevice
*dev
)
330 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
331 struct ag7xxx_dma_desc
*curr
, *next
;
335 for (i
= 0; i
< CONFIG_RX_DESCR_NUM
; i
++) {
336 curr
= &priv
->rx_mac_descrtable
[i
];
337 next
= &priv
->rx_mac_descrtable
[(i
+ 1) % CONFIG_RX_DESCR_NUM
];
339 curr
->data_addr
= virt_to_phys(&priv
->rxbuffs
[i
* CONFIG_ETH_BUFSIZE
]);
340 curr
->config
= AG7XXX_DMADESC_IS_EMPTY
;
341 curr
->next_desc
= virt_to_phys(next
);
344 priv
->rx_currdescnum
= 0;
346 /* Cache: Flush+Invalidate descriptors, Invalidate buffers. */
347 start
= (u32
)(&priv
->rx_mac_descrtable
[0]);
348 end
= start
+ sizeof(priv
->rx_mac_descrtable
);
349 flush_dcache_range(start
, end
);
350 invalidate_dcache_range(start
, end
);
352 start
= (u32
)&priv
->rxbuffs
;
353 end
= start
+ sizeof(priv
->rxbuffs
);
354 invalidate_dcache_range(start
, end
);
360 static int ag7xxx_eth_send(struct udevice
*dev
, void *packet
, int length
)
362 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
363 struct ag7xxx_dma_desc
*curr
;
366 curr
= &priv
->tx_mac_descrtable
[priv
->tx_currdescnum
];
368 /* Cache: Invalidate descriptor. */
370 end
= start
+ sizeof(*curr
);
371 invalidate_dcache_range(start
, end
);
373 if (!(curr
->config
& AG7XXX_DMADESC_IS_EMPTY
)) {
374 printf("ag7xxx: Out of TX DMA descriptors!\n");
378 /* Copy the packet into the data buffer. */
379 memcpy(phys_to_virt(curr
->data_addr
), packet
, length
);
380 curr
->config
= length
& AG7XXX_DMADESC_PKT_SIZE_MASK
;
382 /* Cache: Flush descriptor, Flush buffer. */
384 end
= start
+ sizeof(*curr
);
385 flush_dcache_range(start
, end
);
386 start
= (u32
)phys_to_virt(curr
->data_addr
);
387 end
= start
+ length
;
388 flush_dcache_range(start
, end
);
390 /* Load the DMA descriptor and start TX DMA. */
391 writel(AG7XXX_ETH_DMA_TX_CTRL_TXE
,
392 priv
->regs
+ AG7XXX_ETH_DMA_TX_CTRL
);
394 /* Switch to next TX descriptor. */
395 priv
->tx_currdescnum
= (priv
->tx_currdescnum
+ 1) % CONFIG_TX_DESCR_NUM
;
400 static int ag7xxx_eth_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
402 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
403 struct ag7xxx_dma_desc
*curr
;
404 u32 start
, end
, length
;
406 curr
= &priv
->rx_mac_descrtable
[priv
->rx_currdescnum
];
408 /* Cache: Invalidate descriptor. */
410 end
= start
+ sizeof(*curr
);
411 invalidate_dcache_range(start
, end
);
413 /* No packets received. */
414 if (curr
->config
& AG7XXX_DMADESC_IS_EMPTY
)
417 length
= curr
->config
& AG7XXX_DMADESC_PKT_SIZE_MASK
;
419 /* Cache: Invalidate buffer. */
420 start
= (u32
)phys_to_virt(curr
->data_addr
);
421 end
= start
+ length
;
422 invalidate_dcache_range(start
, end
);
424 /* Receive one packet and return length. */
425 *packetp
= phys_to_virt(curr
->data_addr
);
429 static int ag7xxx_eth_free_pkt(struct udevice
*dev
, uchar
*packet
,
432 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
433 struct ag7xxx_dma_desc
*curr
;
436 curr
= &priv
->rx_mac_descrtable
[priv
->rx_currdescnum
];
438 curr
->config
= AG7XXX_DMADESC_IS_EMPTY
;
440 /* Cache: Flush descriptor. */
442 end
= start
+ sizeof(*curr
);
443 flush_dcache_range(start
, end
);
445 /* Switch to next RX descriptor. */
446 priv
->rx_currdescnum
= (priv
->rx_currdescnum
+ 1) % CONFIG_RX_DESCR_NUM
;
451 static int ag7xxx_eth_start(struct udevice
*dev
)
453 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
455 /* FIXME: Check if link up */
457 /* Clear the DMA rings. */
458 ag7xxx_dma_clean_tx(dev
);
459 ag7xxx_dma_clean_rx(dev
);
461 /* Load DMA descriptors and start the RX DMA. */
462 writel(virt_to_phys(&priv
->tx_mac_descrtable
[priv
->tx_currdescnum
]),
463 priv
->regs
+ AG7XXX_ETH_DMA_TX_DESC
);
464 writel(virt_to_phys(&priv
->rx_mac_descrtable
[priv
->rx_currdescnum
]),
465 priv
->regs
+ AG7XXX_ETH_DMA_RX_DESC
);
466 writel(AG7XXX_ETH_DMA_RX_CTRL_RXE
,
467 priv
->regs
+ AG7XXX_ETH_DMA_RX_CTRL
);
472 static void ag7xxx_eth_stop(struct udevice
*dev
)
474 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
476 /* Stop the TX DMA. */
477 writel(0, priv
->regs
+ AG7XXX_ETH_DMA_TX_CTRL
);
478 wait_for_bit("ag7xxx", priv
->regs
+ AG7XXX_ETH_DMA_TX_CTRL
, ~0, 0,
481 /* Stop the RX DMA. */
482 writel(0, priv
->regs
+ AG7XXX_ETH_DMA_RX_CTRL
);
483 wait_for_bit("ag7xxx", priv
->regs
+ AG7XXX_ETH_DMA_RX_CTRL
, ~0, 0,
490 static int ag7xxx_eth_write_hwaddr(struct udevice
*dev
)
492 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
493 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
494 unsigned char *mac
= pdata
->enetaddr
;
495 u32 macid_lo
, macid_hi
;
497 macid_hi
= mac
[3] | (mac
[2] << 8) | (mac
[1] << 16) | (mac
[0] << 24);
498 macid_lo
= (mac
[5] << 16) | (mac
[4] << 24);
500 writel(macid_lo
, priv
->regs
+ AG7XXX_ETH_ADDR1
);
501 writel(macid_hi
, priv
->regs
+ AG7XXX_ETH_ADDR2
);
506 static void ag7xxx_hw_setup(struct udevice
*dev
)
508 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
511 setbits_be32(priv
->regs
+ AG7XXX_ETH_CFG1
,
512 AG7XXX_ETH_CFG1_RX_RST
| AG7XXX_ETH_CFG1_TX_RST
|
513 AG7XXX_ETH_CFG1_SOFT_RST
);
517 writel(AG7XXX_ETH_CFG1_RX_EN
| AG7XXX_ETH_CFG1_TX_EN
,
518 priv
->regs
+ AG7XXX_ETH_CFG1
);
520 if (priv
->interface
== PHY_INTERFACE_MODE_RMII
)
521 speed
= AG7XXX_ETH_CFG2_IF_10_100
;
523 speed
= AG7XXX_ETH_CFG2_IF_1000
;
525 clrsetbits_be32(priv
->regs
+ AG7XXX_ETH_CFG2
,
526 AG7XXX_ETH_CFG2_IF_SPEED_MASK
,
527 speed
| AG7XXX_ETH_CFG2_PAD_CRC_EN
|
528 AG7XXX_ETH_CFG2_LEN_CHECK
);
530 writel(0xfff0000, priv
->regs
+ AG7XXX_ETH_FIFO_CFG_1
);
531 writel(0x1fff, priv
->regs
+ AG7XXX_ETH_FIFO_CFG_2
);
533 writel(0x1f00, priv
->regs
+ AG7XXX_ETH_FIFO_CFG_0
);
534 setbits_be32(priv
->regs
+ AG7XXX_ETH_FIFO_CFG_4
, 0x3ffff);
535 writel(0x10ffff, priv
->regs
+ AG7XXX_ETH_FIFO_CFG_1
);
536 writel(0xaaa0555, priv
->regs
+ AG7XXX_ETH_FIFO_CFG_2
);
537 writel(0x7eccf, priv
->regs
+ AG7XXX_ETH_FIFO_CFG_5
);
538 writel(0x1f00140, priv
->regs
+ AG7XXX_ETH_FIFO_CFG_3
);
541 static int ag7xxx_mii_get_div(void)
543 ulong freq
= get_bus_freq(0);
545 switch (freq
/ 1000000) {
546 case 150: return 0x7;
547 case 175: return 0x5;
548 case 200: return 0x4;
549 case 210: return 0x9;
550 case 220: return 0x9;
555 static int ag7xxx_mii_setup(struct udevice
*dev
)
557 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
558 int i
, ret
, div
= ag7xxx_mii_get_div();
561 if (priv
->model
== AG7XXX_MODEL_AG933X
) {
562 /* Unit 0 is PHY-less on AR9331, see datasheet Figure 2-3 */
563 if (priv
->interface
== PHY_INTERFACE_MODE_RMII
)
567 if (priv
->model
== AG7XXX_MODEL_AG934X
) {
568 writel(AG7XXX_ETH_MII_MGMT_CFG_RESET
| 0x4,
569 priv
->regs
+ AG7XXX_ETH_MII_MGMT_CFG
);
570 writel(0x4, priv
->regs
+ AG7XXX_ETH_MII_MGMT_CFG
);
574 for (i
= 0; i
< 10; i
++) {
575 writel(AG7XXX_ETH_MII_MGMT_CFG_RESET
| div
,
576 priv
->regs
+ AG7XXX_ETH_MII_MGMT_CFG
);
577 writel(div
, priv
->regs
+ AG7XXX_ETH_MII_MGMT_CFG
);
579 /* Check the switch */
580 ret
= ag7xxx_switch_reg_read(priv
->bus
, 0x10c, ®
);
584 if (reg
!= 0x18007fff)
593 static int ag933x_phy_setup_wan(struct udevice
*dev
)
595 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
597 /* Configure switch port 4 (GMAC0) */
598 return ag7xxx_mdio_write(priv
->bus
, 4, 0, MII_BMCR
, 0x9000);
601 static int ag933x_phy_setup_lan(struct udevice
*dev
)
603 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
607 /* Reset the switch */
608 ret
= ag7xxx_switch_reg_read(priv
->bus
, 0, ®
);
612 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0, reg
);
617 ret
= ag7xxx_switch_reg_read(priv
->bus
, 0, ®
);
620 } while (reg
& BIT(31));
622 /* Configure switch ports 0...3 (GMAC1) */
623 for (i
= 0; i
< 4; i
++) {
624 ret
= ag7xxx_mdio_write(priv
->bus
, 0x4, 0, MII_BMCR
, 0x9000);
629 /* Enable CPU port */
630 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0x78, BIT(8));
634 for (i
= 0; i
< 4; i
++) {
635 ret
= ag7xxx_switch_reg_write(priv
->bus
, i
* 0x100, BIT(9));
641 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0x38, 0xc000050e);
645 /* Disable Atheros header */
646 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0x104, 0x4004);
650 /* Tag priority mapping */
651 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0x70, 0xfa50);
655 /* Enable ARP packets to the CPU */
656 ret
= ag7xxx_switch_reg_read(priv
->bus
, 0x5c, ®
);
660 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0x5c, reg
);
667 static int ag933x_phy_setup_reset_set(struct udevice
*dev
, int port
)
669 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
672 ret
= ag7xxx_mdio_write(priv
->bus
, port
, 0, MII_ADVERTISE
,
673 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
|
674 ADVERTISE_PAUSE_ASYM
);
678 if (priv
->model
== AG7XXX_MODEL_AG934X
) {
679 ret
= ag7xxx_mdio_write(priv
->bus
, port
, 0, MII_CTRL1000
,
685 return ag7xxx_mdio_write(priv
->bus
, port
, 0, MII_BMCR
,
686 BMCR_ANENABLE
| BMCR_RESET
);
689 static int ag933x_phy_setup_reset_fin(struct udevice
*dev
, int port
)
691 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
695 ret
= ag7xxx_mdio_read(priv
->bus
, port
, 0, MII_BMCR
);
699 } while (ret
& BMCR_RESET
);
704 static int ag933x_phy_setup_common(struct udevice
*dev
)
706 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
709 if (priv
->model
== AG7XXX_MODEL_AG933X
)
711 else if (priv
->model
== AG7XXX_MODEL_AG934X
)
716 if (priv
->interface
== PHY_INTERFACE_MODE_RMII
) {
717 ret
= ag933x_phy_setup_reset_set(dev
, phymax
);
721 ret
= ag933x_phy_setup_reset_fin(dev
, phymax
);
725 /* Read out link status */
726 ret
= ag7xxx_mdio_read(priv
->bus
, phymax
, 0, MII_MIPSCR
);
734 for (i
= 0; i
< phymax
; i
++) {
735 ret
= ag933x_phy_setup_reset_set(dev
, i
);
740 for (i
= 0; i
< phymax
; i
++) {
741 ret
= ag933x_phy_setup_reset_fin(dev
, i
);
746 for (i
= 0; i
< phymax
; i
++) {
747 /* Read out link status */
748 ret
= ag7xxx_mdio_read(priv
->bus
, i
, 0, MII_MIPSCR
);
756 static int ag934x_phy_setup(struct udevice
*dev
)
758 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
762 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0x624, 0x7f7f7f7f);
765 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0x10, 0x40000000);
768 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0x4, 0x07600000);
771 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0xc, 0x01000000);
774 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0x7c, 0x0000007e);
778 /* AR8327/AR8328 v1.0 fixup */
779 ret
= ag7xxx_switch_reg_read(priv
->bus
, 0, ®
);
782 if ((reg
& 0xffff) == 0x1201) {
783 for (i
= 0; i
< 5; i
++) {
784 ret
= ag7xxx_mdio_write(priv
->bus
, i
, 0, 0x1d, 0x0);
787 ret
= ag7xxx_mdio_write(priv
->bus
, i
, 0, 0x1e, 0x02ea);
790 ret
= ag7xxx_mdio_write(priv
->bus
, i
, 0, 0x1d, 0x3d);
793 ret
= ag7xxx_mdio_write(priv
->bus
, i
, 0, 0x1e, 0x68a0);
799 ret
= ag7xxx_switch_reg_read(priv
->bus
, 0x66c, ®
);
803 ret
= ag7xxx_switch_reg_write(priv
->bus
, 0x66c, reg
);
810 static int ag7xxx_mac_probe(struct udevice
*dev
)
812 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
815 ag7xxx_hw_setup(dev
);
816 ret
= ag7xxx_mii_setup(dev
);
820 ag7xxx_eth_write_hwaddr(dev
);
822 if (priv
->model
== AG7XXX_MODEL_AG933X
) {
823 if (priv
->interface
== PHY_INTERFACE_MODE_RMII
)
824 ret
= ag933x_phy_setup_wan(dev
);
826 ret
= ag933x_phy_setup_lan(dev
);
827 } else if (priv
->model
== AG7XXX_MODEL_AG934X
) {
828 ret
= ag934x_phy_setup(dev
);
836 return ag933x_phy_setup_common(dev
);
839 static int ag7xxx_mdio_probe(struct udevice
*dev
)
841 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
842 struct mii_dev
*bus
= mdio_alloc();
847 bus
->read
= ag7xxx_mdio_read
;
848 bus
->write
= ag7xxx_mdio_write
;
849 snprintf(bus
->name
, sizeof(bus
->name
), dev
->name
);
851 bus
->priv
= (void *)priv
;
853 return mdio_register(bus
);
856 static int ag7xxx_get_phy_iface_offset(struct udevice
*dev
)
860 offset
= fdtdec_lookup_phandle(gd
->fdt_blob
, dev_of_offset(dev
), "phy");
862 debug("%s: PHY OF node not found (ret=%i)\n", __func__
, offset
);
866 offset
= fdt_parent_offset(gd
->fdt_blob
, offset
);
868 debug("%s: PHY OF node parent MDIO bus not found (ret=%i)\n",
873 offset
= fdt_parent_offset(gd
->fdt_blob
, offset
);
875 debug("%s: PHY MDIO OF node parent MAC not found (ret=%i)\n",
883 static int ag7xxx_eth_probe(struct udevice
*dev
)
885 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
886 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
887 void __iomem
*iobase
, *phyiobase
;
890 /* Decoding of convoluted PHY wiring on Atheros MIPS. */
891 ret
= ag7xxx_get_phy_iface_offset(dev
);
894 phyreg
= fdtdec_get_int(gd
->fdt_blob
, ret
, "reg", -1);
896 iobase
= map_physmem(pdata
->iobase
, 0x200, MAP_NOCACHE
);
897 phyiobase
= map_physmem(phyreg
, 0x200, MAP_NOCACHE
);
899 debug("%s, iobase=%p, phyiobase=%p, priv=%p\n",
900 __func__
, iobase
, phyiobase
, priv
);
902 priv
->phyregs
= phyiobase
;
903 priv
->interface
= pdata
->phy_interface
;
904 priv
->model
= dev_get_driver_data(dev
);
906 ret
= ag7xxx_mdio_probe(dev
);
910 priv
->bus
= miiphy_get_dev_by_name(dev
->name
);
912 ret
= ag7xxx_mac_probe(dev
);
913 debug("%s, ret=%d\n", __func__
, ret
);
918 static int ag7xxx_eth_remove(struct udevice
*dev
)
920 struct ar7xxx_eth_priv
*priv
= dev_get_priv(dev
);
923 mdio_unregister(priv
->bus
);
924 mdio_free(priv
->bus
);
929 static const struct eth_ops ag7xxx_eth_ops
= {
930 .start
= ag7xxx_eth_start
,
931 .send
= ag7xxx_eth_send
,
932 .recv
= ag7xxx_eth_recv
,
933 .free_pkt
= ag7xxx_eth_free_pkt
,
934 .stop
= ag7xxx_eth_stop
,
935 .write_hwaddr
= ag7xxx_eth_write_hwaddr
,
938 static int ag7xxx_eth_ofdata_to_platdata(struct udevice
*dev
)
940 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
941 const char *phy_mode
;
944 pdata
->iobase
= dev_get_addr(dev
);
945 pdata
->phy_interface
= -1;
947 /* Decoding of convoluted PHY wiring on Atheros MIPS. */
948 ret
= ag7xxx_get_phy_iface_offset(dev
);
952 phy_mode
= fdt_getprop(gd
->fdt_blob
, ret
, "phy-mode", NULL
);
954 pdata
->phy_interface
= phy_get_interface_by_name(phy_mode
);
955 if (pdata
->phy_interface
== -1) {
956 debug("%s: Invalid PHY interface '%s'\n", __func__
, phy_mode
);
963 static const struct udevice_id ag7xxx_eth_ids
[] = {
964 { .compatible
= "qca,ag933x-mac", .data
= AG7XXX_MODEL_AG933X
},
965 { .compatible
= "qca,ag934x-mac", .data
= AG7XXX_MODEL_AG934X
},
969 U_BOOT_DRIVER(eth_ag7xxx
) = {
970 .name
= "eth_ag7xxx",
972 .of_match
= ag7xxx_eth_ids
,
973 .ofdata_to_platdata
= ag7xxx_eth_ofdata_to_platdata
,
974 .probe
= ag7xxx_eth_probe
,
975 .remove
= ag7xxx_eth_remove
,
976 .ops
= &ag7xxx_eth_ops
,
977 .priv_auto_alloc_size
= sizeof(struct ar7xxx_eth_priv
),
978 .platdata_auto_alloc_size
= sizeof(struct eth_pdata
),
979 .flags
= DM_FLAG_ALLOC_PRIV_DMA
,