drivers/net/altera_tse.c

   1 /*
   2  * Altera 10/100/1000 triple speed ethernet mac driver
   3  *
   4  * Copyright (C) 2008 Altera Corporation.
   5  * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <common.h>
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <fdt_support.h>
  15 #include <memalign.h>
  16 #include <miiphy.h>
  17 #include <net.h>
  18 #include <asm/cache.h>
  19 #include <asm/dma-mapping.h>
  20 #include <asm/io.h>
  21 #include "altera_tse.h"
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 static inline void alt_sgdma_construct_descriptor(
  26         struct alt_sgdma_descriptor *desc,
  27         struct alt_sgdma_descriptor *next,
  28         void *read_addr,
  29         void *write_addr,
  30         u16 length_or_eop,
  31         int generate_eop,
  32         int read_fixed,
  33         int write_fixed_or_sop)
  34 {
  35         u8 val;
  36
  37         /*
  38          * Mark the "next" descriptor as "not" owned by hardware. This prevents
  39          * The SGDMA controller from continuing to process the chain.
  40          */
  41         next->descriptor_control = next->descriptor_control &
  42                 ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
  43
  44         memset(desc, 0, sizeof(struct alt_sgdma_descriptor));
  45         desc->source = virt_to_phys(read_addr);
  46         desc->destination = virt_to_phys(write_addr);
  47         desc->next = virt_to_phys(next);
  48         desc->bytes_to_transfer = length_or_eop;
  49
  50         /*
  51          * Set the descriptor control block as follows:
  52          * - Set "owned by hardware" bit
  53          * - Optionally set "generate EOP" bit
  54          * - Optionally set the "read from fixed address" bit
  55          * - Optionally set the "write to fixed address bit (which serves
  56          *   serves as a "generate SOP" control bit in memory-to-stream mode).
  57          * - Set the 4-bit atlantic channel, if specified
  58          *
  59          * Note this step is performed after all other descriptor information
  60          * has been filled out so that, if the controller already happens to be
  61          * pointing at this descriptor, it will not run (via the "owned by
  62          * hardware" bit) until all other descriptor has been set up.
  63          */
  64         val = ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
  65         if (generate_eop)
  66                 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK;
  67         if (read_fixed)
  68                 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK;
  69         if (write_fixed_or_sop)
  70                 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK;
  71         desc->descriptor_control = val;
  72 }
  73
  74 static int alt_sgdma_wait_transfer(struct alt_sgdma_registers *regs)
  75 {
  76         int status;
  77         ulong ctime;
  78
  79         /* Wait for the descriptor (chain) to complete */
  80         ctime = get_timer(0);
  81         while (1) {
  82                 status = readl(&regs->status);
  83                 if (!(status & ALT_SGDMA_STATUS_BUSY_MSK))
  84                         break;
  85                 if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) {
  86                         status = -ETIMEDOUT;
  87                         debug("sgdma timeout\n");
  88                         break;
  89                 }
  90         }
  91
  92         /* Clear Run */
  93         writel(0, &regs->control);
  94         /* Clear status */
  95         writel(0xff, &regs->status);
  96
  97         return status;
  98 }
  99
 100 static int alt_sgdma_start_transfer(struct alt_sgdma_registers *regs,
 101                                     struct alt_sgdma_descriptor *desc)
 102 {
 103         u32 val;
 104
 105         /* Point the controller at the descriptor */
 106         writel(virt_to_phys(desc), &regs->next_descriptor_pointer);
 107
 108         /*
 109          * Set up SGDMA controller to:
 110          * - Disable interrupt generation
 111          * - Run once a valid descriptor is written to controller
 112          * - Stop on an error with any particular descriptor
 113          */
 114         val = ALT_SGDMA_CONTROL_RUN_MSK | ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK;
 115         writel(val, &regs->control);
 116
 117         return 0;
 118 }
 119
 120 static void tse_adjust_link(struct altera_tse_priv *priv,
 121                             struct phy_device *phydev)
 122 {
 123         struct alt_tse_mac *mac_dev = priv->mac_dev;
 124         u32 refvar;
 125
 126         if (!phydev->link) {
 127                 debug("%s: No link.\n", phydev->dev->name);
 128                 return;
 129         }
 130
 131         refvar = readl(&mac_dev->command_config);
 132
 133         if (phydev->duplex)
 134                 refvar |= ALTERA_TSE_CMD_HD_ENA_MSK;
 135         else
 136                 refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK;
 137
 138         switch (phydev->speed) {
 139         case 1000:
 140                 refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK;
 141                 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
 142                 break;
 143         case 100:
 144                 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
 145                 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
 146                 break;
 147         case 10:
 148                 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
 149                 refvar |= ALTERA_TSE_CMD_ENA_10_MSK;
 150                 break;
 151         }
 152         writel(refvar, &mac_dev->command_config);
 153 }
 154
 155 static int altera_tse_send(struct udevice *dev, void *packet, int length)
 156 {
 157         struct altera_tse_priv *priv = dev_get_priv(dev);
 158         struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
 159         unsigned long tx_buf = (unsigned long)packet;
 160
 161         flush_dcache_range(tx_buf, tx_buf + length);
 162         alt_sgdma_construct_descriptor(
 163                 tx_desc,
 164                 tx_desc + 1,
 165                 packet, /* read addr */
 166                 NULL,   /* write addr */
 167                 length, /* length or EOP ,will change for each tx */
 168                 1,      /* gen eop */
 169                 0,      /* read fixed */
 170                 1       /* write fixed or sop */
 171                 );
 172
 173         /* send the packet */
 174         alt_sgdma_start_transfer(priv->sgdma_tx, tx_desc);
 175         alt_sgdma_wait_transfer(priv->sgdma_tx);
 176         debug("sent %d bytes\n", tx_desc->actual_bytes_transferred);
 177
 178         return tx_desc->actual_bytes_transferred;
 179 }
 180
 181 static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp)
 182 {
 183         struct altera_tse_priv *priv = dev_get_priv(dev);
 184         struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
 185         int packet_length;
 186
 187         if (rx_desc->descriptor_status &
 188             ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) {
 189                 packet_length = rx_desc->actual_bytes_transferred;
 190                 debug("recv %d bytes\n", packet_length);
 191                 *packetp = priv->rx_buf;
 192
 193                 return packet_length;
 194         }
 195
 196         return -EAGAIN;
 197 }
 198
 199 static int altera_tse_free_pkt(struct udevice *dev, uchar *packet,
 200                                int length)
 201 {
 202         struct altera_tse_priv *priv = dev_get_priv(dev);
 203         struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
 204         unsigned long rx_buf = (unsigned long)priv->rx_buf;
 205
 206         alt_sgdma_wait_transfer(priv->sgdma_rx);
 207         invalidate_dcache_range(rx_buf, rx_buf + PKTSIZE_ALIGN);
 208         alt_sgdma_construct_descriptor(
 209                 rx_desc,
 210                 rx_desc + 1,
 211                 NULL,   /* read addr */
 212                 priv->rx_buf, /* write addr */
 213                 0,      /* length or EOP */
 214                 0,      /* gen eop */
 215                 0,      /* read fixed */
 216                 0       /* write fixed or sop */
 217                 );
 218
 219         /* setup the sgdma */
 220         alt_sgdma_start_transfer(priv->sgdma_rx, rx_desc);
 221         debug("recv setup\n");
 222
 223         return 0;
 224 }
 225
 226 static void altera_tse_stop(struct udevice *dev)
 227 {
 228         struct altera_tse_priv *priv = dev_get_priv(dev);
 229         struct alt_tse_mac *mac_dev = priv->mac_dev;
 230         struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx;
 231         struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
 232         struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
 233         u32 status;
 234         int ret;
 235         ulong ctime;
 236
 237         /* clear rx desc & wait for sgdma to complete */
 238         rx_desc->descriptor_control = 0;
 239         writel(0, &rx_sgdma->control);
 240         ret = alt_sgdma_wait_transfer(rx_sgdma);
 241         if (ret == -ETIMEDOUT)
 242                 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
 243                        &rx_sgdma->control);
 244
 245         writel(0, &tx_sgdma->control);
 246         ret = alt_sgdma_wait_transfer(tx_sgdma);
 247         if (ret == -ETIMEDOUT)
 248                 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
 249                        &tx_sgdma->control);
 250
 251         /* reset the mac */
 252         writel(ALTERA_TSE_CMD_SW_RESET_MSK, &mac_dev->command_config);
 253         ctime = get_timer(0);
 254         while (1) {
 255                 status = readl(&mac_dev->command_config);
 256                 if (!(status & ALTERA_TSE_CMD_SW_RESET_MSK))
 257                         break;
 258                 if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
 259                         debug("Reset mac timeout\n");
 260                         break;
 261                 }
 262         }
 263 }
 264
 265 static int tse_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 266 {
 267         struct altera_tse_priv *priv = bus->priv;
 268         struct alt_tse_mac *mac_dev = priv->mac_dev;
 269         u32 value;
 270
 271         /* set mdio address */
 272         writel(addr, &mac_dev->mdio_phy1_addr);
 273         /* get the data */
 274         value = readl(&mac_dev->mdio_phy1[reg]);
 275
 276         return value & 0xffff;
 277 }
 278
 279 static int tse_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
 280                           u16 val)
 281 {
 282         struct altera_tse_priv *priv = bus->priv;
 283         struct alt_tse_mac *mac_dev = priv->mac_dev;
 284
 285         /* set mdio address */
 286         writel(addr, &mac_dev->mdio_phy1_addr);
 287         /* set the data */
 288         writel(val, &mac_dev->mdio_phy1[reg]);
 289
 290         return 0;
 291 }
 292
 293 static int tse_mdio_init(const char *name, struct altera_tse_priv *priv)
 294 {
 295         struct mii_dev *bus = mdio_alloc();
 296
 297         if (!bus) {
 298                 printf("Failed to allocate MDIO bus\n");
 299                 return -ENOMEM;
 300         }
 301
 302         bus->read = tse_mdio_read;
 303         bus->write = tse_mdio_write;
 304         snprintf(bus->name, sizeof(bus->name), name);
 305
 306         bus->priv = (void *)priv;
 307
 308         return mdio_register(bus);
 309 }
 310
 311 static int tse_phy_init(struct altera_tse_priv *priv, void *dev)
 312 {
 313         struct phy_device *phydev;
 314         unsigned int mask = 0xffffffff;
 315
 316         if (priv->phyaddr)
 317                 mask = 1 << priv->phyaddr;
 318
 319         phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
 320         if (!phydev)
 321                 return -ENODEV;
 322
 323         phy_connect_dev(phydev, dev);
 324
 325         phydev->supported &= PHY_GBIT_FEATURES;
 326         phydev->advertising = phydev->supported;
 327
 328         priv->phydev = phydev;
 329         phy_config(phydev);
 330
 331         return 0;
 332 }
 333
 334 static int altera_tse_write_hwaddr(struct udevice *dev)
 335 {
 336         struct altera_tse_priv *priv = dev_get_priv(dev);
 337         struct alt_tse_mac *mac_dev = priv->mac_dev;
 338         struct eth_pdata *pdata = dev_get_platdata(dev);
 339         u8 *hwaddr = pdata->enetaddr;
 340         u32 mac_lo, mac_hi;
 341
 342         mac_lo = (hwaddr[3] << 24) | (hwaddr[2] << 16) |
 343                 (hwaddr[1] << 8) | hwaddr[0];
 344         mac_hi = (hwaddr[5] << 8) | hwaddr[4];
 345         debug("Set MAC address to 0x%04x%08x\n", mac_hi, mac_lo);
 346
 347         writel(mac_lo, &mac_dev->mac_addr_0);
 348         writel(mac_hi, &mac_dev->mac_addr_1);
 349         writel(mac_lo, &mac_dev->supp_mac_addr_0_0);
 350         writel(mac_hi, &mac_dev->supp_mac_addr_0_1);
 351         writel(mac_lo, &mac_dev->supp_mac_addr_1_0);
 352         writel(mac_hi, &mac_dev->supp_mac_addr_1_1);
 353         writel(mac_lo, &mac_dev->supp_mac_addr_2_0);
 354         writel(mac_hi, &mac_dev->supp_mac_addr_2_1);
 355         writel(mac_lo, &mac_dev->supp_mac_addr_3_0);
 356         writel(mac_hi, &mac_dev->supp_mac_addr_3_1);
 357
 358         return 0;
 359 }
 360
 361 static int altera_tse_start(struct udevice *dev)
 362 {
 363         struct altera_tse_priv *priv = dev_get_priv(dev);
 364         struct alt_tse_mac *mac_dev = priv->mac_dev;
 365         u32 val;
 366         int ret;
 367
 368         /* need to create sgdma */
 369         debug("Configuring rx desc\n");
 370         altera_tse_free_pkt(dev, priv->rx_buf, PKTSIZE_ALIGN);
 371         /* start TSE */
 372         debug("Configuring TSE Mac\n");
 373         /* Initialize MAC registers */
 374         writel(PKTSIZE_ALIGN, &mac_dev->max_frame_length);
 375         writel(priv->rx_fifo_depth - 16, &mac_dev->rx_sel_empty_threshold);
 376         writel(0, &mac_dev->rx_sel_full_threshold);
 377         writel(priv->tx_fifo_depth - 16, &mac_dev->tx_sel_empty_threshold);
 378         writel(0, &mac_dev->tx_sel_full_threshold);
 379         writel(8, &mac_dev->rx_almost_empty_threshold);
 380         writel(8, &mac_dev->rx_almost_full_threshold);
 381         writel(8, &mac_dev->tx_almost_empty_threshold);
 382         writel(3, &mac_dev->tx_almost_full_threshold);
 383
 384         /* NO Shift */
 385         writel(0, &mac_dev->rx_cmd_stat);
 386         writel(0, &mac_dev->tx_cmd_stat);
 387
 388         /* enable MAC */
 389         val = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK;
 390         writel(val, &mac_dev->command_config);
 391
 392         /* Start up the PHY */
 393         ret = phy_startup(priv->phydev);
 394         if (ret) {
 395                 debug("Could not initialize PHY %s\n",
 396                       priv->phydev->dev->name);
 397                 return ret;
 398         }
 399
 400         tse_adjust_link(priv, priv->phydev);
 401
 402         if (!priv->phydev->link)
 403                 return -EIO;
 404
 405         return 0;
 406 }
 407
 408 static int altera_tse_probe(struct udevice *dev)
 409 {
 410         struct eth_pdata *pdata = dev_get_platdata(dev);
 411         struct altera_tse_priv *priv = dev_get_priv(dev);
 412         void *blob = (void *)gd->fdt_blob;
 413         int node = dev->of_offset;
 414         const char *list, *end;
 415         const fdt32_t *cell;
 416         void *base, *desc_mem = NULL;
 417         unsigned long addr, size;
 418         int parent, addrc, sizec;
 419         int len, idx;
 420         int ret;
 421
 422         /*
 423          * decode regs. there are multiple reg tuples, and they need to
 424          * match with reg-names.
 425          */
 426         parent = fdt_parent_offset(blob, node);
 427         of_bus_default_count_cells(blob, parent, &addrc, &sizec);
 428         list = fdt_getprop(blob, node, "reg-names", &len);
 429         if (!list)
 430                 return -ENOENT;
 431         end = list + len;
 432         cell = fdt_getprop(blob, node, "reg", &len);
 433         if (!cell)
 434                 return -ENOENT;
 435         idx = 0;
 436         while (list < end) {
 437                 addr = fdt_translate_address((void *)blob,
 438                                              node, cell + idx);
 439                 size = fdt_addr_to_cpu(cell[idx + addrc]);
 440                 base = ioremap(addr, size);
 441                 len = strlen(list);
 442                 if (strcmp(list, "control_port") == 0)
 443                         priv->mac_dev = base;
 444                 else if (strcmp(list, "rx_csr") == 0)
 445                         priv->sgdma_rx = base;
 446                 else if (strcmp(list, "tx_csr") == 0)
 447                         priv->sgdma_tx = base;
 448                 else if (strcmp(list, "s1") == 0)
 449                         desc_mem = base;
 450                 idx += addrc + sizec;
 451                 list += (len + 1);
 452         }
 453         /* decode fifo depth */
 454         priv->rx_fifo_depth = fdtdec_get_int(blob, node,
 455                 "rx-fifo-depth", 0);
 456         priv->tx_fifo_depth = fdtdec_get_int(blob, node,
 457                 "tx-fifo-depth", 0);
 458         /* decode phy */
 459         addr = fdtdec_get_int(blob, node,
 460                               "phy-handle", 0);
 461         addr = fdt_node_offset_by_phandle(blob, addr);
 462         priv->phyaddr = fdtdec_get_int(blob, addr,
 463                 "reg", 0);
 464         /* init desc */
 465         len = sizeof(struct alt_sgdma_descriptor) * 4;
 466         if (!desc_mem) {
 467                 desc_mem = dma_alloc_coherent(len, &addr);
 468                 if (!desc_mem)
 469                         return -ENOMEM;
 470         }
 471         memset(desc_mem, 0, len);
 472         priv->tx_desc = desc_mem;
 473         priv->rx_desc = priv->tx_desc + 2;
 474         /* allocate recv packet buffer */
 475         priv->rx_buf = malloc_cache_aligned(PKTSIZE_ALIGN);
 476         if (!priv->rx_buf)
 477                 return -ENOMEM;
 478
 479         /* stop controller */
 480         debug("Reset TSE & SGDMAs\n");
 481         altera_tse_stop(dev);
 482
 483         /* start the phy */
 484         priv->interface = pdata->phy_interface;
 485         tse_mdio_init(dev->name, priv);
 486         priv->bus = miiphy_get_dev_by_name(dev->name);
 487
 488         ret = tse_phy_init(priv, dev);
 489
 490         return ret;
 491 }
 492
 493 static int altera_tse_ofdata_to_platdata(struct udevice *dev)
 494 {
 495         struct eth_pdata *pdata = dev_get_platdata(dev);
 496         const char *phy_mode;
 497
 498         pdata->phy_interface = -1;
 499         phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
 500         if (phy_mode)
 501                 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
 502         if (pdata->phy_interface == -1) {
 503                 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
 504                 return -EINVAL;
 505         }
 506
 507         return 0;
 508 }
 509
 510 static const struct eth_ops altera_tse_ops = {
 511         .start          = altera_tse_start,
 512         .send           = altera_tse_send,
 513         .recv           = altera_tse_recv,
 514         .free_pkt       = altera_tse_free_pkt,
 515         .stop           = altera_tse_stop,
 516         .write_hwaddr   = altera_tse_write_hwaddr,
 517 };
 518
 519 static const struct udevice_id altera_tse_ids[] = {
 520         { .compatible = "altr,tse-1.0", },
 521         { }
 522 };
 523
 524 U_BOOT_DRIVER(altera_tse) = {
 525         .name   = "altera_tse",
 526         .id     = UCLASS_ETH,
 527         .of_match = altera_tse_ids,
 528         .ops    = &altera_tse_ops,
 529         .ofdata_to_platdata = altera_tse_ofdata_to_platdata,
 530         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 531         .priv_auto_alloc_size = sizeof(struct altera_tse_priv),
 532         .probe  = altera_tse_probe,
 533 };