2 * Altera 10/100/1000 triple speed ethernet mac driver
4 * Copyright (C) 2008 Altera Corporation.
5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
16 #include <asm/cache.h>
17 #include <asm/dma-mapping.h>
19 #include "altera_tse.h"
21 /* sgdma debug - print descriptor */
22 static void alt_sgdma_print_desc(volatile struct alt_sgdma_descriptor
*desc
)
24 debug("SGDMA DEBUG :\n");
25 debug("desc->source : 0x%x \n", (unsigned int)desc
->source
);
26 debug("desc->destination : 0x%x \n", (unsigned int)desc
->destination
);
27 debug("desc->next : 0x%x \n", (unsigned int)desc
->next
);
28 debug("desc->source_pad : 0x%x \n", (unsigned int)desc
->source_pad
);
29 debug("desc->destination_pad : 0x%x \n",
30 (unsigned int)desc
->destination_pad
);
31 debug("desc->next_pad : 0x%x \n", (unsigned int)desc
->next_pad
);
32 debug("desc->bytes_to_transfer : 0x%x \n",
33 (unsigned int)desc
->bytes_to_transfer
);
34 debug("desc->actual_bytes_transferred : 0x%x \n",
35 (unsigned int)desc
->actual_bytes_transferred
);
36 debug("desc->descriptor_status : 0x%x \n",
37 (unsigned int)desc
->descriptor_status
);
38 debug("desc->descriptor_control : 0x%x \n",
39 (unsigned int)desc
->descriptor_control
);
42 /* This is a generic routine that the SGDMA mode-specific routines
43 * call to populate a descriptor.
44 * arg1 :pointer to first SGDMA descriptor.
45 * arg2 :pointer to next SGDMA descriptor.
46 * arg3 :Address to where data to be written.
47 * arg4 :Address from where data to be read.
48 * arg5 :no of byte to transaction.
49 * arg6 :variable indicating to generate start of packet or not
54 * arg11 :atlantic_channel number
56 static void alt_sgdma_construct_descriptor_burst(
57 volatile struct alt_sgdma_descriptor
*desc
,
58 volatile struct alt_sgdma_descriptor
*next
,
59 unsigned int *read_addr
,
60 unsigned int *write_addr
,
61 unsigned short length_or_eop
,
64 int write_fixed_or_sop
,
67 unsigned char atlantic_channel
)
70 * Mark the "next" descriptor as "not" owned by hardware. This prevents
71 * The SGDMA controller from continuing to process the chain. This is
72 * done as a single IO write to bypass cache, without flushing
73 * the entire descriptor, since only the 8-bit descriptor status must
77 debug("Next descriptor not defined!!\n");
79 next
->descriptor_control
= (next
->descriptor_control
&
80 ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK
);
82 desc
->source
= (unsigned int *)((unsigned int)read_addr
& 0x1FFFFFFF);
84 (unsigned int *)((unsigned int)write_addr
& 0x1FFFFFFF);
85 desc
->next
= (unsigned int *)((unsigned int)next
& 0x1FFFFFFF);
86 desc
->source_pad
= 0x0;
87 desc
->destination_pad
= 0x0;
89 desc
->bytes_to_transfer
= length_or_eop
;
90 desc
->actual_bytes_transferred
= 0;
91 desc
->descriptor_status
= 0x0;
93 /* SGDMA burst not currently supported */
95 desc
->write_burst
= 0;
98 * Set the descriptor control block as follows:
99 * - Set "owned by hardware" bit
100 * - Optionally set "generate EOP" bit
101 * - Optionally set the "read from fixed address" bit
102 * - Optionally set the "write to fixed address bit (which serves
103 * serves as a "generate SOP" control bit in memory-to-stream mode).
104 * - Set the 4-bit atlantic channel, if specified
106 * Note this step is performed after all other descriptor information
107 * has been filled out so that, if the controller already happens to be
108 * pointing at this descriptor, it will not run (via the "owned by
109 * hardware" bit) until all other descriptor has been set up.
112 desc
->descriptor_control
=
113 ((ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK
) |
115 ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK
: 0x0) |
117 ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK
: 0x0) |
118 (write_fixed_or_sop
?
119 ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK
: 0x0) |
120 (atlantic_channel
? ((atlantic_channel
& 0x0F) << 3) : 0)
124 static int alt_sgdma_do_sync_transfer(volatile struct alt_sgdma_registers
*dev
,
125 volatile struct alt_sgdma_descriptor
*desc
)
130 /* Wait for any pending transfers to complete */
131 alt_sgdma_print_desc(desc
);
132 status
= dev
->status
;
135 while (dev
->status
& ALT_SGDMA_STATUS_BUSY_MSK
) {
136 if (counter
++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR
)
140 if (counter
>= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR
)
141 debug("Timeout waiting sgdma in do sync!\n");
144 * Clear any (previous) status register information
145 * that might occlude our error checking later.
149 /* Point the controller at the descriptor */
150 dev
->next_descriptor_pointer
= (unsigned int)desc
& 0x1FFFFFFF;
151 debug("next desc in sgdma 0x%x\n",
152 (unsigned int)dev
->next_descriptor_pointer
);
155 * Set up SGDMA controller to:
156 * - Disable interrupt generation
157 * - Run once a valid descriptor is written to controller
158 * - Stop on an error with any particular descriptor
160 dev
->control
= (ALT_SGDMA_CONTROL_RUN_MSK
|
161 ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK
);
163 /* Wait for the descriptor (chain) to complete */
164 status
= dev
->status
;
165 debug("wait for sgdma....");
166 while (dev
->status
& ALT_SGDMA_STATUS_BUSY_MSK
)
171 dev
->control
= (dev
->control
& (~ALT_SGDMA_CONTROL_RUN_MSK
));
173 /* Get & clear status register contents */
174 status
= dev
->status
;
177 /* we really should check if the transfer completes properly */
178 debug("tx sgdma status = 0x%x", status
);
182 static int alt_sgdma_do_async_transfer(volatile struct alt_sgdma_registers
*dev
,
183 volatile struct alt_sgdma_descriptor
*desc
)
188 /* Wait for any pending transfers to complete */
189 alt_sgdma_print_desc(desc
);
190 status
= dev
->status
;
193 while (dev
->status
& ALT_SGDMA_STATUS_BUSY_MSK
) {
194 if (counter
++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR
)
198 if (counter
>= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR
)
199 debug("Timeout waiting sgdma in do async!\n");
202 * Clear any (previous) status register information
203 * that might occlude our error checking later.
207 /* Point the controller at the descriptor */
208 dev
->next_descriptor_pointer
= (unsigned int)desc
& 0x1FFFFFFF;
211 * Set up SGDMA controller to:
212 * - Disable interrupt generation
213 * - Run once a valid descriptor is written to controller
214 * - Stop on an error with any particular descriptor
216 dev
->control
= (ALT_SGDMA_CONTROL_RUN_MSK
|
217 ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK
);
219 /* we really should check if the transfer completes properly */
223 /* u-boot interface */
224 static int tse_adjust_link(struct altera_tse_priv
*priv
)
228 refvar
= priv
->mac_dev
->command_config
.image
;
230 if (!(priv
->duplexity
))
231 refvar
|= ALTERA_TSE_CMD_HD_ENA_MSK
;
233 refvar
&= ~ALTERA_TSE_CMD_HD_ENA_MSK
;
235 switch (priv
->speed
) {
237 refvar
|= ALTERA_TSE_CMD_ETH_SPEED_MSK
;
238 refvar
&= ~ALTERA_TSE_CMD_ENA_10_MSK
;
241 refvar
&= ~ALTERA_TSE_CMD_ETH_SPEED_MSK
;
242 refvar
&= ~ALTERA_TSE_CMD_ENA_10_MSK
;
245 refvar
&= ~ALTERA_TSE_CMD_ETH_SPEED_MSK
;
246 refvar
|= ALTERA_TSE_CMD_ENA_10_MSK
;
249 priv
->mac_dev
->command_config
.image
= refvar
;
254 static int tse_eth_send(struct eth_device
*dev
,
255 volatile void *packet
, int length
)
257 struct altera_tse_priv
*priv
= dev
->priv
;
258 volatile struct alt_sgdma_registers
*tx_sgdma
= priv
->sgdma_tx
;
259 volatile struct alt_sgdma_descriptor
*tx_desc
=
260 (volatile struct alt_sgdma_descriptor
*)priv
->tx_desc
;
262 volatile struct alt_sgdma_descriptor
*tx_desc_cur
=
263 (volatile struct alt_sgdma_descriptor
*)&tx_desc
[0];
265 flush_dcache((unsigned long)packet
, length
);
266 alt_sgdma_construct_descriptor_burst(
267 (volatile struct alt_sgdma_descriptor
*)&tx_desc
[0],
268 (volatile struct alt_sgdma_descriptor
*)&tx_desc
[1],
269 (unsigned int *)packet
, /* read addr */
271 length
, /* length or EOP ,will change for each tx */
273 0x0, /* read fixed */
274 0x1, /* write fixed or sop */
275 0x0, /* read burst */
276 0x0, /* write burst */
279 debug("TX Packet @ 0x%x,0x%x bytes", (unsigned int)packet
, length
);
281 /* send the packet */
282 debug("sending packet\n");
283 alt_sgdma_do_sync_transfer(tx_sgdma
, tx_desc_cur
);
284 debug("sent %d bytes\n", tx_desc_cur
->actual_bytes_transferred
);
285 return tx_desc_cur
->actual_bytes_transferred
;
288 static int tse_eth_rx(struct eth_device
*dev
)
290 int packet_length
= 0;
291 struct altera_tse_priv
*priv
= dev
->priv
;
292 volatile struct alt_sgdma_descriptor
*rx_desc
=
293 (volatile struct alt_sgdma_descriptor
*)priv
->rx_desc
;
294 volatile struct alt_sgdma_descriptor
*rx_desc_cur
= &rx_desc
[0];
296 if (rx_desc_cur
->descriptor_status
&
297 ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK
) {
298 debug("got packet\n");
299 packet_length
= rx_desc
->actual_bytes_transferred
;
300 NetReceive(NetRxPackets
[0], packet_length
);
302 /* start descriptor again */
303 flush_dcache((unsigned long)(NetRxPackets
[0]), PKTSIZE_ALIGN
);
304 alt_sgdma_construct_descriptor_burst(
305 (volatile struct alt_sgdma_descriptor
*)&rx_desc
[0],
306 (volatile struct alt_sgdma_descriptor
*)&rx_desc
[1],
307 (unsigned int)0x0, /* read addr */
308 (unsigned int *)NetRxPackets
[0],
309 0x0, /* length or EOP */
311 0x0, /* read fixed */
312 0x0, /* write fixed or sop */
313 0x0, /* read burst */
314 0x0, /* write burst */
318 /* setup the sgdma */
319 alt_sgdma_do_async_transfer(priv
->sgdma_rx
, &rx_desc
[0]);
325 static void tse_eth_halt(struct eth_device
*dev
)
327 /* don't do anything! */
328 /* this gets called after each uboot */
329 /* network command. don't need to reset the thing all of the time */
332 static void tse_eth_reset(struct eth_device
*dev
)
334 /* stop sgdmas, disable tse receive */
335 struct altera_tse_priv
*priv
= dev
->priv
;
336 volatile struct alt_tse_mac
*mac_dev
= priv
->mac_dev
;
337 volatile struct alt_sgdma_registers
*rx_sgdma
= priv
->sgdma_rx
;
338 volatile struct alt_sgdma_registers
*tx_sgdma
= priv
->sgdma_tx
;
340 volatile struct alt_sgdma_descriptor
*rx_desc
=
341 (volatile struct alt_sgdma_descriptor
*)&priv
->rx_desc
[0];
343 /* clear rx desc & wait for sgdma to complete */
344 rx_desc
->descriptor_control
= 0;
345 rx_sgdma
->control
= 0;
347 while (rx_sgdma
->status
& ALT_SGDMA_STATUS_BUSY_MSK
) {
348 if (counter
++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR
)
352 if (counter
>= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR
) {
353 debug("Timeout waiting for rx sgdma!\n");
354 rx_sgdma
->control
&= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK
;
355 rx_sgdma
->control
&= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK
;
359 tx_sgdma
->control
= 0;
360 while (tx_sgdma
->status
& ALT_SGDMA_STATUS_BUSY_MSK
) {
361 if (counter
++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR
)
365 if (counter
>= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR
) {
366 debug("Timeout waiting for tx sgdma!\n");
367 tx_sgdma
->control
&= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK
;
368 tx_sgdma
->control
&= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK
;
371 mac_dev
->command_config
.bits
.transmit_enable
= 1;
372 mac_dev
->command_config
.bits
.receive_enable
= 1;
373 mac_dev
->command_config
.bits
.software_reset
= 1;
376 while (mac_dev
->command_config
.bits
.software_reset
) {
377 if (counter
++ > ALT_TSE_SW_RESET_WATCHDOG_CNTR
)
381 if (counter
>= ALT_TSE_SW_RESET_WATCHDOG_CNTR
)
382 debug("TSEMAC SW reset bit never cleared!\n");
385 static int tse_mdio_read(struct altera_tse_priv
*priv
, unsigned int regnum
)
387 volatile struct alt_tse_mac
*mac_dev
;
388 unsigned int *mdio_regs
;
392 mac_dev
= priv
->mac_dev
;
394 /* set mdio address */
395 mac_dev
->mdio_phy1_addr
= priv
->phyaddr
;
396 mdio_regs
= (unsigned int *)&mac_dev
->mdio_phy1
;
399 data
= mdio_regs
[regnum
];
401 value
= data
& 0xffff;
406 static int tse_mdio_write(struct altera_tse_priv
*priv
, unsigned int regnum
,
409 volatile struct alt_tse_mac
*mac_dev
;
410 unsigned int *mdio_regs
;
413 mac_dev
= priv
->mac_dev
;
415 /* set mdio address */
416 mac_dev
->mdio_phy1_addr
= priv
->phyaddr
;
417 mdio_regs
= (unsigned int *)&mac_dev
->mdio_phy1
;
420 data
= (unsigned int)value
;
422 mdio_regs
[regnum
] = data
;
427 /* MDIO access to phy */
428 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
429 static int altera_tse_miiphy_write(const char *devname
, unsigned char addr
,
430 unsigned char reg
, unsigned short value
)
432 struct eth_device
*dev
;
433 struct altera_tse_priv
*priv
;
434 dev
= eth_get_dev_by_name(devname
);
437 tse_mdio_write(priv
, (uint
) reg
, (uint
) value
);
442 static int altera_tse_miiphy_read(const char *devname
, unsigned char addr
,
443 unsigned char reg
, unsigned short *value
)
445 struct eth_device
*dev
;
446 struct altera_tse_priv
*priv
;
447 volatile struct alt_tse_mac
*mac_dev
;
448 unsigned int *mdio_regs
;
450 dev
= eth_get_dev_by_name(devname
);
453 mac_dev
= priv
->mac_dev
;
454 mac_dev
->mdio_phy1_addr
= (int)addr
;
455 mdio_regs
= (unsigned int *)&mac_dev
->mdio_phy1
;
457 *value
= 0xffff & mdio_regs
[reg
];
465 * Also copied from tsec.c
467 /* Parse the status register for link, and then do
470 static uint
mii_parse_sr(uint mii_reg
, struct altera_tse_priv
*priv
)
473 * Wait if the link is up, and autonegotiation is in progress
474 * (ie - we're capable and it's not done)
476 mii_reg
= tse_mdio_read(priv
, MIIM_STATUS
);
478 if (!(mii_reg
& MIIM_STATUS_LINK
) && (mii_reg
& BMSR_ANEGCAPABLE
)
479 && !(mii_reg
& BMSR_ANEGCOMPLETE
)) {
482 puts("Waiting for PHY auto negotiation to complete");
483 while (!(mii_reg
& BMSR_ANEGCOMPLETE
)) {
487 if (i
> PHY_AUTONEGOTIATE_TIMEOUT
) {
488 puts(" TIMEOUT !\n");
493 if ((i
++ % 1000) == 0)
495 udelay(1000); /* 1 ms */
496 mii_reg
= tse_mdio_read(priv
, MIIM_STATUS
);
500 udelay(500000); /* another 500 ms (results in faster booting) */
502 if (mii_reg
& MIIM_STATUS_LINK
) {
503 debug("Link is up\n");
506 debug("Link is down\n");
514 /* Parse the 88E1011's status register for speed and duplex
517 static uint
mii_parse_88E1011_psr(uint mii_reg
, struct altera_tse_priv
*priv
)
521 mii_reg
= tse_mdio_read(priv
, MIIM_88E1011_PHY_STATUS
);
523 if ((mii_reg
& MIIM_88E1011_PHYSTAT_LINK
) &&
524 !(mii_reg
& MIIM_88E1011_PHYSTAT_SPDDONE
)) {
527 puts("Waiting for PHY realtime link");
528 while (!(mii_reg
& MIIM_88E1011_PHYSTAT_SPDDONE
)) {
529 /* Timeout reached ? */
530 if (i
> PHY_AUTONEGOTIATE_TIMEOUT
) {
531 puts(" TIMEOUT !\n");
536 if ((i
++ == 1000) == 0) {
540 udelay(1000); /* 1 ms */
541 mii_reg
= tse_mdio_read(priv
, MIIM_88E1011_PHY_STATUS
);
544 udelay(500000); /* another 500 ms (results in faster booting) */
546 if (mii_reg
& MIIM_88E1011_PHYSTAT_LINK
)
552 if (mii_reg
& MIIM_88E1011_PHYSTAT_DUPLEX
)
557 speed
= (mii_reg
& MIIM_88E1011_PHYSTAT_SPEED
);
560 case MIIM_88E1011_PHYSTAT_GBIT
:
562 debug("PHY Speed is 1000Mbit\n");
564 case MIIM_88E1011_PHYSTAT_100
:
565 debug("PHY Speed is 100Mbit\n");
569 debug("PHY Speed is 10Mbit\n");
576 static uint
mii_m88e1111s_setmode_sr(uint mii_reg
, struct altera_tse_priv
*priv
)
578 uint mii_data
= tse_mdio_read(priv
, mii_reg
);
584 static uint
mii_m88e1111s_setmode_cr(uint mii_reg
, struct altera_tse_priv
*priv
)
586 uint mii_data
= tse_mdio_read(priv
, mii_reg
);
593 * Returns which value to write to the control register.
594 * For 10/100, the value is slightly different
596 static uint
mii_cr_init(uint mii_reg
, struct altera_tse_priv
*priv
)
598 return MIIM_CONTROL_INIT
;
603 * Need to add SGMII stuff
607 static struct phy_info phy_info_M88E1111S
= {
611 (struct phy_cmd
[]){ /* config */
612 /* Reset and configure the PHY */
613 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
614 {MIIM_88E1111_PHY_EXT_SR
, 0x848f,
615 &mii_m88e1111s_setmode_sr
},
616 /* Delay RGMII TX and RX */
617 {MIIM_88E1111_PHY_EXT_CR
, 0x0cd2,
618 &mii_m88e1111s_setmode_cr
},
619 {MIIM_GBIT_CONTROL
, MIIM_GBIT_CONTROL_INIT
, NULL
},
620 {MIIM_ANAR
, MIIM_ANAR_INIT
, NULL
},
621 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
622 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
625 (struct phy_cmd
[]){ /* startup */
626 /* Status is read once to clear old link state */
627 {MIIM_STATUS
, miim_read
, NULL
},
629 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
630 /* Read the status */
631 {MIIM_88E1011_PHY_STATUS
, miim_read
,
632 &mii_parse_88E1011_psr
},
635 (struct phy_cmd
[]){ /* shutdown */
640 /* a generic flavor. */
641 static struct phy_info phy_info_generic
= {
643 "Unknown/Generic PHY",
645 (struct phy_cmd
[]){ /* config */
646 {MII_BMCR
, BMCR_RESET
, NULL
},
647 {MII_BMCR
, BMCR_ANENABLE
| BMCR_ANRESTART
, NULL
},
650 (struct phy_cmd
[]){ /* startup */
651 {MII_BMSR
, miim_read
, NULL
},
652 {MII_BMSR
, miim_read
, &mii_parse_sr
},
655 (struct phy_cmd
[]){ /* shutdown */
660 static struct phy_info
*phy_info
[] = {
665 /* Grab the identifier of the device's PHY, and search through
666 * all of the known PHYs to see if one matches. If so, return
667 * it, if not, return NULL
669 static struct phy_info
*get_phy_info(struct eth_device
*dev
)
671 struct altera_tse_priv
*priv
= (struct altera_tse_priv
*)dev
->priv
;
672 uint phy_reg
, phy_ID
;
674 struct phy_info
*theInfo
= NULL
;
676 /* Grab the bits from PHYIR1, and put them in the upper half */
677 phy_reg
= tse_mdio_read(priv
, MIIM_PHYIR1
);
678 phy_ID
= (phy_reg
& 0xffff) << 16;
680 /* Grab the bits from PHYIR2, and put them in the lower half */
681 phy_reg
= tse_mdio_read(priv
, MIIM_PHYIR2
);
682 phy_ID
|= (phy_reg
& 0xffff);
684 /* loop through all the known PHY types, and find one that */
685 /* matches the ID we read from the PHY. */
686 for (i
= 0; phy_info
[i
]; i
++) {
687 if (phy_info
[i
]->id
== (phy_ID
>> phy_info
[i
]->shift
)) {
688 theInfo
= phy_info
[i
];
693 if (theInfo
== NULL
) {
694 theInfo
= &phy_info_generic
;
695 debug("%s: No support for PHY id %x; assuming generic\n",
698 debug("%s: PHY is %s (%x)\n", dev
->name
, theInfo
->name
, phy_ID
);
703 /* Execute the given series of commands on the given device's
704 * PHY, running functions as necessary
706 static void phy_run_commands(struct altera_tse_priv
*priv
, struct phy_cmd
*cmd
)
711 for (i
= 0; cmd
->mii_reg
!= miim_end
; i
++) {
712 if (cmd
->mii_data
== miim_read
) {
713 result
= tse_mdio_read(priv
, cmd
->mii_reg
);
715 if (cmd
->funct
!= NULL
)
716 (*(cmd
->funct
)) (result
, priv
);
719 if (cmd
->funct
!= NULL
)
720 result
= (*(cmd
->funct
)) (cmd
->mii_reg
, priv
);
722 result
= cmd
->mii_data
;
724 tse_mdio_write(priv
, cmd
->mii_reg
, result
);
732 static int init_phy(struct eth_device
*dev
)
734 struct altera_tse_priv
*priv
= (struct altera_tse_priv
*)dev
->priv
;
735 struct phy_info
*curphy
;
737 /* Get the cmd structure corresponding to the attached
739 curphy
= get_phy_info(dev
);
741 if (curphy
== NULL
) {
742 priv
->phyinfo
= NULL
;
743 debug("%s: No PHY found\n", dev
->name
);
747 debug("%s found\n", curphy
->name
);
748 priv
->phyinfo
= curphy
;
750 phy_run_commands(priv
, priv
->phyinfo
->config
);
755 static int tse_set_mac_address(struct eth_device
*dev
)
757 struct altera_tse_priv
*priv
= dev
->priv
;
758 volatile struct alt_tse_mac
*mac_dev
= priv
->mac_dev
;
760 debug("Setting MAC address to 0x%02x%02x%02x%02x%02x%02x\n",
761 dev
->enetaddr
[5], dev
->enetaddr
[4],
762 dev
->enetaddr
[3], dev
->enetaddr
[2],
763 dev
->enetaddr
[1], dev
->enetaddr
[0]);
764 mac_dev
->mac_addr_0
= ((dev
->enetaddr
[3]) << 24 |
765 (dev
->enetaddr
[2]) << 16 |
766 (dev
->enetaddr
[1]) << 8 | (dev
->enetaddr
[0]));
768 mac_dev
->mac_addr_1
= ((dev
->enetaddr
[5] << 8 |
769 (dev
->enetaddr
[4])) & 0xFFFF);
771 /* Set the MAC address */
772 mac_dev
->supp_mac_addr_0_0
= mac_dev
->mac_addr_0
;
773 mac_dev
->supp_mac_addr_0_1
= mac_dev
->mac_addr_1
;
775 /* Set the MAC address */
776 mac_dev
->supp_mac_addr_1_0
= mac_dev
->mac_addr_0
;
777 mac_dev
->supp_mac_addr_1_1
= mac_dev
->mac_addr_1
;
779 /* Set the MAC address */
780 mac_dev
->supp_mac_addr_2_0
= mac_dev
->mac_addr_0
;
781 mac_dev
->supp_mac_addr_2_1
= mac_dev
->mac_addr_1
;
783 /* Set the MAC address */
784 mac_dev
->supp_mac_addr_3_0
= mac_dev
->mac_addr_0
;
785 mac_dev
->supp_mac_addr_3_1
= mac_dev
->mac_addr_1
;
789 static int tse_eth_init(struct eth_device
*dev
, bd_t
* bd
)
792 struct altera_tse_priv
*priv
= dev
->priv
;
793 volatile struct alt_tse_mac
*mac_dev
= priv
->mac_dev
;
794 volatile struct alt_sgdma_descriptor
*tx_desc
= priv
->tx_desc
;
795 volatile struct alt_sgdma_descriptor
*rx_desc
= priv
->rx_desc
;
796 volatile struct alt_sgdma_descriptor
*rx_desc_cur
=
797 (volatile struct alt_sgdma_descriptor
*)&rx_desc
[0];
799 /* stop controller */
800 debug("Reseting TSE & SGDMAs\n");
804 debug("Configuring PHY\n");
805 phy_run_commands(priv
, priv
->phyinfo
->startup
);
807 /* need to create sgdma */
808 debug("Configuring tx desc\n");
809 alt_sgdma_construct_descriptor_burst(
810 (volatile struct alt_sgdma_descriptor
*)&tx_desc
[0],
811 (volatile struct alt_sgdma_descriptor
*)&tx_desc
[1],
812 (unsigned int *)NULL
, /* read addr */
814 0, /* length or EOP ,will change for each tx */
816 0x0, /* read fixed */
817 0x1, /* write fixed or sop */
818 0x0, /* read burst */
819 0x0, /* write burst */
822 debug("Configuring rx desc\n");
823 flush_dcache((unsigned long)(NetRxPackets
[0]), PKTSIZE_ALIGN
);
824 alt_sgdma_construct_descriptor_burst(
825 (volatile struct alt_sgdma_descriptor
*)&rx_desc
[0],
826 (volatile struct alt_sgdma_descriptor
*)&rx_desc
[1],
827 (unsigned int)0x0, /* read addr */
828 (unsigned int *)NetRxPackets
[0],
829 0x0, /* length or EOP */
831 0x0, /* read fixed */
832 0x0, /* write fixed or sop */
833 0x0, /* read burst */
834 0x0, /* write burst */
837 /* start rx async transfer */
838 debug("Starting rx sgdma\n");
839 alt_sgdma_do_async_transfer(priv
->sgdma_rx
, rx_desc_cur
);
842 debug("Configuring TSE Mac\n");
843 /* Initialize MAC registers */
844 mac_dev
->max_frame_length
= PKTSIZE_ALIGN
;
845 mac_dev
->rx_almost_empty_threshold
= 8;
846 mac_dev
->rx_almost_full_threshold
= 8;
847 mac_dev
->tx_almost_empty_threshold
= 8;
848 mac_dev
->tx_almost_full_threshold
= 3;
849 mac_dev
->tx_sel_empty_threshold
=
850 CONFIG_SYS_ALTERA_TSE_TX_FIFO
- 16;
851 mac_dev
->tx_sel_full_threshold
= 0;
852 mac_dev
->rx_sel_empty_threshold
=
853 CONFIG_SYS_ALTERA_TSE_TX_FIFO
- 16;
854 mac_dev
->rx_sel_full_threshold
= 0;
857 mac_dev
->rx_cmd_stat
.bits
.rx_shift16
= 0;
858 mac_dev
->tx_cmd_stat
.bits
.tx_shift16
= 0;
862 dat
= ALTERA_TSE_CMD_TX_ENA_MSK
| ALTERA_TSE_CMD_RX_ENA_MSK
;
864 mac_dev
->command_config
.image
= dat
;
866 /* configure the TSE core */
867 /* -- output clocks, */
868 /* -- and later config stuff for SGMII */
870 debug("Adjusting TSE to link speed\n");
871 tse_adjust_link(priv
);
874 return priv
->link
? 0 : -1;
878 int altera_tse_initialize(u8 dev_num
, int mac_base
,
879 int sgdma_rx_base
, int sgdma_tx_base
)
881 struct altera_tse_priv
*priv
;
882 struct eth_device
*dev
;
883 struct alt_sgdma_descriptor
*rx_desc
;
884 struct alt_sgdma_descriptor
*tx_desc
;
885 unsigned long dma_handle
;
887 dev
= (struct eth_device
*)malloc(sizeof *dev
);
892 memset(dev
, 0, sizeof *dev
);
894 priv
= malloc(sizeof(*priv
));
900 tx_desc
= dma_alloc_coherent(sizeof(*tx_desc
) * (3 + PKTBUFSRX
),
902 rx_desc
= tx_desc
+ 2;
903 debug("tx desc: address = 0x%x\n", (unsigned int)tx_desc
);
904 debug("rx desc: address = 0x%x\n", (unsigned int)rx_desc
);
911 memset(rx_desc
, 0, (sizeof *rx_desc
) * (PKTBUFSRX
+ 1));
912 memset(tx_desc
, 0, (sizeof *tx_desc
) * 2);
914 /* initialize tse priv */
915 priv
->mac_dev
= (volatile struct alt_tse_mac
*)mac_base
;
916 priv
->sgdma_rx
= (volatile struct alt_sgdma_registers
*)sgdma_rx_base
;
917 priv
->sgdma_tx
= (volatile struct alt_sgdma_registers
*)sgdma_tx_base
;
918 priv
->phyaddr
= CONFIG_SYS_ALTERA_TSE_PHY_ADDR
;
919 priv
->flags
= CONFIG_SYS_ALTERA_TSE_FLAGS
;
920 priv
->rx_desc
= rx_desc
;
921 priv
->tx_desc
= tx_desc
;
923 /* init eth structure */
925 dev
->init
= tse_eth_init
;
926 dev
->halt
= tse_eth_halt
;
927 dev
->send
= tse_eth_send
;
928 dev
->recv
= tse_eth_rx
;
929 dev
->write_hwaddr
= tse_set_mac_address
;
930 sprintf(dev
->name
, "%s-%hu", "ALTERA_TSE", dev_num
);
934 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
935 miiphy_register(dev
->name
, altera_tse_miiphy_read
,
936 altera_tse_miiphy_write
);