2 * Altera 10/100/1000 triple speed ethernet mac driver
4 * Copyright (C) 2008 Altera Corporation.
5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
16 #include <asm/cache.h>
17 #include <asm/dma-mapping.h>
19 #include "altera_tse.h"
21 /* sgdma debug - print descriptor */
22 static void alt_sgdma_print_desc(volatile struct alt_sgdma_descriptor
*desc
)
24 debug("SGDMA DEBUG :\n");
25 debug("desc->source : 0x%x \n", (unsigned int)desc
->source
);
26 debug("desc->destination : 0x%x \n", (unsigned int)desc
->destination
);
27 debug("desc->next : 0x%x \n", (unsigned int)desc
->next
);
28 debug("desc->source_pad : 0x%x \n", (unsigned int)desc
->source_pad
);
29 debug("desc->destination_pad : 0x%x \n",
30 (unsigned int)desc
->destination_pad
);
31 debug("desc->next_pad : 0x%x \n", (unsigned int)desc
->next_pad
);
32 debug("desc->bytes_to_transfer : 0x%x \n",
33 (unsigned int)desc
->bytes_to_transfer
);
34 debug("desc->actual_bytes_transferred : 0x%x \n",
35 (unsigned int)desc
->actual_bytes_transferred
);
36 debug("desc->descriptor_status : 0x%x \n",
37 (unsigned int)desc
->descriptor_status
);
38 debug("desc->descriptor_control : 0x%x \n",
39 (unsigned int)desc
->descriptor_control
);
42 /* This is a generic routine that the SGDMA mode-specific routines
43 * call to populate a descriptor.
44 * arg1 :pointer to first SGDMA descriptor.
45 * arg2 :pointer to next SGDMA descriptor.
46 * arg3 :Address to where data to be written.
47 * arg4 :Address from where data to be read.
48 * arg5 :no of byte to transaction.
49 * arg6 :variable indicating to generate start of packet or not
54 * arg11 :atlantic_channel number
56 static void alt_sgdma_construct_descriptor_burst(
57 volatile struct alt_sgdma_descriptor
*desc
,
58 volatile struct alt_sgdma_descriptor
*next
,
59 unsigned int *read_addr
,
60 unsigned int *write_addr
,
61 unsigned short length_or_eop
,
64 int write_fixed_or_sop
,
67 unsigned char atlantic_channel
)
70 * Mark the "next" descriptor as "not" owned by hardware. This prevents
71 * The SGDMA controller from continuing to process the chain. This is
72 * done as a single IO write to bypass cache, without flushing
73 * the entire descriptor, since only the 8-bit descriptor status must
77 debug("Next descriptor not defined!!\n");
79 next
->descriptor_control
= (next
->descriptor_control
&
80 ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK
);
82 desc
->source
= (unsigned int *)((unsigned int)read_addr
& 0x1FFFFFFF);
84 (unsigned int *)((unsigned int)write_addr
& 0x1FFFFFFF);
85 desc
->next
= (unsigned int *)((unsigned int)next
& 0x1FFFFFFF);
86 desc
->source_pad
= 0x0;
87 desc
->destination_pad
= 0x0;
89 desc
->bytes_to_transfer
= length_or_eop
;
90 desc
->actual_bytes_transferred
= 0;
91 desc
->descriptor_status
= 0x0;
93 /* SGDMA burst not currently supported */
95 desc
->write_burst
= 0;
98 * Set the descriptor control block as follows:
99 * - Set "owned by hardware" bit
100 * - Optionally set "generate EOP" bit
101 * - Optionally set the "read from fixed address" bit
102 * - Optionally set the "write to fixed address bit (which serves
103 * serves as a "generate SOP" control bit in memory-to-stream mode).
104 * - Set the 4-bit atlantic channel, if specified
106 * Note this step is performed after all other descriptor information
107 * has been filled out so that, if the controller already happens to be
108 * pointing at this descriptor, it will not run (via the "owned by
109 * hardware" bit) until all other descriptor has been set up.
112 desc
->descriptor_control
=
113 ((ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK
) |
115 ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK
: 0x0) |
117 ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK
: 0x0) |
118 (write_fixed_or_sop
?
119 ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK
: 0x0) |
120 (atlantic_channel
? ((atlantic_channel
& 0x0F) << 3) : 0)
124 static int alt_sgdma_do_sync_transfer(volatile struct alt_sgdma_registers
*dev
,
125 volatile struct alt_sgdma_descriptor
*desc
)
130 /* Wait for any pending transfers to complete */
131 alt_sgdma_print_desc(desc
);
132 status
= dev
->status
;
135 while (dev
->status
& ALT_SGDMA_STATUS_BUSY_MSK
) {
136 if (counter
++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR
)
140 if (counter
>= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR
)
141 debug("Timeout waiting sgdma in do sync!\n");
144 * Clear any (previous) status register information
145 * that might occlude our error checking later.
149 /* Point the controller at the descriptor */
150 dev
->next_descriptor_pointer
= (unsigned int)desc
& 0x1FFFFFFF;
151 debug("next desc in sgdma 0x%x\n",
152 (unsigned int)dev
->next_descriptor_pointer
);
155 * Set up SGDMA controller to:
156 * - Disable interrupt generation
157 * - Run once a valid descriptor is written to controller
158 * - Stop on an error with any particular descriptor
160 dev
->control
= (ALT_SGDMA_CONTROL_RUN_MSK
|
161 ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK
);
163 /* Wait for the descriptor (chain) to complete */
164 status
= dev
->status
;
165 debug("wait for sgdma....");
166 while (dev
->status
& ALT_SGDMA_STATUS_BUSY_MSK
)
171 dev
->control
= (dev
->control
& (~ALT_SGDMA_CONTROL_RUN_MSK
));
173 /* Get & clear status register contents */
174 status
= dev
->status
;
177 /* we really should check if the transfer completes properly */
178 debug("tx sgdma status = 0x%x", status
);
182 static int alt_sgdma_do_async_transfer(volatile struct alt_sgdma_registers
*dev
,
183 volatile struct alt_sgdma_descriptor
*desc
)
188 /* Wait for any pending transfers to complete */
189 alt_sgdma_print_desc(desc
);
190 status
= dev
->status
;
193 while (dev
->status
& ALT_SGDMA_STATUS_BUSY_MSK
) {
194 if (counter
++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR
)
198 if (counter
>= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR
)
199 debug("Timeout waiting sgdma in do async!\n");
202 * Clear the RUN bit in the control register. This is needed
203 * to restart the SGDMA engine later on.
208 * Clear any (previous) status register information
209 * that might occlude our error checking later.
213 /* Point the controller at the descriptor */
214 dev
->next_descriptor_pointer
= (unsigned int)desc
& 0x1FFFFFFF;
217 * Set up SGDMA controller to:
218 * - Disable interrupt generation
219 * - Run once a valid descriptor is written to controller
220 * - Stop on an error with any particular descriptor
222 dev
->control
= (ALT_SGDMA_CONTROL_RUN_MSK
|
223 ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK
);
225 /* we really should check if the transfer completes properly */
229 /* u-boot interface */
230 static int tse_adjust_link(struct altera_tse_priv
*priv
)
234 refvar
= priv
->mac_dev
->command_config
.image
;
236 if (!(priv
->duplexity
))
237 refvar
|= ALTERA_TSE_CMD_HD_ENA_MSK
;
239 refvar
&= ~ALTERA_TSE_CMD_HD_ENA_MSK
;
241 switch (priv
->speed
) {
243 refvar
|= ALTERA_TSE_CMD_ETH_SPEED_MSK
;
244 refvar
&= ~ALTERA_TSE_CMD_ENA_10_MSK
;
247 refvar
&= ~ALTERA_TSE_CMD_ETH_SPEED_MSK
;
248 refvar
&= ~ALTERA_TSE_CMD_ENA_10_MSK
;
251 refvar
&= ~ALTERA_TSE_CMD_ETH_SPEED_MSK
;
252 refvar
|= ALTERA_TSE_CMD_ENA_10_MSK
;
255 priv
->mac_dev
->command_config
.image
= refvar
;
260 static int tse_eth_send(struct eth_device
*dev
,
261 volatile void *packet
, int length
)
263 struct altera_tse_priv
*priv
= dev
->priv
;
264 volatile struct alt_sgdma_registers
*tx_sgdma
= priv
->sgdma_tx
;
265 volatile struct alt_sgdma_descriptor
*tx_desc
=
266 (volatile struct alt_sgdma_descriptor
*)priv
->tx_desc
;
268 volatile struct alt_sgdma_descriptor
*tx_desc_cur
=
269 (volatile struct alt_sgdma_descriptor
*)&tx_desc
[0];
271 flush_dcache((unsigned long)packet
, length
);
272 alt_sgdma_construct_descriptor_burst(
273 (volatile struct alt_sgdma_descriptor
*)&tx_desc
[0],
274 (volatile struct alt_sgdma_descriptor
*)&tx_desc
[1],
275 (unsigned int *)packet
, /* read addr */
277 length
, /* length or EOP ,will change for each tx */
279 0x0, /* read fixed */
280 0x1, /* write fixed or sop */
281 0x0, /* read burst */
282 0x0, /* write burst */
285 debug("TX Packet @ 0x%x,0x%x bytes", (unsigned int)packet
, length
);
287 /* send the packet */
288 debug("sending packet\n");
289 alt_sgdma_do_sync_transfer(tx_sgdma
, tx_desc_cur
);
290 debug("sent %d bytes\n", tx_desc_cur
->actual_bytes_transferred
);
291 return tx_desc_cur
->actual_bytes_transferred
;
294 static int tse_eth_rx(struct eth_device
*dev
)
296 int packet_length
= 0;
297 struct altera_tse_priv
*priv
= dev
->priv
;
298 volatile struct alt_sgdma_descriptor
*rx_desc
=
299 (volatile struct alt_sgdma_descriptor
*)priv
->rx_desc
;
300 volatile struct alt_sgdma_descriptor
*rx_desc_cur
= &rx_desc
[0];
302 if (rx_desc_cur
->descriptor_status
&
303 ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK
) {
304 debug("got packet\n");
305 packet_length
= rx_desc
->actual_bytes_transferred
;
306 NetReceive(NetRxPackets
[0], packet_length
);
308 /* start descriptor again */
309 flush_dcache((unsigned long)(NetRxPackets
[0]), PKTSIZE_ALIGN
);
310 alt_sgdma_construct_descriptor_burst(
311 (volatile struct alt_sgdma_descriptor
*)&rx_desc
[0],
312 (volatile struct alt_sgdma_descriptor
*)&rx_desc
[1],
313 (unsigned int)0x0, /* read addr */
314 (unsigned int *)NetRxPackets
[0],
315 0x0, /* length or EOP */
317 0x0, /* read fixed */
318 0x0, /* write fixed or sop */
319 0x0, /* read burst */
320 0x0, /* write burst */
324 /* setup the sgdma */
325 alt_sgdma_do_async_transfer(priv
->sgdma_rx
, &rx_desc
[0]);
331 static void tse_eth_halt(struct eth_device
*dev
)
333 /* don't do anything! */
334 /* this gets called after each uboot */
335 /* network command. don't need to reset the thing all of the time */
338 static void tse_eth_reset(struct eth_device
*dev
)
340 /* stop sgdmas, disable tse receive */
341 struct altera_tse_priv
*priv
= dev
->priv
;
342 volatile struct alt_tse_mac
*mac_dev
= priv
->mac_dev
;
343 volatile struct alt_sgdma_registers
*rx_sgdma
= priv
->sgdma_rx
;
344 volatile struct alt_sgdma_registers
*tx_sgdma
= priv
->sgdma_tx
;
346 volatile struct alt_sgdma_descriptor
*rx_desc
=
347 (volatile struct alt_sgdma_descriptor
*)&priv
->rx_desc
[0];
349 /* clear rx desc & wait for sgdma to complete */
350 rx_desc
->descriptor_control
= 0;
351 rx_sgdma
->control
= 0;
353 while (rx_sgdma
->status
& ALT_SGDMA_STATUS_BUSY_MSK
) {
354 if (counter
++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR
)
358 if (counter
>= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR
) {
359 debug("Timeout waiting for rx sgdma!\n");
360 rx_sgdma
->control
= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK
;
361 rx_sgdma
->control
= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK
;
365 tx_sgdma
->control
= 0;
366 while (tx_sgdma
->status
& ALT_SGDMA_STATUS_BUSY_MSK
) {
367 if (counter
++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR
)
371 if (counter
>= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR
) {
372 debug("Timeout waiting for tx sgdma!\n");
373 tx_sgdma
->control
= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK
;
374 tx_sgdma
->control
= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK
;
377 mac_dev
->command_config
.bits
.transmit_enable
= 1;
378 mac_dev
->command_config
.bits
.receive_enable
= 1;
379 mac_dev
->command_config
.bits
.software_reset
= 1;
382 while (mac_dev
->command_config
.bits
.software_reset
) {
383 if (counter
++ > ALT_TSE_SW_RESET_WATCHDOG_CNTR
)
387 if (counter
>= ALT_TSE_SW_RESET_WATCHDOG_CNTR
)
388 debug("TSEMAC SW reset bit never cleared!\n");
391 static int tse_mdio_read(struct altera_tse_priv
*priv
, unsigned int regnum
)
393 volatile struct alt_tse_mac
*mac_dev
;
394 unsigned int *mdio_regs
;
398 mac_dev
= priv
->mac_dev
;
400 /* set mdio address */
401 mac_dev
->mdio_phy1_addr
= priv
->phyaddr
;
402 mdio_regs
= (unsigned int *)&mac_dev
->mdio_phy1
;
405 data
= mdio_regs
[regnum
];
407 value
= data
& 0xffff;
412 static int tse_mdio_write(struct altera_tse_priv
*priv
, unsigned int regnum
,
415 volatile struct alt_tse_mac
*mac_dev
;
416 unsigned int *mdio_regs
;
419 mac_dev
= priv
->mac_dev
;
421 /* set mdio address */
422 mac_dev
->mdio_phy1_addr
= priv
->phyaddr
;
423 mdio_regs
= (unsigned int *)&mac_dev
->mdio_phy1
;
426 data
= (unsigned int)value
;
428 mdio_regs
[regnum
] = data
;
433 /* MDIO access to phy */
434 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
435 static int altera_tse_miiphy_write(const char *devname
, unsigned char addr
,
436 unsigned char reg
, unsigned short value
)
438 struct eth_device
*dev
;
439 struct altera_tse_priv
*priv
;
440 dev
= eth_get_dev_by_name(devname
);
443 tse_mdio_write(priv
, (uint
) reg
, (uint
) value
);
448 static int altera_tse_miiphy_read(const char *devname
, unsigned char addr
,
449 unsigned char reg
, unsigned short *value
)
451 struct eth_device
*dev
;
452 struct altera_tse_priv
*priv
;
453 volatile struct alt_tse_mac
*mac_dev
;
454 unsigned int *mdio_regs
;
456 dev
= eth_get_dev_by_name(devname
);
459 mac_dev
= priv
->mac_dev
;
460 mac_dev
->mdio_phy1_addr
= (int)addr
;
461 mdio_regs
= (unsigned int *)&mac_dev
->mdio_phy1
;
463 *value
= 0xffff & mdio_regs
[reg
];
471 * Also copied from tsec.c
473 /* Parse the status register for link, and then do
476 static uint
mii_parse_sr(uint mii_reg
, struct altera_tse_priv
*priv
)
479 * Wait if the link is up, and autonegotiation is in progress
480 * (ie - we're capable and it's not done)
482 mii_reg
= tse_mdio_read(priv
, MIIM_STATUS
);
484 if (!(mii_reg
& MIIM_STATUS_LINK
) && (mii_reg
& BMSR_ANEGCAPABLE
)
485 && !(mii_reg
& BMSR_ANEGCOMPLETE
)) {
488 puts("Waiting for PHY auto negotiation to complete");
489 while (!(mii_reg
& BMSR_ANEGCOMPLETE
)) {
493 if (i
> PHY_AUTONEGOTIATE_TIMEOUT
) {
494 puts(" TIMEOUT !\n");
499 if ((i
++ % 1000) == 0)
501 udelay(1000); /* 1 ms */
502 mii_reg
= tse_mdio_read(priv
, MIIM_STATUS
);
506 udelay(500000); /* another 500 ms (results in faster booting) */
508 if (mii_reg
& MIIM_STATUS_LINK
) {
509 debug("Link is up\n");
512 debug("Link is down\n");
520 /* Parse the 88E1011's status register for speed and duplex
523 static uint
mii_parse_88E1011_psr(uint mii_reg
, struct altera_tse_priv
*priv
)
527 mii_reg
= tse_mdio_read(priv
, MIIM_88E1011_PHY_STATUS
);
529 if ((mii_reg
& MIIM_88E1011_PHYSTAT_LINK
) &&
530 !(mii_reg
& MIIM_88E1011_PHYSTAT_SPDDONE
)) {
533 puts("Waiting for PHY realtime link");
534 while (!(mii_reg
& MIIM_88E1011_PHYSTAT_SPDDONE
)) {
535 /* Timeout reached ? */
536 if (i
> PHY_AUTONEGOTIATE_TIMEOUT
) {
537 puts(" TIMEOUT !\n");
542 if ((i
++ == 1000) == 0) {
546 udelay(1000); /* 1 ms */
547 mii_reg
= tse_mdio_read(priv
, MIIM_88E1011_PHY_STATUS
);
550 udelay(500000); /* another 500 ms (results in faster booting) */
552 if (mii_reg
& MIIM_88E1011_PHYSTAT_LINK
)
558 if (mii_reg
& MIIM_88E1011_PHYSTAT_DUPLEX
)
563 speed
= (mii_reg
& MIIM_88E1011_PHYSTAT_SPEED
);
566 case MIIM_88E1011_PHYSTAT_GBIT
:
568 debug("PHY Speed is 1000Mbit\n");
570 case MIIM_88E1011_PHYSTAT_100
:
571 debug("PHY Speed is 100Mbit\n");
575 debug("PHY Speed is 10Mbit\n");
582 static uint
mii_m88e1111s_setmode_sr(uint mii_reg
, struct altera_tse_priv
*priv
)
584 uint mii_data
= tse_mdio_read(priv
, mii_reg
);
590 static uint
mii_m88e1111s_setmode_cr(uint mii_reg
, struct altera_tse_priv
*priv
)
592 uint mii_data
= tse_mdio_read(priv
, mii_reg
);
599 * Returns which value to write to the control register.
600 * For 10/100, the value is slightly different
602 static uint
mii_cr_init(uint mii_reg
, struct altera_tse_priv
*priv
)
604 return MIIM_CONTROL_INIT
;
609 * Need to add SGMII stuff
613 static struct phy_info phy_info_M88E1111S
= {
617 (struct phy_cmd
[]){ /* config */
618 /* Reset and configure the PHY */
619 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
620 {MIIM_88E1111_PHY_EXT_SR
, 0x848f,
621 &mii_m88e1111s_setmode_sr
},
622 /* Delay RGMII TX and RX */
623 {MIIM_88E1111_PHY_EXT_CR
, 0x0cd2,
624 &mii_m88e1111s_setmode_cr
},
625 {MIIM_GBIT_CONTROL
, MIIM_GBIT_CONTROL_INIT
, NULL
},
626 {MIIM_ANAR
, MIIM_ANAR_INIT
, NULL
},
627 {MIIM_CONTROL
, MIIM_CONTROL_RESET
, NULL
},
628 {MIIM_CONTROL
, MIIM_CONTROL_INIT
, &mii_cr_init
},
631 (struct phy_cmd
[]){ /* startup */
632 /* Status is read once to clear old link state */
633 {MIIM_STATUS
, miim_read
, NULL
},
635 {MIIM_STATUS
, miim_read
, &mii_parse_sr
},
636 /* Read the status */
637 {MIIM_88E1011_PHY_STATUS
, miim_read
,
638 &mii_parse_88E1011_psr
},
641 (struct phy_cmd
[]){ /* shutdown */
646 /* a generic flavor. */
647 static struct phy_info phy_info_generic
= {
649 "Unknown/Generic PHY",
651 (struct phy_cmd
[]){ /* config */
652 {MII_BMCR
, BMCR_RESET
, NULL
},
653 {MII_BMCR
, BMCR_ANENABLE
| BMCR_ANRESTART
, NULL
},
656 (struct phy_cmd
[]){ /* startup */
657 {MII_BMSR
, miim_read
, NULL
},
658 {MII_BMSR
, miim_read
, &mii_parse_sr
},
661 (struct phy_cmd
[]){ /* shutdown */
666 static struct phy_info
*phy_info
[] = {
671 /* Grab the identifier of the device's PHY, and search through
672 * all of the known PHYs to see if one matches. If so, return
673 * it, if not, return NULL
675 static struct phy_info
*get_phy_info(struct eth_device
*dev
)
677 struct altera_tse_priv
*priv
= (struct altera_tse_priv
*)dev
->priv
;
678 uint phy_reg
, phy_ID
;
680 struct phy_info
*theInfo
= NULL
;
682 /* Grab the bits from PHYIR1, and put them in the upper half */
683 phy_reg
= tse_mdio_read(priv
, MIIM_PHYIR1
);
684 phy_ID
= (phy_reg
& 0xffff) << 16;
686 /* Grab the bits from PHYIR2, and put them in the lower half */
687 phy_reg
= tse_mdio_read(priv
, MIIM_PHYIR2
);
688 phy_ID
|= (phy_reg
& 0xffff);
690 /* loop through all the known PHY types, and find one that */
691 /* matches the ID we read from the PHY. */
692 for (i
= 0; phy_info
[i
]; i
++) {
693 if (phy_info
[i
]->id
== (phy_ID
>> phy_info
[i
]->shift
)) {
694 theInfo
= phy_info
[i
];
699 if (theInfo
== NULL
) {
700 theInfo
= &phy_info_generic
;
701 debug("%s: No support for PHY id %x; assuming generic\n",
704 debug("%s: PHY is %s (%x)\n", dev
->name
, theInfo
->name
, phy_ID
);
709 /* Execute the given series of commands on the given device's
710 * PHY, running functions as necessary
712 static void phy_run_commands(struct altera_tse_priv
*priv
, struct phy_cmd
*cmd
)
717 for (i
= 0; cmd
->mii_reg
!= miim_end
; i
++) {
718 if (cmd
->mii_data
== miim_read
) {
719 result
= tse_mdio_read(priv
, cmd
->mii_reg
);
721 if (cmd
->funct
!= NULL
)
722 (*(cmd
->funct
)) (result
, priv
);
725 if (cmd
->funct
!= NULL
)
726 result
= (*(cmd
->funct
)) (cmd
->mii_reg
, priv
);
728 result
= cmd
->mii_data
;
730 tse_mdio_write(priv
, cmd
->mii_reg
, result
);
738 static int init_phy(struct eth_device
*dev
)
740 struct altera_tse_priv
*priv
= (struct altera_tse_priv
*)dev
->priv
;
741 struct phy_info
*curphy
;
743 /* Get the cmd structure corresponding to the attached
745 curphy
= get_phy_info(dev
);
747 if (curphy
== NULL
) {
748 priv
->phyinfo
= NULL
;
749 debug("%s: No PHY found\n", dev
->name
);
753 debug("%s found\n", curphy
->name
);
754 priv
->phyinfo
= curphy
;
756 phy_run_commands(priv
, priv
->phyinfo
->config
);
761 static int tse_set_mac_address(struct eth_device
*dev
)
763 struct altera_tse_priv
*priv
= dev
->priv
;
764 volatile struct alt_tse_mac
*mac_dev
= priv
->mac_dev
;
766 debug("Setting MAC address to 0x%02x%02x%02x%02x%02x%02x\n",
767 dev
->enetaddr
[5], dev
->enetaddr
[4],
768 dev
->enetaddr
[3], dev
->enetaddr
[2],
769 dev
->enetaddr
[1], dev
->enetaddr
[0]);
770 mac_dev
->mac_addr_0
= ((dev
->enetaddr
[3]) << 24 |
771 (dev
->enetaddr
[2]) << 16 |
772 (dev
->enetaddr
[1]) << 8 | (dev
->enetaddr
[0]));
774 mac_dev
->mac_addr_1
= ((dev
->enetaddr
[5] << 8 |
775 (dev
->enetaddr
[4])) & 0xFFFF);
777 /* Set the MAC address */
778 mac_dev
->supp_mac_addr_0_0
= mac_dev
->mac_addr_0
;
779 mac_dev
->supp_mac_addr_0_1
= mac_dev
->mac_addr_1
;
781 /* Set the MAC address */
782 mac_dev
->supp_mac_addr_1_0
= mac_dev
->mac_addr_0
;
783 mac_dev
->supp_mac_addr_1_1
= mac_dev
->mac_addr_1
;
785 /* Set the MAC address */
786 mac_dev
->supp_mac_addr_2_0
= mac_dev
->mac_addr_0
;
787 mac_dev
->supp_mac_addr_2_1
= mac_dev
->mac_addr_1
;
789 /* Set the MAC address */
790 mac_dev
->supp_mac_addr_3_0
= mac_dev
->mac_addr_0
;
791 mac_dev
->supp_mac_addr_3_1
= mac_dev
->mac_addr_1
;
795 static int tse_eth_init(struct eth_device
*dev
, bd_t
* bd
)
798 struct altera_tse_priv
*priv
= dev
->priv
;
799 volatile struct alt_tse_mac
*mac_dev
= priv
->mac_dev
;
800 volatile struct alt_sgdma_descriptor
*tx_desc
= priv
->tx_desc
;
801 volatile struct alt_sgdma_descriptor
*rx_desc
= priv
->rx_desc
;
802 volatile struct alt_sgdma_descriptor
*rx_desc_cur
=
803 (volatile struct alt_sgdma_descriptor
*)&rx_desc
[0];
805 /* stop controller */
806 debug("Reseting TSE & SGDMAs\n");
810 debug("Configuring PHY\n");
811 phy_run_commands(priv
, priv
->phyinfo
->startup
);
813 /* need to create sgdma */
814 debug("Configuring tx desc\n");
815 alt_sgdma_construct_descriptor_burst(
816 (volatile struct alt_sgdma_descriptor
*)&tx_desc
[0],
817 (volatile struct alt_sgdma_descriptor
*)&tx_desc
[1],
818 (unsigned int *)NULL
, /* read addr */
820 0, /* length or EOP ,will change for each tx */
822 0x0, /* read fixed */
823 0x1, /* write fixed or sop */
824 0x0, /* read burst */
825 0x0, /* write burst */
828 debug("Configuring rx desc\n");
829 flush_dcache((unsigned long)(NetRxPackets
[0]), PKTSIZE_ALIGN
);
830 alt_sgdma_construct_descriptor_burst(
831 (volatile struct alt_sgdma_descriptor
*)&rx_desc
[0],
832 (volatile struct alt_sgdma_descriptor
*)&rx_desc
[1],
833 (unsigned int)0x0, /* read addr */
834 (unsigned int *)NetRxPackets
[0],
835 0x0, /* length or EOP */
837 0x0, /* read fixed */
838 0x0, /* write fixed or sop */
839 0x0, /* read burst */
840 0x0, /* write burst */
843 /* start rx async transfer */
844 debug("Starting rx sgdma\n");
845 alt_sgdma_do_async_transfer(priv
->sgdma_rx
, rx_desc_cur
);
848 debug("Configuring TSE Mac\n");
849 /* Initialize MAC registers */
850 mac_dev
->max_frame_length
= PKTSIZE_ALIGN
;
851 mac_dev
->rx_almost_empty_threshold
= 8;
852 mac_dev
->rx_almost_full_threshold
= 8;
853 mac_dev
->tx_almost_empty_threshold
= 8;
854 mac_dev
->tx_almost_full_threshold
= 3;
855 mac_dev
->tx_sel_empty_threshold
=
856 CONFIG_SYS_ALTERA_TSE_TX_FIFO
- 16;
857 mac_dev
->tx_sel_full_threshold
= 0;
858 mac_dev
->rx_sel_empty_threshold
=
859 CONFIG_SYS_ALTERA_TSE_TX_FIFO
- 16;
860 mac_dev
->rx_sel_full_threshold
= 0;
863 mac_dev
->rx_cmd_stat
.bits
.rx_shift16
= 0;
864 mac_dev
->tx_cmd_stat
.bits
.tx_shift16
= 0;
868 dat
= ALTERA_TSE_CMD_TX_ENA_MSK
| ALTERA_TSE_CMD_RX_ENA_MSK
;
870 mac_dev
->command_config
.image
= dat
;
872 /* configure the TSE core */
873 /* -- output clocks, */
874 /* -- and later config stuff for SGMII */
876 debug("Adjusting TSE to link speed\n");
877 tse_adjust_link(priv
);
880 return priv
->link
? 0 : -1;
884 int altera_tse_initialize(u8 dev_num
, int mac_base
,
885 int sgdma_rx_base
, int sgdma_tx_base
,
886 u32 sgdma_desc_base
, u32 sgdma_desc_size
)
888 struct altera_tse_priv
*priv
;
889 struct eth_device
*dev
;
890 struct alt_sgdma_descriptor
*rx_desc
;
891 struct alt_sgdma_descriptor
*tx_desc
;
892 unsigned long dma_handle
;
894 dev
= (struct eth_device
*)malloc(sizeof *dev
);
899 memset(dev
, 0, sizeof *dev
);
901 priv
= malloc(sizeof(*priv
));
907 if (sgdma_desc_size
) {
908 if (sgdma_desc_size
< (sizeof(*tx_desc
) * (3 + PKTBUFSRX
))) {
909 printf("ALTERA_TSE-%hu: "
910 "descriptor memory is too small\n", dev_num
);
915 tx_desc
= (struct alt_sgdma_descriptor
*)sgdma_desc_base
;
917 tx_desc
= dma_alloc_coherent(sizeof(*tx_desc
) * (3 + PKTBUFSRX
),
921 rx_desc
= tx_desc
+ 2;
922 debug("tx desc: address = 0x%x\n", (unsigned int)tx_desc
);
923 debug("rx desc: address = 0x%x\n", (unsigned int)rx_desc
);
930 memset(rx_desc
, 0, (sizeof *rx_desc
) * (PKTBUFSRX
+ 1));
931 memset(tx_desc
, 0, (sizeof *tx_desc
) * 2);
933 /* initialize tse priv */
934 priv
->mac_dev
= (volatile struct alt_tse_mac
*)mac_base
;
935 priv
->sgdma_rx
= (volatile struct alt_sgdma_registers
*)sgdma_rx_base
;
936 priv
->sgdma_tx
= (volatile struct alt_sgdma_registers
*)sgdma_tx_base
;
937 priv
->phyaddr
= CONFIG_SYS_ALTERA_TSE_PHY_ADDR
;
938 priv
->flags
= CONFIG_SYS_ALTERA_TSE_FLAGS
;
939 priv
->rx_desc
= rx_desc
;
940 priv
->tx_desc
= tx_desc
;
942 /* init eth structure */
944 dev
->init
= tse_eth_init
;
945 dev
->halt
= tse_eth_halt
;
946 dev
->send
= tse_eth_send
;
947 dev
->recv
= tse_eth_rx
;
948 dev
->write_hwaddr
= tse_set_mac_address
;
949 sprintf(dev
->name
, "%s-%hu", "ALTERA_TSE", dev_num
);
953 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
954 miiphy_register(dev
->name
, altera_tse_miiphy_read
,
955 altera_tse_miiphy_write
);