3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5 * SPDX-License-Identifier: GPL-2.0+
9 * Designware ethernet IP driver for U-Boot
18 #include <linux/compiler.h>
19 #include <linux/err.h>
21 #include "designware.h"
23 DECLARE_GLOBAL_DATA_PTR
;
25 static int dw_mdio_read(struct mii_dev
*bus
, int addr
, int devad
, int reg
)
28 struct dw_eth_dev
*priv
= dev_get_priv((struct udevice
*)bus
->priv
);
29 struct eth_mac_regs
*mac_p
= priv
->mac_regs_p
;
31 struct eth_mac_regs
*mac_p
= bus
->priv
;
35 int timeout
= CONFIG_MDIO_TIMEOUT
;
37 miiaddr
= ((addr
<< MIIADDRSHIFT
) & MII_ADDRMSK
) |
38 ((reg
<< MIIREGSHIFT
) & MII_REGMSK
);
40 writel(miiaddr
| MII_CLKRANGE_150_250M
| MII_BUSY
, &mac_p
->miiaddr
);
43 while (get_timer(start
) < timeout
) {
44 if (!(readl(&mac_p
->miiaddr
) & MII_BUSY
))
45 return readl(&mac_p
->miidata
);
52 static int dw_mdio_write(struct mii_dev
*bus
, int addr
, int devad
, int reg
,
56 struct dw_eth_dev
*priv
= dev_get_priv((struct udevice
*)bus
->priv
);
57 struct eth_mac_regs
*mac_p
= priv
->mac_regs_p
;
59 struct eth_mac_regs
*mac_p
= bus
->priv
;
63 int ret
= -ETIMEDOUT
, timeout
= CONFIG_MDIO_TIMEOUT
;
65 writel(val
, &mac_p
->miidata
);
66 miiaddr
= ((addr
<< MIIADDRSHIFT
) & MII_ADDRMSK
) |
67 ((reg
<< MIIREGSHIFT
) & MII_REGMSK
) | MII_WRITE
;
69 writel(miiaddr
| MII_CLKRANGE_150_250M
| MII_BUSY
, &mac_p
->miiaddr
);
72 while (get_timer(start
) < timeout
) {
73 if (!(readl(&mac_p
->miiaddr
) & MII_BUSY
)) {
83 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
84 static int dw_mdio_reset(struct mii_dev
*bus
)
86 struct udevice
*dev
= bus
->priv
;
87 struct dw_eth_dev
*priv
= dev_get_priv(dev
);
88 struct dw_eth_pdata
*pdata
= dev_get_platdata(dev
);
91 if (!dm_gpio_is_valid(&priv
->reset_gpio
))
95 ret
= dm_gpio_set_value(&priv
->reset_gpio
, 0);
99 udelay(pdata
->reset_delays
[0]);
101 ret
= dm_gpio_set_value(&priv
->reset_gpio
, 1);
105 udelay(pdata
->reset_delays
[1]);
107 ret
= dm_gpio_set_value(&priv
->reset_gpio
, 0);
111 udelay(pdata
->reset_delays
[2]);
117 static int dw_mdio_init(const char *name
, void *priv
)
119 struct mii_dev
*bus
= mdio_alloc();
122 printf("Failed to allocate MDIO bus\n");
126 bus
->read
= dw_mdio_read
;
127 bus
->write
= dw_mdio_write
;
128 snprintf(bus
->name
, sizeof(bus
->name
), "%s", name
);
129 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
130 bus
->reset
= dw_mdio_reset
;
135 return mdio_register(bus
);
138 static void tx_descs_init(struct dw_eth_dev
*priv
)
140 struct eth_dma_regs
*dma_p
= priv
->dma_regs_p
;
141 struct dmamacdescr
*desc_table_p
= &priv
->tx_mac_descrtable
[0];
142 char *txbuffs
= &priv
->txbuffs
[0];
143 struct dmamacdescr
*desc_p
;
146 for (idx
= 0; idx
< CONFIG_TX_DESCR_NUM
; idx
++) {
147 desc_p
= &desc_table_p
[idx
];
148 desc_p
->dmamac_addr
= (ulong
)&txbuffs
[idx
* CONFIG_ETH_BUFSIZE
];
149 desc_p
->dmamac_next
= (ulong
)&desc_table_p
[idx
+ 1];
151 #if defined(CONFIG_DW_ALTDESCRIPTOR)
152 desc_p
->txrx_status
&= ~(DESC_TXSTS_TXINT
| DESC_TXSTS_TXLAST
|
153 DESC_TXSTS_TXFIRST
| DESC_TXSTS_TXCRCDIS
|
154 DESC_TXSTS_TXCHECKINSCTRL
|
155 DESC_TXSTS_TXRINGEND
| DESC_TXSTS_TXPADDIS
);
157 desc_p
->txrx_status
|= DESC_TXSTS_TXCHAIN
;
158 desc_p
->dmamac_cntl
= 0;
159 desc_p
->txrx_status
&= ~(DESC_TXSTS_MSK
| DESC_TXSTS_OWNBYDMA
);
161 desc_p
->dmamac_cntl
= DESC_TXCTRL_TXCHAIN
;
162 desc_p
->txrx_status
= 0;
166 /* Correcting the last pointer of the chain */
167 desc_p
->dmamac_next
= (ulong
)&desc_table_p
[0];
169 /* Flush all Tx buffer descriptors at once */
170 flush_dcache_range((ulong
)priv
->tx_mac_descrtable
,
171 (ulong
)priv
->tx_mac_descrtable
+
172 sizeof(priv
->tx_mac_descrtable
));
174 writel((ulong
)&desc_table_p
[0], &dma_p
->txdesclistaddr
);
175 priv
->tx_currdescnum
= 0;
178 static void rx_descs_init(struct dw_eth_dev
*priv
)
180 struct eth_dma_regs
*dma_p
= priv
->dma_regs_p
;
181 struct dmamacdescr
*desc_table_p
= &priv
->rx_mac_descrtable
[0];
182 char *rxbuffs
= &priv
->rxbuffs
[0];
183 struct dmamacdescr
*desc_p
;
186 /* Before passing buffers to GMAC we need to make sure zeros
187 * written there right after "priv" structure allocation were
189 * Otherwise there's a chance to get some of them flushed in RAM when
190 * GMAC is already pushing data to RAM via DMA. This way incoming from
191 * GMAC data will be corrupted. */
192 flush_dcache_range((ulong
)rxbuffs
, (ulong
)rxbuffs
+ RX_TOTAL_BUFSIZE
);
194 for (idx
= 0; idx
< CONFIG_RX_DESCR_NUM
; idx
++) {
195 desc_p
= &desc_table_p
[idx
];
196 desc_p
->dmamac_addr
= (ulong
)&rxbuffs
[idx
* CONFIG_ETH_BUFSIZE
];
197 desc_p
->dmamac_next
= (ulong
)&desc_table_p
[idx
+ 1];
199 desc_p
->dmamac_cntl
=
200 (MAC_MAX_FRAME_SZ
& DESC_RXCTRL_SIZE1MASK
) |
203 desc_p
->txrx_status
= DESC_RXSTS_OWNBYDMA
;
206 /* Correcting the last pointer of the chain */
207 desc_p
->dmamac_next
= (ulong
)&desc_table_p
[0];
209 /* Flush all Rx buffer descriptors at once */
210 flush_dcache_range((ulong
)priv
->rx_mac_descrtable
,
211 (ulong
)priv
->rx_mac_descrtable
+
212 sizeof(priv
->rx_mac_descrtable
));
214 writel((ulong
)&desc_table_p
[0], &dma_p
->rxdesclistaddr
);
215 priv
->rx_currdescnum
= 0;
218 static int _dw_write_hwaddr(struct dw_eth_dev
*priv
, u8
*mac_id
)
220 struct eth_mac_regs
*mac_p
= priv
->mac_regs_p
;
221 u32 macid_lo
, macid_hi
;
223 macid_lo
= mac_id
[0] + (mac_id
[1] << 8) + (mac_id
[2] << 16) +
225 macid_hi
= mac_id
[4] + (mac_id
[5] << 8);
227 writel(macid_hi
, &mac_p
->macaddr0hi
);
228 writel(macid_lo
, &mac_p
->macaddr0lo
);
233 static void dw_adjust_link(struct eth_mac_regs
*mac_p
,
234 struct phy_device
*phydev
)
236 u32 conf
= readl(&mac_p
->conf
) | FRAMEBURSTENABLE
| DISABLERXOWN
;
239 printf("%s: No link.\n", phydev
->dev
->name
);
243 if (phydev
->speed
!= 1000)
244 conf
|= MII_PORTSELECT
;
246 conf
&= ~MII_PORTSELECT
;
248 if (phydev
->speed
== 100)
252 conf
|= FULLDPLXMODE
;
254 writel(conf
, &mac_p
->conf
);
256 printf("Speed: %d, %s duplex%s\n", phydev
->speed
,
257 (phydev
->duplex
) ? "full" : "half",
258 (phydev
->port
== PORT_FIBRE
) ? ", fiber mode" : "");
261 static void _dw_eth_halt(struct dw_eth_dev
*priv
)
263 struct eth_mac_regs
*mac_p
= priv
->mac_regs_p
;
264 struct eth_dma_regs
*dma_p
= priv
->dma_regs_p
;
266 writel(readl(&mac_p
->conf
) & ~(RXENABLE
| TXENABLE
), &mac_p
->conf
);
267 writel(readl(&dma_p
->opmode
) & ~(RXSTART
| TXSTART
), &dma_p
->opmode
);
269 phy_shutdown(priv
->phydev
);
272 static int _dw_eth_init(struct dw_eth_dev
*priv
, u8
*enetaddr
)
274 struct eth_mac_regs
*mac_p
= priv
->mac_regs_p
;
275 struct eth_dma_regs
*dma_p
= priv
->dma_regs_p
;
279 writel(readl(&dma_p
->busmode
) | DMAMAC_SRST
, &dma_p
->busmode
);
281 start
= get_timer(0);
282 while (readl(&dma_p
->busmode
) & DMAMAC_SRST
) {
283 if (get_timer(start
) >= CONFIG_MACRESET_TIMEOUT
) {
284 printf("DMA reset timeout\n");
292 * Soft reset above clears HW address registers.
293 * So we have to set it here once again.
295 _dw_write_hwaddr(priv
, enetaddr
);
300 writel(FIXEDBURST
| PRIORXTX_41
| DMA_PBL
, &dma_p
->busmode
);
302 #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
303 writel(readl(&dma_p
->opmode
) | FLUSHTXFIFO
| STOREFORWARD
,
306 writel(readl(&dma_p
->opmode
) | FLUSHTXFIFO
,
310 writel(readl(&dma_p
->opmode
) | RXSTART
| TXSTART
, &dma_p
->opmode
);
312 #ifdef CONFIG_DW_AXI_BURST_LEN
313 writel((CONFIG_DW_AXI_BURST_LEN
& 0x1FF >> 1), &dma_p
->axibus
);
316 /* Start up the PHY */
317 ret
= phy_startup(priv
->phydev
);
319 printf("Could not initialize PHY %s\n",
320 priv
->phydev
->dev
->name
);
324 dw_adjust_link(mac_p
, priv
->phydev
);
326 if (!priv
->phydev
->link
)
329 writel(readl(&mac_p
->conf
) | RXENABLE
| TXENABLE
, &mac_p
->conf
);
334 static int _dw_eth_send(struct dw_eth_dev
*priv
, void *packet
, int length
)
336 struct eth_dma_regs
*dma_p
= priv
->dma_regs_p
;
337 u32 desc_num
= priv
->tx_currdescnum
;
338 struct dmamacdescr
*desc_p
= &priv
->tx_mac_descrtable
[desc_num
];
339 ulong desc_start
= (ulong
)desc_p
;
340 ulong desc_end
= desc_start
+
341 roundup(sizeof(*desc_p
), ARCH_DMA_MINALIGN
);
342 ulong data_start
= desc_p
->dmamac_addr
;
343 ulong data_end
= data_start
+ roundup(length
, ARCH_DMA_MINALIGN
);
345 * Strictly we only need to invalidate the "txrx_status" field
346 * for the following check, but on some platforms we cannot
347 * invalidate only 4 bytes, so we flush the entire descriptor,
348 * which is 16 bytes in total. This is safe because the
349 * individual descriptors in the array are each aligned to
350 * ARCH_DMA_MINALIGN and padded appropriately.
352 invalidate_dcache_range(desc_start
, desc_end
);
354 /* Check if the descriptor is owned by CPU */
355 if (desc_p
->txrx_status
& DESC_TXSTS_OWNBYDMA
) {
356 printf("CPU not owner of tx frame\n");
360 memcpy((void *)data_start
, packet
, length
);
362 /* Flush data to be sent */
363 flush_dcache_range(data_start
, data_end
);
365 #if defined(CONFIG_DW_ALTDESCRIPTOR)
366 desc_p
->txrx_status
|= DESC_TXSTS_TXFIRST
| DESC_TXSTS_TXLAST
;
367 desc_p
->dmamac_cntl
|= (length
<< DESC_TXCTRL_SIZE1SHFT
) &
368 DESC_TXCTRL_SIZE1MASK
;
370 desc_p
->txrx_status
&= ~(DESC_TXSTS_MSK
);
371 desc_p
->txrx_status
|= DESC_TXSTS_OWNBYDMA
;
373 desc_p
->dmamac_cntl
|= ((length
<< DESC_TXCTRL_SIZE1SHFT
) &
374 DESC_TXCTRL_SIZE1MASK
) | DESC_TXCTRL_TXLAST
|
377 desc_p
->txrx_status
= DESC_TXSTS_OWNBYDMA
;
380 /* Flush modified buffer descriptor */
381 flush_dcache_range(desc_start
, desc_end
);
383 /* Test the wrap-around condition. */
384 if (++desc_num
>= CONFIG_TX_DESCR_NUM
)
387 priv
->tx_currdescnum
= desc_num
;
389 /* Start the transmission */
390 writel(POLL_DATA
, &dma_p
->txpolldemand
);
395 static int _dw_eth_recv(struct dw_eth_dev
*priv
, uchar
**packetp
)
397 u32 status
, desc_num
= priv
->rx_currdescnum
;
398 struct dmamacdescr
*desc_p
= &priv
->rx_mac_descrtable
[desc_num
];
399 int length
= -EAGAIN
;
400 ulong desc_start
= (ulong
)desc_p
;
401 ulong desc_end
= desc_start
+
402 roundup(sizeof(*desc_p
), ARCH_DMA_MINALIGN
);
403 ulong data_start
= desc_p
->dmamac_addr
;
406 /* Invalidate entire buffer descriptor */
407 invalidate_dcache_range(desc_start
, desc_end
);
409 status
= desc_p
->txrx_status
;
411 /* Check if the owner is the CPU */
412 if (!(status
& DESC_RXSTS_OWNBYDMA
)) {
414 length
= (status
& DESC_RXSTS_FRMLENMSK
) >>
415 DESC_RXSTS_FRMLENSHFT
;
417 /* Invalidate received data */
418 data_end
= data_start
+ roundup(length
, ARCH_DMA_MINALIGN
);
419 invalidate_dcache_range(data_start
, data_end
);
420 *packetp
= (uchar
*)(ulong
)desc_p
->dmamac_addr
;
426 static int _dw_free_pkt(struct dw_eth_dev
*priv
)
428 u32 desc_num
= priv
->rx_currdescnum
;
429 struct dmamacdescr
*desc_p
= &priv
->rx_mac_descrtable
[desc_num
];
430 ulong desc_start
= (ulong
)desc_p
;
431 ulong desc_end
= desc_start
+
432 roundup(sizeof(*desc_p
), ARCH_DMA_MINALIGN
);
435 * Make the current descriptor valid again and go to
438 desc_p
->txrx_status
|= DESC_RXSTS_OWNBYDMA
;
440 /* Flush only status field - others weren't changed */
441 flush_dcache_range(desc_start
, desc_end
);
443 /* Test the wrap-around condition. */
444 if (++desc_num
>= CONFIG_RX_DESCR_NUM
)
446 priv
->rx_currdescnum
= desc_num
;
451 static int dw_phy_init(struct dw_eth_dev
*priv
, void *dev
)
453 struct phy_device
*phydev
;
454 int mask
= 0xffffffff, ret
;
456 #ifdef CONFIG_PHY_ADDR
457 mask
= 1 << CONFIG_PHY_ADDR
;
460 phydev
= phy_find_by_mask(priv
->bus
, mask
, priv
->interface
);
464 phy_connect_dev(phydev
, dev
);
466 phydev
->supported
&= PHY_GBIT_FEATURES
;
467 if (priv
->max_speed
) {
468 ret
= phy_set_supported(phydev
, priv
->max_speed
);
472 phydev
->advertising
= phydev
->supported
;
474 priv
->phydev
= phydev
;
480 #ifndef CONFIG_DM_ETH
481 static int dw_eth_init(struct eth_device
*dev
, bd_t
*bis
)
483 return _dw_eth_init(dev
->priv
, dev
->enetaddr
);
486 static int dw_eth_send(struct eth_device
*dev
, void *packet
, int length
)
488 return _dw_eth_send(dev
->priv
, packet
, length
);
491 static int dw_eth_recv(struct eth_device
*dev
)
496 length
= _dw_eth_recv(dev
->priv
, &packet
);
497 if (length
== -EAGAIN
)
499 net_process_received_packet(packet
, length
);
501 _dw_free_pkt(dev
->priv
);
506 static void dw_eth_halt(struct eth_device
*dev
)
508 return _dw_eth_halt(dev
->priv
);
511 static int dw_write_hwaddr(struct eth_device
*dev
)
513 return _dw_write_hwaddr(dev
->priv
, dev
->enetaddr
);
516 int designware_initialize(ulong base_addr
, u32 interface
)
518 struct eth_device
*dev
;
519 struct dw_eth_dev
*priv
;
521 dev
= (struct eth_device
*) malloc(sizeof(struct eth_device
));
526 * Since the priv structure contains the descriptors which need a strict
527 * buswidth alignment, memalign is used to allocate memory
529 priv
= (struct dw_eth_dev
*) memalign(ARCH_DMA_MINALIGN
,
530 sizeof(struct dw_eth_dev
));
536 if ((phys_addr_t
)priv
+ sizeof(*priv
) > (1ULL << 32)) {
537 printf("designware: buffers are outside DMA memory\n");
541 memset(dev
, 0, sizeof(struct eth_device
));
542 memset(priv
, 0, sizeof(struct dw_eth_dev
));
544 sprintf(dev
->name
, "dwmac.%lx", base_addr
);
545 dev
->iobase
= (int)base_addr
;
549 priv
->mac_regs_p
= (struct eth_mac_regs
*)base_addr
;
550 priv
->dma_regs_p
= (struct eth_dma_regs
*)(base_addr
+
553 dev
->init
= dw_eth_init
;
554 dev
->send
= dw_eth_send
;
555 dev
->recv
= dw_eth_recv
;
556 dev
->halt
= dw_eth_halt
;
557 dev
->write_hwaddr
= dw_write_hwaddr
;
561 priv
->interface
= interface
;
563 dw_mdio_init(dev
->name
, priv
->mac_regs_p
);
564 priv
->bus
= miiphy_get_dev_by_name(dev
->name
);
566 return dw_phy_init(priv
, dev
);
571 static int designware_eth_start(struct udevice
*dev
)
573 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
575 return _dw_eth_init(dev
->priv
, pdata
->enetaddr
);
578 static int designware_eth_send(struct udevice
*dev
, void *packet
, int length
)
580 struct dw_eth_dev
*priv
= dev_get_priv(dev
);
582 return _dw_eth_send(priv
, packet
, length
);
585 static int designware_eth_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
587 struct dw_eth_dev
*priv
= dev_get_priv(dev
);
589 return _dw_eth_recv(priv
, packetp
);
592 static int designware_eth_free_pkt(struct udevice
*dev
, uchar
*packet
,
595 struct dw_eth_dev
*priv
= dev_get_priv(dev
);
597 return _dw_free_pkt(priv
);
600 static void designware_eth_stop(struct udevice
*dev
)
602 struct dw_eth_dev
*priv
= dev_get_priv(dev
);
604 return _dw_eth_halt(priv
);
607 static int designware_eth_write_hwaddr(struct udevice
*dev
)
609 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
610 struct dw_eth_dev
*priv
= dev_get_priv(dev
);
612 return _dw_write_hwaddr(priv
, pdata
->enetaddr
);
615 static int designware_eth_bind(struct udevice
*dev
)
618 static int num_cards
;
621 /* Create a unique device name for PCI type devices */
622 if (device_is_on_pci_bus(dev
)) {
623 sprintf(name
, "eth_designware#%u", num_cards
++);
624 device_set_name(dev
, name
);
631 static int designware_eth_probe(struct udevice
*dev
)
633 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
634 struct dw_eth_dev
*priv
= dev_get_priv(dev
);
635 u32 iobase
= pdata
->iobase
;
641 * If we are on PCI bus, either directly attached to a PCI root port,
642 * or via a PCI bridge, fill in platdata before we probe the hardware.
644 if (device_is_on_pci_bus(dev
)) {
645 dm_pci_read_config32(dev
, PCI_BASE_ADDRESS_0
, &iobase
);
646 iobase
&= PCI_BASE_ADDRESS_MEM_MASK
;
647 iobase
= dm_pci_mem_to_phys(dev
, iobase
);
649 pdata
->iobase
= iobase
;
650 pdata
->phy_interface
= PHY_INTERFACE_MODE_RMII
;
654 debug("%s, iobase=%x, priv=%p\n", __func__
, iobase
, priv
);
656 priv
->mac_regs_p
= (struct eth_mac_regs
*)ioaddr
;
657 priv
->dma_regs_p
= (struct eth_dma_regs
*)(ioaddr
+ DW_DMA_BASE_OFFSET
);
658 priv
->interface
= pdata
->phy_interface
;
659 priv
->max_speed
= pdata
->max_speed
;
661 dw_mdio_init(dev
->name
, dev
);
662 priv
->bus
= miiphy_get_dev_by_name(dev
->name
);
664 ret
= dw_phy_init(priv
, dev
);
665 debug("%s, ret=%d\n", __func__
, ret
);
670 static int designware_eth_remove(struct udevice
*dev
)
672 struct dw_eth_dev
*priv
= dev_get_priv(dev
);
675 mdio_unregister(priv
->bus
);
676 mdio_free(priv
->bus
);
681 static const struct eth_ops designware_eth_ops
= {
682 .start
= designware_eth_start
,
683 .send
= designware_eth_send
,
684 .recv
= designware_eth_recv
,
685 .free_pkt
= designware_eth_free_pkt
,
686 .stop
= designware_eth_stop
,
687 .write_hwaddr
= designware_eth_write_hwaddr
,
690 static int designware_eth_ofdata_to_platdata(struct udevice
*dev
)
692 struct dw_eth_pdata
*dw_pdata
= dev_get_platdata(dev
);
693 #ifdef CONFIG_DM_GPIO
694 struct dw_eth_dev
*priv
= dev_get_priv(dev
);
696 struct eth_pdata
*pdata
= &dw_pdata
->eth_pdata
;
697 const char *phy_mode
;
699 #ifdef CONFIG_DM_GPIO
700 int reset_flags
= GPIOD_IS_OUT
;
704 pdata
->iobase
= dev_get_addr(dev
);
705 pdata
->phy_interface
= -1;
706 phy_mode
= fdt_getprop(gd
->fdt_blob
, dev
->of_offset
, "phy-mode", NULL
);
708 pdata
->phy_interface
= phy_get_interface_by_name(phy_mode
);
709 if (pdata
->phy_interface
== -1) {
710 debug("%s: Invalid PHY interface '%s'\n", __func__
, phy_mode
);
714 pdata
->max_speed
= 0;
715 cell
= fdt_getprop(gd
->fdt_blob
, dev
->of_offset
, "max-speed", NULL
);
717 pdata
->max_speed
= fdt32_to_cpu(*cell
);
719 #ifdef CONFIG_DM_GPIO
720 if (fdtdec_get_bool(gd
->fdt_blob
, dev
->of_offset
,
721 "snps,reset-active-low"))
722 reset_flags
|= GPIOD_ACTIVE_LOW
;
724 ret
= gpio_request_by_name(dev
, "snps,reset-gpio", 0,
725 &priv
->reset_gpio
, reset_flags
);
727 ret
= fdtdec_get_int_array(gd
->fdt_blob
, dev
->of_offset
,
728 "snps,reset-delays-us", dw_pdata
->reset_delays
, 3);
729 } else if (ret
== -ENOENT
) {
737 static const struct udevice_id designware_eth_ids
[] = {
738 { .compatible
= "allwinner,sun7i-a20-gmac" },
739 { .compatible
= "altr,socfpga-stmmac" },
740 { .compatible
= "amlogic,meson6-dwmac" },
744 U_BOOT_DRIVER(eth_designware
) = {
745 .name
= "eth_designware",
747 .of_match
= designware_eth_ids
,
748 .ofdata_to_platdata
= designware_eth_ofdata_to_platdata
,
749 .bind
= designware_eth_bind
,
750 .probe
= designware_eth_probe
,
751 .remove
= designware_eth_remove
,
752 .ops
= &designware_eth_ops
,
753 .priv_auto_alloc_size
= sizeof(struct dw_eth_dev
),
754 .platdata_auto_alloc_size
= sizeof(struct dw_eth_pdata
),
755 .flags
= DM_FLAG_ALLOC_PRIV_DMA
,
758 static struct pci_device_id supported
[] = {
759 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_QRK_EMAC
) },
763 U_BOOT_PCI_DEVICE(eth_designware
, supported
);