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git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/net/dm9000x.c
2 dm9000.c: Version 1.2 12/15/2003
4 A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
5 Copyright (C) 1997 Sten Wang
7 This program is free software; you can redistribute it and/or
8 modify it under the terms of the GNU General Public License
9 as published by the Free Software Foundation; either version 2
10 of the License, or (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
19 V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
20 06/22/2001 Support DM9801 progrmming
21 E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
22 E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
23 R17 = (R17 & 0xfff0) | NF + 3
24 E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
25 R17 = (R17 & 0xfff0) | NF
27 v1.00 modify by simon 2001.9.5
28 change for kernel 2.4.x
30 v1.1 11/09/2001 fix force mode bug
32 v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
34 Added tx/rx 32 bit mode.
35 Cleaned up for kernel merge.
37 --------------------------------------
39 12/15/2003 Initial port to u-boot by Sascha Hauer <saschahauer@web.de>
41 TODO: Homerun NIC and longrun NIC are not functional, only internal at the
50 #ifdef CONFIG_DRIVER_DM9000
54 /* Board/System/Debug information/definition ---------------- */
56 #define DM9801_NOISE_FLOOR 0x08
57 #define DM9802_NOISE_FLOOR 0x05
59 /* #define CONFIG_DM9000_DEBUG */
61 #ifdef CONFIG_DM9000_DEBUG
62 #define DM9000_DBG(fmt,args...) printf(fmt ,##args)
64 #define DM9000_DBG(fmt,args...)
66 enum DM9000_PHY_mode
{ DM9000_10MHD
= 0, DM9000_100MHD
=
67 1, DM9000_10MFD
= 4, DM9000_100MFD
= 5, DM9000_AUTO
=
68 8, DM9000_1M_HPNA
= 0x10
70 enum DM9000_NIC_TYPE
{ FASTETHER_NIC
= 0, HOMERUN_NIC
= 1, LONGRUN_NIC
= 2
73 /* Structure/enum declaration ------------------------------- */
74 typedef struct board_info
{
75 u32 runt_length_counter
; /* counter: RX length < 64byte */
76 u32 long_length_counter
; /* counter: RX length > 1514byte */
77 u32 reset_counter
; /* counter: RESET */
78 u32 reset_tx_timeout
; /* RESET caused by TX Timeout */
79 u32 reset_rx_status
; /* RESET caused by RX Statsus wrong */
84 u8 device_wait_reset
; /* device state */
85 u8 nic_type
; /* NIC type */
86 unsigned char srom
[128];
88 board_info_t dmfe_info
;
90 /* For module input parameter */
91 static int media_mode
= DM9000_AUTO
;
94 /* function declaration ------------------------------------- */
95 int eth_init(bd_t
* bd
);
96 int eth_send(volatile void *, int);
99 static int dm9000_probe(void);
100 static u16
phy_read(int);
101 static void phy_write(int, u16
);
102 u16
read_srom_word(int);
103 static u8
DM9000_ior(int);
104 static void DM9000_iow(int reg
, u8 value
);
106 /* DM9000 network board routine ---------------------------- */
108 #define DM9000_outb(d,r) ( *(volatile u8 *)r = d )
109 #define DM9000_outw(d,r) ( *(volatile u16 *)r = d )
110 #define DM9000_outl(d,r) ( *(volatile u32 *)r = d )
111 #define DM9000_inb(r) (*(volatile u8 *)r)
112 #define DM9000_inw(r) (*(volatile u16 *)r)
113 #define DM9000_inl(r) (*(volatile u32 *)r)
115 #ifdef CONFIG_DM9000_DEBUG
120 DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0));
121 DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1));
122 DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2));
123 DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3));
124 DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4));
125 DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5));
126 DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6));
127 DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(ISR
));
133 Search DM9000 board, allocate space and register it
139 id_val
= DM9000_ior(DM9000_VIDL
);
140 id_val
|= DM9000_ior(DM9000_VIDH
) << 8;
141 id_val
|= DM9000_ior(DM9000_PIDL
) << 16;
142 id_val
|= DM9000_ior(DM9000_PIDH
) << 24;
143 if (id_val
== DM9000_ID
) {
144 printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE
,
148 printf("dm9000 not found at 0x%08x id: 0x%08x\n",
149 CONFIG_DM9000_BASE
, id_val
);
154 /* Set PHY operationg mode
159 u16 phy_reg4
= 0x01e1, phy_reg0
= 0x1000;
160 if (!(media_mode
& DM9000_AUTO
)) {
161 switch (media_mode
) {
179 phy_write(4, phy_reg4
); /* Set PHY media mode */
180 phy_write(0, phy_reg0
); /* Tmp */
182 DM9000_iow(DM9000_GPCR
, 0x01); /* Let GPIO0 output */
183 DM9000_iow(DM9000_GPR
, 0x00); /* Enable PHY */
190 program_dm9801(u16 HPNA_rev
)
192 __u16 reg16
, reg17
, reg24
, reg25
;
194 nfloor
= DM9801_NOISE_FLOOR
;
195 reg16
= phy_read(16);
196 reg17
= phy_read(17);
197 reg24
= phy_read(24);
198 reg25
= phy_read(25);
200 case 0xb900: /* DM9801 E3 */
202 reg25
= ((reg24
+ nfloor
) & 0x00ff) | 0xf000;
204 case 0xb901: /* DM9801 E4 */
205 reg25
= ((reg24
+ nfloor
) & 0x00ff) | 0xc200;
206 reg17
= (reg17
& 0xfff0) + nfloor
+ 3;
208 case 0xb902: /* DM9801 E5 */
209 case 0xb903: /* DM9801 E6 */
212 reg25
= ((reg24
+ nfloor
- 3) & 0x00ff) | 0xc200;
213 reg17
= (reg17
& 0xfff0) + nfloor
;
215 phy_write(16, reg16
);
216 phy_write(17, reg17
);
217 phy_write(25, reg25
);
228 nfloor
= DM9802_NOISE_FLOOR
;
229 reg25
= phy_read(25);
230 reg25
= (reg25
& 0xff00) + nfloor
;
231 phy_write(25, reg25
);
239 struct board_info
*db
= &dmfe_info
; /* Point a board information structure */
241 DM9000_iow(DM9000_NCR
, NCR_EXT_PHY
);
242 phy_reg3
= phy_read(3);
243 switch (phy_reg3
& 0xfff0) {
245 if (phy_read(31) == 0x4404) {
246 db
->nic_type
= HOMERUN_NIC
;
247 program_dm9801(phy_reg3
);
248 DM9000_DBG("found homerun NIC\n");
250 db
->nic_type
= LONGRUN_NIC
;
251 DM9000_DBG("found longrun NIC\n");
256 db
->nic_type
= FASTETHER_NIC
;
259 DM9000_iow(DM9000_NCR
, 0);
262 /* General Purpose dm9000 reset routine */
266 DM9000_DBG("resetting\n");
267 DM9000_iow(DM9000_NCR
, NCR_RST
);
268 udelay(1000); /* delay 1ms */
271 /* Initilize dm9000 board
277 DM9000_DBG("eth_init()\n");
283 /* NIC Type: FASTETHER, HOMERUN, LONGRUN */
286 /* GPIO0 on pre-activate PHY */
287 DM9000_iow(DM9000_GPR
, 0x00); /*REG_1F bit0 activate phyxcer */
292 /* Program operating register */
293 DM9000_iow(DM9000_NCR
, 0x0); /* only intern phy supported by now */
294 DM9000_iow(DM9000_TCR
, 0); /* TX Polling clear */
295 DM9000_iow(DM9000_BPTR
, 0x3f); /* Less 3Kb, 200us */
296 DM9000_iow(DM9000_FCTR
, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */
297 DM9000_iow(DM9000_FCR
, 0x0); /* SH FIXME: This looks strange! Flow Control */
298 DM9000_iow(DM9000_SMCR
, 0); /* Special Mode */
299 DM9000_iow(DM9000_NSR
, NSR_WAKEST
| NSR_TX2END
| NSR_TX1END
); /* clear TX status */
300 DM9000_iow(DM9000_ISR
, 0x0f); /* Clear interrupt status */
302 /* Set Node address */
303 #ifndef CONFIG_AT91SAM9261EK
304 for (i
= 0; i
< 6; i
++)
305 ((u16
*) bd
->bi_enetaddr
)[i
] = read_srom_word(i
);
308 if (is_zero_ether_addr(bd
->bi_enetaddr
) ||
309 is_multicast_ether_addr(bd
->bi_enetaddr
)) {
310 /* try reading from environment */
313 s
= getenv ("ethaddr");
314 for (i
= 0; i
< 6; ++i
) {
315 bd
->bi_enetaddr
[i
] = s
?
316 simple_strtoul (s
, &e
, 16) : 0;
318 s
= (*e
) ? e
+ 1 : e
;
322 printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd
->bi_enetaddr
[0],
323 bd
->bi_enetaddr
[1], bd
->bi_enetaddr
[2], bd
->bi_enetaddr
[3],
324 bd
->bi_enetaddr
[4], bd
->bi_enetaddr
[5]);
325 for (i
= 0, oft
= 0x10; i
< 6; i
++, oft
++)
326 DM9000_iow(oft
, bd
->bi_enetaddr
[i
]);
327 for (i
= 0, oft
= 0x16; i
< 8; i
++, oft
++)
328 DM9000_iow(oft
, 0xff);
330 /* read back mac, just to be sure */
331 for (i
= 0, oft
= 0x10; i
< 6; i
++, oft
++)
332 DM9000_DBG("%02x:", DM9000_ior(oft
));
335 /* Activate DM9000 */
336 DM9000_iow(DM9000_RCR
, RCR_DIS_LONG
| RCR_DIS_CRC
| RCR_RXEN
); /* RX enable */
337 DM9000_iow(DM9000_IMR
, IMR_PAR
); /* Enable TX/RX interrupt mask */
339 while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */
343 printf("could not establish link\n");
348 /* see what we've got */
349 lnk
= phy_read(17) >> 12;
350 printf("operating at ");
353 printf("10M half duplex ");
356 printf("10M full duplex ");
359 printf("100M half duplex ");
362 printf("100M full duplex ");
365 printf("unknown: %d ", lnk
);
373 Hardware start transmission.
374 Send a packet to media from the upper layer.
377 eth_send(volatile void *packet
, int length
)
382 DM9000_DBG("eth_send: length: %d\n", length
);
383 for (i
= 0; i
< length
; i
++) {
385 DM9000_DBG("\nSend: 02x: ", i
);
386 DM9000_DBG("%02x ", ((unsigned char *) packet
)[i
]);
389 /* Move data to DM9000 TX RAM */
390 data_ptr
= (char *) packet
;
391 DM9000_outb(DM9000_MWCMD
, DM9000_IO
);
393 #ifdef CONFIG_DM9000_USE_8BIT
395 for (i
= 0; i
< length
; i
++)
396 DM9000_outb((data_ptr
[i
] & 0xff), DM9000_DATA
);
399 #ifdef CONFIG_DM9000_USE_16BIT
400 tmplen
= (length
+ 1) / 2;
401 for (i
= 0; i
< tmplen
; i
++)
402 DM9000_outw(((u16
*) data_ptr
)[i
], DM9000_DATA
);
405 #ifdef CONFIG_DM9000_USE_32BIT
406 tmplen
= (length
+ 3) / 4;
407 for (i
= 0; i
< tmplen
; i
++)
408 DM9000_outl(((u32
*) data_ptr
)[i
], DM9000_DATA
);
412 /* Set TX length to DM9000 */
413 DM9000_iow(DM9000_TXPLL
, length
& 0xff);
414 DM9000_iow(DM9000_TXPLH
, (length
>> 8) & 0xff);
416 /* Issue TX polling command */
417 DM9000_iow(DM9000_TCR
, TCR_TXREQ
); /* Cleared after TX complete */
419 /* wait for end of transmission */
420 tmo
= get_timer(0) + 5 * CFG_HZ
;
421 while (DM9000_ior(DM9000_TCR
) & TCR_TXREQ
) {
422 if (get_timer(0) >= tmo
) {
423 printf("transmission timeout\n");
427 DM9000_DBG("transmit done\n\n");
433 The interface is stopped when it is brought.
438 DM9000_DBG("eth_halt\n");
441 phy_write(0, 0x8000); /* PHY RESET */
442 DM9000_iow(DM9000_GPR
, 0x01); /* Power-Down PHY */
443 DM9000_iow(DM9000_IMR
, 0x80); /* Disable all interrupt */
444 DM9000_iow(DM9000_RCR
, 0x00); /* Disable RX */
448 Received a packet and pass to upper layer
453 u8 rxbyte
, *rdptr
= (u8
*) NetRxPackets
[0];
454 u16 RxStatus
, RxLen
= 0;
456 #ifdef CONFIG_DM9000_USE_32BIT
460 /* Check packet ready or not */
461 DM9000_ior(DM9000_MRCMDX
); /* Dummy read */
462 rxbyte
= DM9000_inb(DM9000_DATA
); /* Got most updated data */
466 /* Status check: this byte must be 0 or 1 */
468 DM9000_iow(DM9000_RCR
, 0x00); /* Stop Device */
469 DM9000_iow(DM9000_ISR
, 0x80); /* Stop INT request */
470 DM9000_DBG("rx status check: %d\n", rxbyte
);
472 DM9000_DBG("receiving packet\n");
474 /* A packet ready now & Get status/length */
475 DM9000_outb(DM9000_MRCMD
, DM9000_IO
);
477 #ifdef CONFIG_DM9000_USE_8BIT
478 RxStatus
= DM9000_inb(DM9000_DATA
) + (DM9000_inb(DM9000_DATA
) << 8);
479 RxLen
= DM9000_inb(DM9000_DATA
) + (DM9000_inb(DM9000_DATA
) << 8);
482 #ifdef CONFIG_DM9000_USE_16BIT
483 RxStatus
= DM9000_inw(DM9000_DATA
);
484 RxLen
= DM9000_inw(DM9000_DATA
);
487 #ifdef CONFIG_DM9000_USE_32BIT
488 tmpdata
= DM9000_inl(DM9000_DATA
);
490 RxLen
= tmpdata
>> 16;
493 DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus
, RxLen
);
495 /* Move data from DM9000 */
496 /* Read received packet from RX SRAM */
497 #ifdef CONFIG_DM9000_USE_8BIT
498 for (i
= 0; i
< RxLen
; i
++)
499 rdptr
[i
] = DM9000_inb(DM9000_DATA
);
502 #ifdef CONFIG_DM9000_USE_16BIT
503 tmplen
= (RxLen
+ 1) / 2;
504 for (i
= 0; i
< tmplen
; i
++)
505 ((u16
*) rdptr
)[i
] = DM9000_inw(DM9000_DATA
);
508 #ifdef CONFIG_DM9000_USE_32BIT
509 tmplen
= (RxLen
+ 3) / 4;
510 for (i
= 0; i
< tmplen
; i
++)
511 ((u32
*) rdptr
)[i
] = DM9000_inl(DM9000_DATA
);
514 if ((RxStatus
& 0xbf00) || (RxLen
< 0x40)
515 || (RxLen
> DM9000_PKT_MAX
)) {
516 if (RxStatus
& 0x100) {
517 printf("rx fifo error\n");
519 if (RxStatus
& 0x200) {
520 printf("rx crc error\n");
522 if (RxStatus
& 0x8000) {
523 printf("rx length error\n");
525 if (RxLen
> DM9000_PKT_MAX
) {
526 printf("rx length too big\n");
531 /* Pass to upper layer */
532 DM9000_DBG("passing packet to upper layer\n");
533 NetReceive(NetRxPackets
[0], RxLen
);
540 Read a word data from SROM
543 read_srom_word(int offset
)
545 DM9000_iow(DM9000_EPAR
, offset
);
546 DM9000_iow(DM9000_EPCR
, 0x4);
548 DM9000_iow(DM9000_EPCR
, 0x0);
549 return (DM9000_ior(DM9000_EPDRL
) + (DM9000_ior(DM9000_EPDRH
) << 8));
553 write_srom_word(int offset
, u16 val
)
555 DM9000_iow(DM9000_EPAR
, offset
);
556 DM9000_iow(DM9000_EPDRH
, ((val
>> 8) & 0xff));
557 DM9000_iow(DM9000_EPDRL
, (val
& 0xff));
558 DM9000_iow(DM9000_EPCR
, 0x12);
560 DM9000_iow(DM9000_EPCR
, 0);
565 Read a byte from I/O port
570 DM9000_outb(reg
, DM9000_IO
);
571 return DM9000_inb(DM9000_DATA
);
575 Write a byte to I/O port
578 DM9000_iow(int reg
, u8 value
)
580 DM9000_outb(reg
, DM9000_IO
);
581 DM9000_outb(value
, DM9000_DATA
);
585 Read a word from phyxcer
592 /* Fill the phyxcer register into REG_0C */
593 DM9000_iow(DM9000_EPAR
, DM9000_PHY
| reg
);
594 DM9000_iow(DM9000_EPCR
, 0xc); /* Issue phyxcer read command */
595 udelay(100); /* Wait read complete */
596 DM9000_iow(DM9000_EPCR
, 0x0); /* Clear phyxcer read command */
597 val
= (DM9000_ior(DM9000_EPDRH
) << 8) | DM9000_ior(DM9000_EPDRL
);
599 /* The read data keeps on REG_0D & REG_0E */
600 DM9000_DBG("phy_read(%d): %d\n", reg
, val
);
605 Write a word to phyxcer
608 phy_write(int reg
, u16 value
)
611 /* Fill the phyxcer register into REG_0C */
612 DM9000_iow(DM9000_EPAR
, DM9000_PHY
| reg
);
614 /* Fill the written data into REG_0D & REG_0E */
615 DM9000_iow(DM9000_EPDRL
, (value
& 0xff));
616 DM9000_iow(DM9000_EPDRH
, ((value
>> 8) & 0xff));
617 DM9000_iow(DM9000_EPCR
, 0xa); /* Issue phyxcer write command */
618 udelay(500); /* Wait write complete */
619 DM9000_iow(DM9000_EPCR
, 0x0); /* Clear phyxcer write command */
620 DM9000_DBG("phy_write(reg:%d, value:%d)\n", reg
, value
);
622 #endif /* CONFIG_DRIVER_DM9000 */