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Merge git://git.denx.de/u-boot-mmc
[people/ms/u-boot.git] / drivers / net / eepro100.c
1 /*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <malloc.h>
10 #include <net.h>
11 #include <netdev.h>
12 #include <asm/io.h>
13 #include <pci.h>
14 #include <miiphy.h>
15
16 #undef DEBUG
17
18 /* Ethernet chip registers.
19 */
20 #define SCBStatus 0 /* Rx/Command Unit Status *Word* */
21 #define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */
22 #define SCBCmd 2 /* Rx/Command Unit Command *Word* */
23 #define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */
24 #define SCBPointer 4 /* General purpose pointer. */
25 #define SCBPort 8 /* Misc. commands and operands. */
26 #define SCBflash 12 /* Flash memory control. */
27 #define SCBeeprom 14 /* EEPROM memory control. */
28 #define SCBCtrlMDI 16 /* MDI interface control. */
29 #define SCBEarlyRx 20 /* Early receive byte count. */
30 #define SCBGenControl 28 /* 82559 General Control Register */
31 #define SCBGenStatus 29 /* 82559 General Status register */
32
33 /* 82559 SCB status word defnitions
34 */
35 #define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */
36 #define SCB_STATUS_FR 0x4000 /* frame received */
37 #define SCB_STATUS_CNA 0x2000 /* CU left active state */
38 #define SCB_STATUS_RNR 0x1000 /* receiver left ready state */
39 #define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */
40 #define SCB_STATUS_SWI 0x0400 /* software generated interrupt */
41 #define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */
42
43 #define SCB_INTACK_MASK 0xFD00 /* all the above */
44
45 #define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA)
46 #define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR)
47
48 /* System control block commands
49 */
50 /* CU Commands */
51 #define CU_NOP 0x0000
52 #define CU_START 0x0010
53 #define CU_RESUME 0x0020
54 #define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */
55 #define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */
56 #define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */
57 #define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */
58
59 /* RUC Commands */
60 #define RUC_NOP 0x0000
61 #define RUC_START 0x0001
62 #define RUC_RESUME 0x0002
63 #define RUC_ABORT 0x0004
64 #define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */
65 #define RUC_RESUMENR 0x0007
66
67 #define CU_CMD_MASK 0x00f0
68 #define RU_CMD_MASK 0x0007
69
70 #define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */
71 #define SCB_SWI 0x0200 /* 1 - cause device to interrupt */
72
73 #define CU_STATUS_MASK 0x00C0
74 #define RU_STATUS_MASK 0x003C
75
76 #define RU_STATUS_IDLE (0<<2)
77 #define RU_STATUS_SUS (1<<2)
78 #define RU_STATUS_NORES (2<<2)
79 #define RU_STATUS_READY (4<<2)
80 #define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2))
81 #define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2))
82 #define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2))
83
84 /* 82559 Port interface commands.
85 */
86 #define I82559_RESET 0x00000000 /* Software reset */
87 #define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */
88 #define I82559_SELECTIVE_RESET 0x00000002
89 #define I82559_DUMP 0x00000003
90 #define I82559_DUMP_WAKEUP 0x00000007
91
92 /* 82559 Eeprom interface.
93 */
94 #define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
95 #define EE_CS 0x02 /* EEPROM chip select. */
96 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
97 #define EE_WRITE_0 0x01
98 #define EE_WRITE_1 0x05
99 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
100 #define EE_ENB (0x4800 | EE_CS)
101 #define EE_CMD_BITS 3
102 #define EE_DATA_BITS 16
103
104 /* The EEPROM commands include the alway-set leading bit.
105 */
106 #define EE_EWENB_CMD (4 << addr_len)
107 #define EE_WRITE_CMD (5 << addr_len)
108 #define EE_READ_CMD (6 << addr_len)
109 #define EE_ERASE_CMD (7 << addr_len)
110
111 /* Receive frame descriptors.
112 */
113 struct RxFD {
114 volatile u16 status;
115 volatile u16 control;
116 volatile u32 link; /* struct RxFD * */
117 volatile u32 rx_buf_addr; /* void * */
118 volatile u32 count;
119
120 volatile u8 data[PKTSIZE_ALIGN];
121 };
122
123 #define RFD_STATUS_C 0x8000 /* completion of received frame */
124 #define RFD_STATUS_OK 0x2000 /* frame received with no errors */
125
126 #define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */
127 #define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */
128 #define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */
129 #define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */
130
131 #define RFD_COUNT_MASK 0x3fff
132 #define RFD_COUNT_F 0x4000
133 #define RFD_COUNT_EOF 0x8000
134
135 #define RFD_RX_CRC 0x0800 /* crc error */
136 #define RFD_RX_ALIGNMENT 0x0400 /* alignment error */
137 #define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */
138 #define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */
139 #define RFD_RX_SHORT 0x0080 /* short frame error */
140 #define RFD_RX_LENGTH 0x0020
141 #define RFD_RX_ERROR 0x0010 /* receive error */
142 #define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */
143 #define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */
144 #define RFD_RX_TCO 0x0001 /* TCO indication */
145
146 /* Transmit frame descriptors
147 */
148 struct TxFD { /* Transmit frame descriptor set. */
149 volatile u16 status;
150 volatile u16 command;
151 volatile u32 link; /* void * */
152 volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */
153 volatile s32 count;
154
155 volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */
156 volatile s32 tx_buf_size0; /* Length of Tx frame. */
157 volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */
158 volatile s32 tx_buf_size1; /* Length of Tx frame. */
159 };
160
161 #define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */
162 #define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */
163 #define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */
164 #define TxCB_CMD_I 0x2000 /* generate interrupt on completion */
165 #define TxCB_CMD_S 0x4000 /* suspend on completion */
166 #define TxCB_CMD_EL 0x8000 /* last command block in CBL */
167
168 #define TxCB_COUNT_MASK 0x3fff
169 #define TxCB_COUNT_EOF 0x8000
170
171 /* The Speedo3 Rx and Tx frame/buffer descriptors.
172 */
173 struct descriptor { /* A generic descriptor. */
174 volatile u16 status;
175 volatile u16 command;
176 volatile u32 link; /* struct descriptor * */
177
178 unsigned char params[0];
179 };
180
181 #define CONFIG_SYS_CMD_EL 0x8000
182 #define CONFIG_SYS_CMD_SUSPEND 0x4000
183 #define CONFIG_SYS_CMD_INT 0x2000
184 #define CONFIG_SYS_CMD_IAS 0x0001 /* individual address setup */
185 #define CONFIG_SYS_CMD_CONFIGURE 0x0002 /* configure */
186
187 #define CONFIG_SYS_STATUS_C 0x8000
188 #define CONFIG_SYS_STATUS_OK 0x2000
189
190 /* Misc.
191 */
192 #define NUM_RX_DESC PKTBUFSRX
193 #define NUM_TX_DESC 1 /* Number of TX descriptors */
194
195 #define TOUT_LOOP 1000000
196
197 #define ETH_ALEN 6
198
199 static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
200 static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
201 static int rx_next; /* RX descriptor ring pointer */
202 static int tx_next; /* TX descriptor ring pointer */
203 static int tx_threshold;
204
205 /*
206 * The parameters for a CmdConfigure operation.
207 * There are so many options that it would be difficult to document
208 * each bit. We mostly use the default or recommended settings.
209 */
210 static const char i82558_config_cmd[] = {
211 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */
212 0, 0x2E, 0, 0x60, 0x08, 0x88,
213 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */
214 0x31, 0x05,
215 };
216
217 static void init_rx_ring (struct eth_device *dev);
218 static void purge_tx_ring (struct eth_device *dev);
219
220 static void read_hw_addr (struct eth_device *dev, bd_t * bis);
221
222 static int eepro100_init (struct eth_device *dev, bd_t * bis);
223 static int eepro100_send(struct eth_device *dev, void *packet, int length);
224 static int eepro100_recv (struct eth_device *dev);
225 static void eepro100_halt (struct eth_device *dev);
226
227 #if defined(CONFIG_E500)
228 #define bus_to_phys(a) (a)
229 #define phys_to_bus(a) (a)
230 #else
231 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
232 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
233 #endif
234
235 static inline int INW (struct eth_device *dev, u_long addr)
236 {
237 return le16_to_cpu(*(volatile u16 *)(addr + (u_long)dev->iobase));
238 }
239
240 static inline void OUTW (struct eth_device *dev, int command, u_long addr)
241 {
242 *(volatile u16 *)((addr + (u_long)dev->iobase)) = cpu_to_le16(command);
243 }
244
245 static inline void OUTL (struct eth_device *dev, int command, u_long addr)
246 {
247 *(volatile u32 *)((addr + (u_long)dev->iobase)) = cpu_to_le32(command);
248 }
249
250 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
251 static inline int INL (struct eth_device *dev, u_long addr)
252 {
253 return le32_to_cpu(*(volatile u32 *)(addr + (u_long)dev->iobase));
254 }
255
256 static int get_phyreg (struct eth_device *dev, unsigned char addr,
257 unsigned char reg, unsigned short *value)
258 {
259 int cmd;
260 int timeout = 50;
261
262 /* read requested data */
263 cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
264 OUTL (dev, cmd, SCBCtrlMDI);
265
266 do {
267 udelay(1000);
268 cmd = INL (dev, SCBCtrlMDI);
269 } while (!(cmd & (1 << 28)) && (--timeout));
270
271 if (timeout == 0)
272 return -1;
273
274 *value = (unsigned short) (cmd & 0xffff);
275
276 return 0;
277 }
278
279 static int set_phyreg (struct eth_device *dev, unsigned char addr,
280 unsigned char reg, unsigned short value)
281 {
282 int cmd;
283 int timeout = 50;
284
285 /* write requested data */
286 cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
287 OUTL (dev, cmd | value, SCBCtrlMDI);
288
289 while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout))
290 udelay(1000);
291
292 if (timeout == 0)
293 return -1;
294
295 return 0;
296 }
297
298 /* Check if given phyaddr is valid, i.e. there is a PHY connected.
299 * Do this by checking model value field from ID2 register.
300 */
301 static struct eth_device* verify_phyaddr (const char *devname,
302 unsigned char addr)
303 {
304 struct eth_device *dev;
305 unsigned short value;
306 unsigned char model;
307
308 dev = eth_get_dev_by_name(devname);
309 if (dev == NULL) {
310 printf("%s: no such device\n", devname);
311 return NULL;
312 }
313
314 /* read id2 register */
315 if (get_phyreg(dev, addr, MII_PHYSID2, &value) != 0) {
316 printf("%s: mii read timeout!\n", devname);
317 return NULL;
318 }
319
320 /* get model */
321 model = (unsigned char)((value >> 4) & 0x003f);
322
323 if (model == 0) {
324 printf("%s: no PHY at address %d\n", devname, addr);
325 return NULL;
326 }
327
328 return dev;
329 }
330
331 static int eepro100_miiphy_read(struct mii_dev *bus, int addr, int devad,
332 int reg)
333 {
334 unsigned short value = 0;
335 struct eth_device *dev;
336
337 dev = verify_phyaddr(bus->name, addr);
338 if (dev == NULL)
339 return -1;
340
341 if (get_phyreg(dev, addr, reg, &value) != 0) {
342 printf("%s: mii read timeout!\n", bus->name);
343 return -1;
344 }
345
346 return value;
347 }
348
349 static int eepro100_miiphy_write(struct mii_dev *bus, int addr, int devad,
350 int reg, u16 value)
351 {
352 struct eth_device *dev;
353
354 dev = verify_phyaddr(bus->name, addr);
355 if (dev == NULL)
356 return -1;
357
358 if (set_phyreg(dev, addr, reg, value) != 0) {
359 printf("%s: mii write timeout!\n", bus->name);
360 return -1;
361 }
362
363 return 0;
364 }
365
366 #endif
367
368 /* Wait for the chip get the command.
369 */
370 static int wait_for_eepro100 (struct eth_device *dev)
371 {
372 int i;
373
374 for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
375 if (i >= TOUT_LOOP) {
376 return 0;
377 }
378 }
379
380 return 1;
381 }
382
383 static struct pci_device_id supported[] = {
384 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557},
385 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559},
386 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER},
387 {}
388 };
389
390 int eepro100_initialize (bd_t * bis)
391 {
392 pci_dev_t devno;
393 int card_number = 0;
394 struct eth_device *dev;
395 u32 iobase, status;
396 int idx = 0;
397
398 while (1) {
399 /* Find PCI device
400 */
401 if ((devno = pci_find_devices (supported, idx++)) < 0) {
402 break;
403 }
404
405 pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase);
406 iobase &= ~0xf;
407
408 #ifdef DEBUG
409 printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
410 iobase);
411 #endif
412
413 pci_write_config_dword (devno,
414 PCI_COMMAND,
415 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
416
417 /* Check if I/O accesses and Bus Mastering are enabled.
418 */
419 pci_read_config_dword (devno, PCI_COMMAND, &status);
420 if (!(status & PCI_COMMAND_MEMORY)) {
421 printf ("Error: Can not enable MEM access.\n");
422 continue;
423 }
424
425 if (!(status & PCI_COMMAND_MASTER)) {
426 printf ("Error: Can not enable Bus Mastering.\n");
427 continue;
428 }
429
430 dev = (struct eth_device *) malloc (sizeof *dev);
431 if (!dev) {
432 printf("eepro100: Can not allocate memory\n");
433 break;
434 }
435 memset(dev, 0, sizeof(*dev));
436
437 sprintf (dev->name, "i82559#%d", card_number);
438 dev->priv = (void *) devno; /* this have to come before bus_to_phys() */
439 dev->iobase = bus_to_phys (iobase);
440 dev->init = eepro100_init;
441 dev->halt = eepro100_halt;
442 dev->send = eepro100_send;
443 dev->recv = eepro100_recv;
444
445 eth_register (dev);
446
447 #if defined (CONFIG_MII) || defined(CONFIG_CMD_MII)
448 /* register mii command access routines */
449 int retval;
450 struct mii_dev *mdiodev = mdio_alloc();
451 if (!mdiodev)
452 return -ENOMEM;
453 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
454 mdiodev->read = eepro100_miiphy_read;
455 mdiodev->write = eepro100_miiphy_write;
456
457 retval = mdio_register(mdiodev);
458 if (retval < 0)
459 return retval;
460 #endif
461
462 card_number++;
463
464 /* Set the latency timer for value.
465 */
466 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
467
468 udelay (10 * 1000);
469
470 read_hw_addr (dev, bis);
471 }
472
473 return card_number;
474 }
475
476
477 static int eepro100_init (struct eth_device *dev, bd_t * bis)
478 {
479 int i, status = -1;
480 int tx_cur;
481 struct descriptor *ias_cmd, *cfg_cmd;
482
483 /* Reset the ethernet controller
484 */
485 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
486 udelay (20);
487
488 OUTL (dev, I82559_RESET, SCBPort);
489 udelay (20);
490
491 if (!wait_for_eepro100 (dev)) {
492 printf ("Error: Can not reset ethernet controller.\n");
493 goto Done;
494 }
495 OUTL (dev, 0, SCBPointer);
496 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
497
498 if (!wait_for_eepro100 (dev)) {
499 printf ("Error: Can not reset ethernet controller.\n");
500 goto Done;
501 }
502 OUTL (dev, 0, SCBPointer);
503 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
504
505 /* Initialize Rx and Tx rings.
506 */
507 init_rx_ring (dev);
508 purge_tx_ring (dev);
509
510 /* Tell the adapter where the RX ring is located.
511 */
512 if (!wait_for_eepro100 (dev)) {
513 printf ("Error: Can not reset ethernet controller.\n");
514 goto Done;
515 }
516
517 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
518 OUTW (dev, SCB_M | RUC_START, SCBCmd);
519
520 /* Send the Configure frame */
521 tx_cur = tx_next;
522 tx_next = ((tx_next + 1) % NUM_TX_DESC);
523
524 cfg_cmd = (struct descriptor *) &tx_ring[tx_cur];
525 cfg_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_CONFIGURE));
526 cfg_cmd->status = 0;
527 cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
528
529 memcpy (cfg_cmd->params, i82558_config_cmd,
530 sizeof (i82558_config_cmd));
531
532 if (!wait_for_eepro100 (dev)) {
533 printf ("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n");
534 goto Done;
535 }
536
537 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
538 OUTW (dev, SCB_M | CU_START, SCBCmd);
539
540 for (i = 0;
541 !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
542 i++) {
543 if (i >= TOUT_LOOP) {
544 printf ("%s: Tx error buffer not ready\n", dev->name);
545 goto Done;
546 }
547 }
548
549 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
550 printf ("TX error status = 0x%08X\n",
551 le16_to_cpu (tx_ring[tx_cur].status));
552 goto Done;
553 }
554
555 /* Send the Individual Address Setup frame
556 */
557 tx_cur = tx_next;
558 tx_next = ((tx_next + 1) % NUM_TX_DESC);
559
560 ias_cmd = (struct descriptor *) &tx_ring[tx_cur];
561 ias_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_IAS));
562 ias_cmd->status = 0;
563 ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
564
565 memcpy (ias_cmd->params, dev->enetaddr, 6);
566
567 /* Tell the adapter where the TX ring is located.
568 */
569 if (!wait_for_eepro100 (dev)) {
570 printf ("Error: Can not reset ethernet controller.\n");
571 goto Done;
572 }
573
574 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
575 OUTW (dev, SCB_M | CU_START, SCBCmd);
576
577 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
578 i++) {
579 if (i >= TOUT_LOOP) {
580 printf ("%s: Tx error buffer not ready\n",
581 dev->name);
582 goto Done;
583 }
584 }
585
586 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
587 printf ("TX error status = 0x%08X\n",
588 le16_to_cpu (tx_ring[tx_cur].status));
589 goto Done;
590 }
591
592 status = 0;
593
594 Done:
595 return status;
596 }
597
598 static int eepro100_send(struct eth_device *dev, void *packet, int length)
599 {
600 int i, status = -1;
601 int tx_cur;
602
603 if (length <= 0) {
604 printf ("%s: bad packet size: %d\n", dev->name, length);
605 goto Done;
606 }
607
608 tx_cur = tx_next;
609 tx_next = (tx_next + 1) % NUM_TX_DESC;
610
611 tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT |
612 TxCB_CMD_SF |
613 TxCB_CMD_S |
614 TxCB_CMD_EL );
615 tx_ring[tx_cur].status = 0;
616 tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold);
617 tx_ring[tx_cur].link =
618 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
619 tx_ring[tx_cur].tx_desc_addr =
620 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0));
621 tx_ring[tx_cur].tx_buf_addr0 =
622 cpu_to_le32 (phys_to_bus ((u_long) packet));
623 tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length);
624
625 if (!wait_for_eepro100 (dev)) {
626 printf ("%s: Tx error ethernet controller not ready.\n",
627 dev->name);
628 goto Done;
629 }
630
631 /* Send the packet.
632 */
633 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
634 OUTW (dev, SCB_M | CU_START, SCBCmd);
635
636 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
637 i++) {
638 if (i >= TOUT_LOOP) {
639 printf ("%s: Tx error buffer not ready\n", dev->name);
640 goto Done;
641 }
642 }
643
644 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
645 printf ("TX error status = 0x%08X\n",
646 le16_to_cpu (tx_ring[tx_cur].status));
647 goto Done;
648 }
649
650 status = length;
651
652 Done:
653 return status;
654 }
655
656 static int eepro100_recv (struct eth_device *dev)
657 {
658 u16 status, stat;
659 int rx_prev, length = 0;
660
661 stat = INW (dev, SCBStatus);
662 OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus);
663
664 for (;;) {
665 status = le16_to_cpu (rx_ring[rx_next].status);
666
667 if (!(status & RFD_STATUS_C)) {
668 break;
669 }
670
671 /* Valid frame status.
672 */
673 if ((status & RFD_STATUS_OK)) {
674 /* A valid frame received.
675 */
676 length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff;
677
678 /* Pass the packet up to the protocol
679 * layers.
680 */
681 net_process_received_packet((u8 *)rx_ring[rx_next].data,
682 length);
683 } else {
684 /* There was an error.
685 */
686 printf ("RX error status = 0x%08X\n", status);
687 }
688
689 rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S);
690 rx_ring[rx_next].status = 0;
691 rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
692
693 rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC;
694 rx_ring[rx_prev].control = 0;
695
696 /* Update entry information.
697 */
698 rx_next = (rx_next + 1) % NUM_RX_DESC;
699 }
700
701 if (stat & SCB_STATUS_RNR) {
702
703 printf ("%s: Receiver is not ready, restart it !\n", dev->name);
704
705 /* Reinitialize Rx ring.
706 */
707 init_rx_ring (dev);
708
709 if (!wait_for_eepro100 (dev)) {
710 printf ("Error: Can not restart ethernet controller.\n");
711 goto Done;
712 }
713
714 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
715 OUTW (dev, SCB_M | RUC_START, SCBCmd);
716 }
717
718 Done:
719 return length;
720 }
721
722 static void eepro100_halt (struct eth_device *dev)
723 {
724 /* Reset the ethernet controller
725 */
726 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
727 udelay (20);
728
729 OUTL (dev, I82559_RESET, SCBPort);
730 udelay (20);
731
732 if (!wait_for_eepro100 (dev)) {
733 printf ("Error: Can not reset ethernet controller.\n");
734 goto Done;
735 }
736 OUTL (dev, 0, SCBPointer);
737 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
738
739 if (!wait_for_eepro100 (dev)) {
740 printf ("Error: Can not reset ethernet controller.\n");
741 goto Done;
742 }
743 OUTL (dev, 0, SCBPointer);
744 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
745
746 Done:
747 return;
748 }
749
750 /* SROM Read.
751 */
752 static int read_eeprom (struct eth_device *dev, int location, int addr_len)
753 {
754 unsigned short retval = 0;
755 int read_cmd = location | EE_READ_CMD;
756 int i;
757
758 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
759 OUTW (dev, EE_ENB, SCBeeprom);
760
761 /* Shift the read command bits out. */
762 for (i = 12; i >= 0; i--) {
763 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
764
765 OUTW (dev, EE_ENB | dataval, SCBeeprom);
766 udelay (1);
767 OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
768 udelay (1);
769 }
770 OUTW (dev, EE_ENB, SCBeeprom);
771
772 for (i = 15; i >= 0; i--) {
773 OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom);
774 udelay (1);
775 retval = (retval << 1) |
776 ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0);
777 OUTW (dev, EE_ENB, SCBeeprom);
778 udelay (1);
779 }
780
781 /* Terminate the EEPROM access. */
782 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
783 return retval;
784 }
785
786 #ifdef CONFIG_EEPRO100_SROM_WRITE
787 int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data)
788 {
789 unsigned short dataval;
790 int enable_cmd = 0x3f | EE_EWENB_CMD;
791 int write_cmd = location | EE_WRITE_CMD;
792 int i;
793 unsigned long datalong, tmplong;
794
795 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
796 udelay(1);
797 OUTW(dev, EE_ENB, SCBeeprom);
798
799 /* Shift the enable command bits out. */
800 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
801 {
802 dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
803 OUTW(dev, EE_ENB | dataval, SCBeeprom);
804 udelay(1);
805 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
806 udelay(1);
807 }
808
809 OUTW(dev, EE_ENB, SCBeeprom);
810 udelay(1);
811 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
812 udelay(1);
813 OUTW(dev, EE_ENB, SCBeeprom);
814
815
816 /* Shift the write command bits out. */
817 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
818 {
819 dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
820 OUTW(dev, EE_ENB | dataval, SCBeeprom);
821 udelay(1);
822 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
823 udelay(1);
824 }
825
826 /* Write the data */
827 datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8));
828
829 for (i = 0; i< EE_DATA_BITS; i++)
830 {
831 /* Extract and move data bit to bit DI */
832 dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0;
833
834 OUTW(dev, EE_ENB | dataval, SCBeeprom);
835 udelay(1);
836 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
837 udelay(1);
838 OUTW(dev, EE_ENB | dataval, SCBeeprom);
839 udelay(1);
840
841 datalong = datalong << 1; /* Adjust significant data bit*/
842 }
843
844 /* Finish up command (toggle CS) */
845 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
846 udelay(1); /* delay for more than 250 ns */
847 OUTW(dev, EE_ENB, SCBeeprom);
848
849 /* Wait for programming ready (D0 = 1) */
850 tmplong = 10;
851 do
852 {
853 dataval = INW(dev, SCBeeprom);
854 if (dataval & EE_DATA_READ)
855 break;
856 udelay(10000);
857 }
858 while (-- tmplong);
859
860 if (tmplong == 0)
861 {
862 printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n");
863 return -1;
864 }
865
866 /* Terminate the EEPROM access. */
867 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
868
869 return 0;
870 }
871 #endif
872
873 static void init_rx_ring (struct eth_device *dev)
874 {
875 int i;
876
877 for (i = 0; i < NUM_RX_DESC; i++) {
878 rx_ring[i].status = 0;
879 rx_ring[i].control =
880 (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0;
881 rx_ring[i].link =
882 cpu_to_le32 (phys_to_bus
883 ((u32) & rx_ring[(i + 1) % NUM_RX_DESC]));
884 rx_ring[i].rx_buf_addr = 0xffffffff;
885 rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
886 }
887
888 rx_next = 0;
889 }
890
891 static void purge_tx_ring (struct eth_device *dev)
892 {
893 int i;
894
895 tx_next = 0;
896 tx_threshold = 0x01208000;
897
898 for (i = 0; i < NUM_TX_DESC; i++) {
899 tx_ring[i].status = 0;
900 tx_ring[i].command = 0;
901 tx_ring[i].link = 0;
902 tx_ring[i].tx_desc_addr = 0;
903 tx_ring[i].count = 0;
904
905 tx_ring[i].tx_buf_addr0 = 0;
906 tx_ring[i].tx_buf_size0 = 0;
907 tx_ring[i].tx_buf_addr1 = 0;
908 tx_ring[i].tx_buf_size1 = 0;
909 }
910 }
911
912 static void read_hw_addr (struct eth_device *dev, bd_t * bis)
913 {
914 u16 sum = 0;
915 int i, j;
916 int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6;
917
918 for (j = 0, i = 0; i < 0x40; i++) {
919 u16 value = read_eeprom (dev, i, addr_len);
920
921 sum += value;
922 if (i < 3) {
923 dev->enetaddr[j++] = value;
924 dev->enetaddr[j++] = value >> 8;
925 }
926 }
927
928 if (sum != 0xBABA) {
929 memset (dev->enetaddr, 0, ETH_ALEN);
930 #ifdef DEBUG
931 printf ("%s: Invalid EEPROM checksum %#4.4x, "
932 "check settings before activating this device!\n",
933 dev->name, sum);
934 #endif
935 }
936 }
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