2 * Ethernet driver for TI K2HK EVM.
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/ti-common/keystone_nav.h>
18 #include <asm/ti-common/keystone_net.h>
19 #include <asm/ti-common/keystone_serdes.h>
21 unsigned int emac_open
;
22 static struct mii_dev
*mdio_bus
;
23 static unsigned int sys_has_mdio
= 1;
25 #ifdef KEYSTONE2_EMAC_GIG_ENABLE
26 #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
28 #define emac_gigabit_enable(x) /* no gigabit to enable */
31 #define RX_BUFF_NUMS 24
32 #define RX_BUFF_LEN 1520
33 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
34 #define SGMII_ANEG_TIMEOUT 4000
36 static u8 rx_buffs
[RX_BUFF_NUMS
* RX_BUFF_LEN
] __aligned(16);
38 struct rx_buff_desc net_rx_buffs
= {
40 .num_buffs
= RX_BUFF_NUMS
,
41 .buff_len
= RX_BUFF_LEN
,
45 #ifndef CONFIG_SOC_K2G
46 static void keystone2_net_serdes_setup(void);
49 int keystone2_eth_read_mac_addr(struct eth_device
*dev
)
51 struct eth_priv_t
*eth_priv
;
55 eth_priv
= (struct eth_priv_t
*)dev
->priv
;
57 /* Read the e-fuse mac address */
58 if (eth_priv
->slave_port
== 1) {
59 maca
= __raw_readl(MAC_ID_BASE_ADDR
);
60 macb
= __raw_readl(MAC_ID_BASE_ADDR
+ 4);
63 dev
->enetaddr
[0] = (macb
>> 8) & 0xff;
64 dev
->enetaddr
[1] = (macb
>> 0) & 0xff;
65 dev
->enetaddr
[2] = (maca
>> 24) & 0xff;
66 dev
->enetaddr
[3] = (maca
>> 16) & 0xff;
67 dev
->enetaddr
[4] = (maca
>> 8) & 0xff;
68 dev
->enetaddr
[5] = (maca
>> 0) & 0xff;
75 static int keystone2_mdio_reset(struct mii_dev
*bus
)
78 struct mdio_regs
*adap_mdio
= bus
->priv
;
80 clkdiv
= (EMAC_MDIO_BUS_FREQ
/ EMAC_MDIO_CLOCK_FREQ
) - 1;
82 writel((clkdiv
& 0xffff) | MDIO_CONTROL_ENABLE
|
83 MDIO_CONTROL_FAULT
| MDIO_CONTROL_FAULT_ENABLE
,
86 while (readl(&adap_mdio
->control
) & MDIO_CONTROL_IDLE
)
93 * keystone2_mdio_read - read a PHY register via MDIO interface.
94 * Blocks until operation is complete.
96 static int keystone2_mdio_read(struct mii_dev
*bus
,
97 int addr
, int devad
, int reg
)
100 struct mdio_regs
*adap_mdio
= bus
->priv
;
102 while (readl(&adap_mdio
->useraccess0
) & MDIO_USERACCESS0_GO
)
105 writel(MDIO_USERACCESS0_GO
| MDIO_USERACCESS0_WRITE_READ
|
106 ((reg
& 0x1f) << 21) | ((addr
& 0x1f) << 16),
107 &adap_mdio
->useraccess0
);
109 /* Wait for command to complete */
110 while ((tmp
= readl(&adap_mdio
->useraccess0
)) & MDIO_USERACCESS0_GO
)
113 if (tmp
& MDIO_USERACCESS0_ACK
)
120 * keystone2_mdio_write - write to a PHY register via MDIO interface.
121 * Blocks until operation is complete.
123 static int keystone2_mdio_write(struct mii_dev
*bus
,
124 int addr
, int devad
, int reg
, u16 val
)
126 struct mdio_regs
*adap_mdio
= bus
->priv
;
128 while (readl(&adap_mdio
->useraccess0
) & MDIO_USERACCESS0_GO
)
131 writel(MDIO_USERACCESS0_GO
| MDIO_USERACCESS0_WRITE_WRITE
|
132 ((reg
& 0x1f) << 21) | ((addr
& 0x1f) << 16) |
133 (val
& 0xffff), &adap_mdio
->useraccess0
);
135 /* Wait for command to complete */
136 while (readl(&adap_mdio
->useraccess0
) & MDIO_USERACCESS0_GO
)
142 static void __attribute__((unused
))
143 keystone2_eth_gigabit_enable(struct eth_device
*dev
)
146 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
149 data
= keystone2_mdio_read(mdio_bus
, eth_priv
->phy_addr
,
151 /* speed selection MSB */
152 if (!(data
& (1 << 6)))
157 * Check if link detected is giga-bit
158 * If Gigabit mode detected, enable gigbit in MAC
160 writel(readl(DEVICE_EMACSL_BASE(eth_priv
->slave_port
- 1) +
162 EMAC_MACCONTROL_GIGFORCE
| EMAC_MACCONTROL_GIGABIT_ENABLE
,
163 DEVICE_EMACSL_BASE(eth_priv
->slave_port
- 1) + CPGMACSL_REG_CTL
);
166 int keystone_sgmii_link_status(int port
)
170 status
= __raw_readl(SGMII_STATUS_REG(port
));
172 return (status
& SGMII_REG_STATUS_LOCK
) &&
173 (status
& SGMII_REG_STATUS_LINK
);
176 #ifdef CONFIG_SOC_K2G
177 int keystone_rgmii_config(struct phy_device
*phy_dev
)
179 unsigned int i
, status
;
183 if (i
> SGMII_ANEG_TIMEOUT
) {
184 puts(" TIMEOUT !\n");
190 puts("user interrupt!\n");
195 if ((i
++ % 500) == 0)
198 udelay(1000); /* 1 ms */
199 status
= readl(RGMII_STATUS_REG
);
200 } while (!(status
& RGMII_REG_STATUS_LINK
));
207 int keystone_sgmii_config(struct phy_device
*phy_dev
, int port
, int interface
)
209 unsigned int i
, status
, mask
;
210 unsigned int mr_adv_ability
, control
;
213 case SGMII_LINK_MAC_MAC_AUTONEG
:
214 mr_adv_ability
= (SGMII_REG_MR_ADV_ENABLE
|
215 SGMII_REG_MR_ADV_LINK
|
216 SGMII_REG_MR_ADV_FULL_DUPLEX
|
217 SGMII_REG_MR_ADV_GIG_MODE
);
218 control
= (SGMII_REG_CONTROL_MASTER
|
219 SGMII_REG_CONTROL_AUTONEG
);
222 case SGMII_LINK_MAC_PHY
:
223 case SGMII_LINK_MAC_PHY_FORCED
:
224 mr_adv_ability
= SGMII_REG_MR_ADV_ENABLE
;
225 control
= SGMII_REG_CONTROL_AUTONEG
;
228 case SGMII_LINK_MAC_MAC_FORCED
:
229 mr_adv_ability
= (SGMII_REG_MR_ADV_ENABLE
|
230 SGMII_REG_MR_ADV_LINK
|
231 SGMII_REG_MR_ADV_FULL_DUPLEX
|
232 SGMII_REG_MR_ADV_GIG_MODE
);
233 control
= SGMII_REG_CONTROL_MASTER
;
236 case SGMII_LINK_MAC_FIBER
:
237 mr_adv_ability
= 0x20;
238 control
= SGMII_REG_CONTROL_AUTONEG
;
242 mr_adv_ability
= SGMII_REG_MR_ADV_ENABLE
;
243 control
= SGMII_REG_CONTROL_AUTONEG
;
246 __raw_writel(0, SGMII_CTL_REG(port
));
249 * Wait for the SerDes pll to lock,
250 * but don't trap if lock is never read
252 for (i
= 0; i
< 1000; i
++) {
254 status
= __raw_readl(SGMII_STATUS_REG(port
));
255 if ((status
& SGMII_REG_STATUS_LOCK
) != 0)
259 __raw_writel(mr_adv_ability
, SGMII_MRADV_REG(port
));
260 __raw_writel(control
, SGMII_CTL_REG(port
));
263 mask
= SGMII_REG_STATUS_LINK
;
265 if (control
& SGMII_REG_CONTROL_AUTONEG
)
266 mask
|= SGMII_REG_STATUS_AUTONEG
;
268 status
= __raw_readl(SGMII_STATUS_REG(port
));
269 if ((status
& mask
) == mask
)
272 printf("\n%s Waiting for SGMII auto negotiation to complete",
274 while ((status
& mask
) != mask
) {
278 if (i
> SGMII_ANEG_TIMEOUT
) {
279 puts(" TIMEOUT !\n");
285 puts("user interrupt!\n");
290 if ((i
++ % 500) == 0)
293 udelay(1000); /* 1 ms */
294 status
= __raw_readl(SGMII_STATUS_REG(port
));
302 int mac_sl_reset(u32 port
)
306 if (port
>= DEVICE_N_GMACSL_PORTS
)
307 return GMACSL_RET_INVALID_PORT
;
309 /* Set the soft reset bit */
310 writel(CPGMAC_REG_RESET_VAL_RESET
,
311 DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_RESET
);
313 /* Wait for the bit to clear */
314 for (i
= 0; i
< DEVICE_EMACSL_RESET_POLL_COUNT
; i
++) {
315 v
= readl(DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_RESET
);
316 if ((v
& CPGMAC_REG_RESET_VAL_RESET_MASK
) !=
317 CPGMAC_REG_RESET_VAL_RESET
)
318 return GMACSL_RET_OK
;
321 /* Timeout on the reset */
322 return GMACSL_RET_WARN_RESET_INCOMPLETE
;
325 int mac_sl_config(u_int16_t port
, struct mac_sl_cfg
*cfg
)
328 int ret
= GMACSL_RET_OK
;
330 if (port
>= DEVICE_N_GMACSL_PORTS
)
331 return GMACSL_RET_INVALID_PORT
;
333 if (cfg
->max_rx_len
> CPGMAC_REG_MAXLEN_LEN
) {
334 cfg
->max_rx_len
= CPGMAC_REG_MAXLEN_LEN
;
335 ret
= GMACSL_RET_WARN_MAXLEN_TOO_BIG
;
338 /* Must wait if the device is undergoing reset */
339 for (i
= 0; i
< DEVICE_EMACSL_RESET_POLL_COUNT
; i
++) {
340 v
= readl(DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_RESET
);
341 if ((v
& CPGMAC_REG_RESET_VAL_RESET_MASK
) !=
342 CPGMAC_REG_RESET_VAL_RESET
)
346 if (i
== DEVICE_EMACSL_RESET_POLL_COUNT
)
347 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE
;
349 writel(cfg
->max_rx_len
, DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_MAXLEN
);
350 writel(cfg
->ctl
, DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_CTL
);
352 #ifndef CONFIG_SOC_K2HK
353 /* Map RX packet flow priority to 0 */
354 writel(0, DEVICE_EMACSL_BASE(port
) + CPGMACSL_REG_RX_PRI_MAP
);
360 int ethss_config(u32 ctl
, u32 max_pkt_size
)
364 /* Max length register */
365 writel(max_pkt_size
, DEVICE_CPSW_BASE
+ CPSW_REG_MAXLEN
);
367 /* Control register */
368 writel(ctl
, DEVICE_CPSW_BASE
+ CPSW_REG_CTL
);
370 /* All statistics enabled by default */
371 writel(CPSW_REG_VAL_STAT_ENABLE_ALL
,
372 DEVICE_CPSW_BASE
+ CPSW_REG_STAT_PORT_EN
);
374 /* Reset and enable the ALE */
375 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE
|
376 CPSW_REG_VAL_ALE_CTL_BYPASS
,
377 DEVICE_CPSW_BASE
+ CPSW_REG_ALE_CONTROL
);
379 /* All ports put into forward mode */
380 for (i
= 0; i
< DEVICE_CPSW_NUM_PORTS
; i
++)
381 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE
,
382 DEVICE_CPSW_BASE
+ CPSW_REG_ALE_PORTCTL(i
));
387 int ethss_start(void)
390 struct mac_sl_cfg cfg
;
392 cfg
.max_rx_len
= MAX_SIZE_STREAM_BUFFER
;
393 cfg
.ctl
= GMACSL_ENABLE
| GMACSL_RX_ENABLE_EXT_CTL
;
395 for (i
= 0; i
< DEVICE_N_GMACSL_PORTS
; i
++) {
397 mac_sl_config(i
, &cfg
);
407 for (i
= 0; i
< DEVICE_N_GMACSL_PORTS
; i
++)
413 int32_t cpmac_drv_send(u32
*buffer
, int num_bytes
, int slave_port_num
)
415 if (num_bytes
< EMAC_MIN_ETHERNET_PKT_SIZE
)
416 num_bytes
= EMAC_MIN_ETHERNET_PKT_SIZE
;
418 return ksnav_send(&netcp_pktdma
, buffer
,
419 num_bytes
, (slave_port_num
) << 16);
422 /* Eth device open */
423 static int keystone2_eth_open(struct eth_device
*dev
, bd_t
*bis
)
425 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
426 struct phy_device
*phy_dev
= eth_priv
->phy_dev
;
428 debug("+ emac_open\n");
430 net_rx_buffs
.rx_flow
= eth_priv
->rx_flow
;
433 (eth_priv
->sgmii_link_type
== SGMII_LINK_MAC_PHY
) ? 1 : 0;
436 keystone2_mdio_reset(mdio_bus
);
438 #ifdef CONFIG_SOC_K2G
439 keystone_rgmii_config(phy_dev
);
441 keystone_sgmii_config(phy_dev
, eth_priv
->slave_port
- 1,
442 eth_priv
->sgmii_link_type
);
447 /* On chip switch configuration */
448 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE
);
450 /* TODO: add error handling code */
452 printf("ERROR: qm_init()\n");
455 if (ksnav_init(&netcp_pktdma
, &net_rx_buffs
)) {
457 printf("ERROR: netcp_init()\n");
462 * Streaming switch configuration. If not present this
463 * statement is defined to void in target.h.
464 * If present this is usually defined to a series of register writes
466 hw_config_streaming_switch();
469 keystone2_mdio_reset(mdio_bus
);
471 phy_startup(phy_dev
);
472 if (phy_dev
->link
== 0) {
473 ksnav_close(&netcp_pktdma
);
479 emac_gigabit_enable(dev
);
483 debug("- emac_open\n");
490 /* Eth device close */
491 void keystone2_eth_close(struct eth_device
*dev
)
493 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
494 struct phy_device
*phy_dev
= eth_priv
->phy_dev
;
496 debug("+ emac_close\n");
503 ksnav_close(&netcp_pktdma
);
505 phy_shutdown(phy_dev
);
509 debug("- emac_close\n");
513 * This function sends a single packet on the network and returns
514 * positive number (number of bytes transmitted) or negative for error
516 static int keystone2_eth_send_packet(struct eth_device
*dev
,
517 void *packet
, int length
)
520 struct eth_priv_t
*eth_priv
= (struct eth_priv_t
*)dev
->priv
;
521 struct phy_device
*phy_dev
= eth_priv
->phy_dev
;
523 genphy_update_link(phy_dev
);
524 if (phy_dev
->link
== 0)
527 if (cpmac_drv_send((u32
*)packet
, length
, eth_priv
->slave_port
) != 0)
534 * This function handles receipt of a packet from the network
536 static int keystone2_eth_rcv_packet(struct eth_device
*dev
)
542 hd
= ksnav_recv(&netcp_pktdma
, &pkt
, &pkt_size
);
546 net_process_received_packet((uchar
*)pkt
, pkt_size
);
548 ksnav_release_rxhd(&netcp_pktdma
, hd
);
553 #ifdef CONFIG_MCAST_TFTP
554 static int keystone2_eth_bcast_addr(struct eth_device
*dev
, u32 ip
, u8 set
)
561 * This function initializes the EMAC hardware.
563 int keystone2_emac_initialize(struct eth_priv_t
*eth_priv
)
566 struct eth_device
*dev
;
567 struct phy_device
*phy_dev
;
569 dev
= malloc(sizeof(struct eth_device
));
573 memset(dev
, 0, sizeof(struct eth_device
));
575 strcpy(dev
->name
, eth_priv
->int_name
);
576 dev
->priv
= eth_priv
;
578 keystone2_eth_read_mac_addr(dev
);
581 dev
->init
= keystone2_eth_open
;
582 dev
->halt
= keystone2_eth_close
;
583 dev
->send
= keystone2_eth_send_packet
;
584 dev
->recv
= keystone2_eth_rcv_packet
;
585 #ifdef CONFIG_MCAST_TFTP
586 dev
->mcast
= keystone2_eth_bcast_addr
;
591 /* Register MDIO bus if it's not registered yet */
593 mdio_bus
= mdio_alloc();
594 mdio_bus
->read
= keystone2_mdio_read
;
595 mdio_bus
->write
= keystone2_mdio_write
;
596 mdio_bus
->reset
= keystone2_mdio_reset
;
597 mdio_bus
->priv
= (void *)EMAC_MDIO_BASE_ADDR
;
598 sprintf(mdio_bus
->name
, "ethernet-mdio");
600 res
= mdio_register(mdio_bus
);
605 #ifndef CONFIG_SOC_K2G
606 keystone2_net_serdes_setup();
609 /* Create phy device and bind it with driver */
610 #ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
611 phy_dev
= phy_connect(mdio_bus
, eth_priv
->phy_addr
,
612 dev
, eth_priv
->phy_if
);
615 phy_dev
= phy_find_by_mask(mdio_bus
, 1 << eth_priv
->phy_addr
,
619 eth_priv
->phy_dev
= phy_dev
;
624 struct ks2_serdes ks2_serdes_sgmii_156p25mhz
= {
625 .clk
= SERDES_CLOCK_156P25M
,
626 .rate
= SERDES_RATE_5G
,
627 .rate_mode
= SERDES_QUARTER_RATE
,
628 .intf
= SERDES_PHY_SGMII
,
632 #ifndef CONFIG_SOC_K2G
633 static void keystone2_net_serdes_setup(void)
635 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE
,
636 &ks2_serdes_sgmii_156p25mhz
,
637 CONFIG_KSNET_SERDES_LANES_PER_SGMII
);
639 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
640 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE
,
641 &ks2_serdes_sgmii_156p25mhz
,
642 CONFIG_KSNET_SERDES_LANES_PER_SGMII
);
645 /* wait till setup */