2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 * Copyright (C) 2014 Marvell
6 * Marcin Wojtas <mw@semihalf.com>
9 * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
18 #include <dm/device-internal.h>
25 #include <linux/errno.h>
29 #include <asm/arch/cpu.h>
30 #include <asm/arch/soc.h>
31 #include <linux/compat.h>
32 #include <linux/mbus.h>
34 DECLARE_GLOBAL_DATA_PTR
;
36 /* Some linux -> U-Boot compatibility stuff */
37 #define netdev_err(dev, fmt, args...) \
39 #define netdev_warn(dev, fmt, args...) \
41 #define netdev_info(dev, fmt, args...) \
43 #define netdev_dbg(dev, fmt, args...) \
46 #define ETH_ALEN 6 /* Octets in one ethernet addr */
48 #define __verify_pcpu_ptr(ptr) \
50 const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
54 #define VERIFY_PERCPU_PTR(__p) \
56 __verify_pcpu_ptr(__p); \
57 (typeof(*(__p)) __kernel __force *)(__p); \
60 #define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
61 #define smp_processor_id() 0
62 #define num_present_cpus() 1
63 #define for_each_present_cpu(cpu) \
64 for ((cpu) = 0; (cpu) < 1; (cpu)++)
66 #define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
68 #define CONFIG_NR_CPUS 1
69 #define ETH_HLEN ETHER_HDR_SIZE /* Total octets in header */
71 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
72 #define WRAP (2 + ETH_HLEN + 4 + 32)
74 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
76 #define MVPP2_SMI_TIMEOUT 10000
78 /* RX Fifo Registers */
79 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
80 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
81 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
82 #define MVPP2_RX_FIFO_INIT_REG 0x64
84 /* RX DMA Top Registers */
85 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
86 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
87 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
88 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
89 #define MVPP2_POOL_BUF_SIZE_OFFSET 5
90 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
91 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
92 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
93 #define MVPP2_RXQ_POOL_SHORT_OFFS 20
94 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
95 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
96 #define MVPP2_RXQ_POOL_LONG_OFFS 24
97 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
98 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
99 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
100 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
101 #define MVPP2_RXQ_DISABLE_MASK BIT(31)
103 /* Parser Registers */
104 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
105 #define MVPP2_PRS_PORT_LU_MAX 0xf
106 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
107 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
108 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
109 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
110 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
111 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
112 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
113 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
114 #define MVPP2_PRS_TCAM_IDX_REG 0x1100
115 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
116 #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
117 #define MVPP2_PRS_SRAM_IDX_REG 0x1200
118 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
119 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
120 #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
122 /* Classifier Registers */
123 #define MVPP2_CLS_MODE_REG 0x1800
124 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
125 #define MVPP2_CLS_PORT_WAY_REG 0x1810
126 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
127 #define MVPP2_CLS_LKP_INDEX_REG 0x1814
128 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
129 #define MVPP2_CLS_LKP_TBL_REG 0x1818
130 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
131 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
132 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
133 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
134 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
135 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
136 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
137 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
138 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
139 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
140 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
141 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
143 /* Descriptor Manager Top Registers */
144 #define MVPP2_RXQ_NUM_REG 0x2040
145 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
146 #define MVPP22_DESC_ADDR_OFFS 8
147 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
148 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
149 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
150 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
151 #define MVPP2_RXQ_NUM_NEW_OFFSET 16
152 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
153 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
154 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
155 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
156 #define MVPP2_RXQ_THRESH_REG 0x204c
157 #define MVPP2_OCCUPIED_THRESH_OFFSET 0
158 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
159 #define MVPP2_RXQ_INDEX_REG 0x2050
160 #define MVPP2_TXQ_NUM_REG 0x2080
161 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
162 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
163 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
164 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
165 #define MVPP2_TXQ_THRESH_REG 0x2094
166 #define MVPP2_TRANSMITTED_THRESH_OFFSET 16
167 #define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
168 #define MVPP2_TXQ_INDEX_REG 0x2098
169 #define MVPP2_TXQ_PREF_BUF_REG 0x209c
170 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
171 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
172 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
173 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
174 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
175 #define MVPP2_TXQ_PENDING_REG 0x20a0
176 #define MVPP2_TXQ_PENDING_MASK 0x3fff
177 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
178 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
179 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
180 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
181 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
182 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
183 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
184 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
185 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
186 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
187 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
188 #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
189 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
190 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
191 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
192 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
193 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
195 /* MBUS bridge registers */
196 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
197 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
198 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
199 #define MVPP2_BASE_ADDR_ENABLE 0x4060
201 /* AXI Bridge Registers */
202 #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100
203 #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104
204 #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
205 #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114
206 #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118
207 #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c
208 #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
209 #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
210 #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150
211 #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154
212 #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160
213 #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164
215 /* Values for AXI Bridge registers */
216 #define MVPP22_AXI_ATTR_CACHE_OFFS 0
217 #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12
219 #define MVPP22_AXI_CODE_CACHE_OFFS 0
220 #define MVPP22_AXI_CODE_DOMAIN_OFFS 4
222 #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3
223 #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
224 #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
226 #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2
227 #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3
229 /* Interrupt Cause and Mask registers */
230 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
231 #define MVPP21_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
233 #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
234 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
235 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
236 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
238 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
239 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
241 #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
242 #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
243 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
244 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8
246 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
247 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
248 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
249 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
250 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
251 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
252 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
253 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
254 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
255 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
256 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
257 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
258 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
259 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
260 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
261 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
262 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
263 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
265 /* Buffer Manager registers */
266 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
267 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
268 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
269 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
270 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
271 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
272 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
273 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
274 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
275 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
276 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
277 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
278 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
279 #define MVPP2_BM_START_MASK BIT(0)
280 #define MVPP2_BM_STOP_MASK BIT(1)
281 #define MVPP2_BM_STATE_MASK BIT(4)
282 #define MVPP2_BM_LOW_THRESH_OFFS 8
283 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
284 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
285 MVPP2_BM_LOW_THRESH_OFFS)
286 #define MVPP2_BM_HIGH_THRESH_OFFS 16
287 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
288 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
289 MVPP2_BM_HIGH_THRESH_OFFS)
290 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
291 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
292 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
293 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
294 #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
295 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
296 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
297 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
298 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
299 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
300 #define MVPP2_BM_ADDR_HIGH_ALLOC 0x6444
301 #define MVPP2_BM_ADDR_HIGH_PHYS_MASK 0xff
302 #define MVPP2_BM_ADDR_HIGH_VIRT_MASK 0xff00
303 #define MVPP2_BM_ADDR_HIGH_VIRT_SHIFT 8
304 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
305 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
306 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
307 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
308 #define MVPP2_BM_VIRT_RLS_REG 0x64c0
309 #define MVPP21_BM_MC_RLS_REG 0x64c4
310 #define MVPP2_BM_MC_ID_MASK 0xfff
311 #define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
312 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
313 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
314 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
315 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
316 #define MVPP22_BM_MC_RLS_REG 0x64d4
318 /* TX Scheduler registers */
319 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
320 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
321 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
322 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
323 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
324 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
325 #define MVPP2_TXP_SCHED_MTU_REG 0x801c
326 #define MVPP2_TXP_MTU_MAX 0x7FFFF
327 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
328 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
329 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
330 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
331 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
332 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
333 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
334 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
335 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
336 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
337 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
338 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
339 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
340 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
342 /* TX general registers */
343 #define MVPP2_TX_SNOOP_REG 0x8800
344 #define MVPP2_TX_PORT_FLUSH_REG 0x8810
345 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
348 #define MVPP2_SRC_ADDR_MIDDLE 0x24
349 #define MVPP2_SRC_ADDR_HIGH 0x28
350 #define MVPP2_PHY_AN_CFG0_REG 0x34
351 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
352 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
353 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
355 /* Per-port registers */
356 #define MVPP2_GMAC_CTRL_0_REG 0x0
357 #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
358 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
359 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
360 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
361 #define MVPP2_GMAC_CTRL_1_REG 0x4
362 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
363 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
364 #define MVPP2_GMAC_PCS_LB_EN_BIT 6
365 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
366 #define MVPP2_GMAC_SA_LOW_OFFS 7
367 #define MVPP2_GMAC_CTRL_2_REG 0x8
368 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
369 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
370 #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
371 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
372 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
373 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
374 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
375 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
376 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
377 #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
378 #define MVPP2_GMAC_FC_ADV_EN BIT(9)
379 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
380 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
381 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
382 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
383 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
384 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
385 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
387 #define MVPP22_SMI_MISC_CFG_REG 0x1204
388 #define MVPP22_SMI_POLLING_EN BIT(10)
390 #define MVPP22_PORT_BASE 0x30e00
391 #define MVPP22_PORT_OFFSET 0x1000
393 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
395 /* Descriptor ring Macros */
396 #define MVPP2_QUEUE_NEXT_DESC(q, index) \
397 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
399 /* SMI: 0xc0054 -> offset 0x54 to lms_base */
400 #define MVPP21_SMI 0x0054
401 /* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
402 #define MVPP22_SMI 0x1200
403 #define MVPP2_PHY_REG_MASK 0x1f
404 /* SMI register fields */
405 #define MVPP2_SMI_DATA_OFFS 0 /* Data */
406 #define MVPP2_SMI_DATA_MASK (0xffff << MVPP2_SMI_DATA_OFFS)
407 #define MVPP2_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
408 #define MVPP2_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
409 #define MVPP2_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
410 #define MVPP2_SMI_OPCODE_READ (1 << MVPP2_SMI_OPCODE_OFFS)
411 #define MVPP2_SMI_READ_VALID (1 << 27) /* Read Valid */
412 #define MVPP2_SMI_BUSY (1 << 28) /* Busy */
414 #define MVPP2_PHY_ADDR_MASK 0x1f
415 #define MVPP2_PHY_REG_MASK 0x1f
417 /* Various constants */
420 #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
421 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
422 #define MVPP2_RX_COAL_PKTS 32
423 #define MVPP2_RX_COAL_USEC 100
425 /* The two bytes Marvell header. Either contains a special value used
426 * by Marvell switches when a specific hardware mode is enabled (not
427 * supported by this driver) or is filled automatically by zeroes on
428 * the RX side. Those two bytes being at the front of the Ethernet
429 * header, they allow to have the IP header aligned on a 4 bytes
430 * boundary automatically: the hardware skips those two bytes on its
433 #define MVPP2_MH_SIZE 2
434 #define MVPP2_ETH_TYPE_LEN 2
435 #define MVPP2_PPPOE_HDR_SIZE 8
436 #define MVPP2_VLAN_TAG_LEN 4
438 /* Lbtd 802.3 type */
439 #define MVPP2_IP_LBDT_TYPE 0xfffa
441 #define MVPP2_CPU_D_CACHE_LINE_SIZE 32
442 #define MVPP2_TX_CSUM_MAX_SIZE 9800
444 /* Timeout constants */
445 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
446 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
448 #define MVPP2_TX_MTU_MAX 0x7ffff
450 /* Maximum number of T-CONTs of PON port */
451 #define MVPP2_MAX_TCONT 16
453 /* Maximum number of supported ports */
454 #define MVPP2_MAX_PORTS 4
456 /* Maximum number of TXQs used by single port */
457 #define MVPP2_MAX_TXQ 8
459 /* Default number of TXQs in use */
460 #define MVPP2_DEFAULT_TXQ 1
462 /* Dfault number of RXQs in use */
463 #define MVPP2_DEFAULT_RXQ 1
464 #define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
466 /* Max number of Rx descriptors */
467 #define MVPP2_MAX_RXD 16
469 /* Max number of Tx descriptors */
470 #define MVPP2_MAX_TXD 16
472 /* Amount of Tx descriptors that can be reserved at once by CPU */
473 #define MVPP2_CPU_DESC_CHUNK 64
475 /* Max number of Tx descriptors in each aggregated queue */
476 #define MVPP2_AGGR_TXQ_SIZE 256
478 /* Descriptor aligned size */
479 #define MVPP2_DESC_ALIGNED_SIZE 32
481 /* Descriptor alignment mask */
482 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
484 /* RX FIFO constants */
485 #define MVPP21_RX_FIFO_PORT_DATA_SIZE 0x2000
486 #define MVPP21_RX_FIFO_PORT_ATTR_SIZE 0x80
487 #define MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE 0x8000
488 #define MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE 0x2000
489 #define MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE 0x1000
490 #define MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE 0x200
491 #define MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE 0x80
492 #define MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE 0x40
493 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
495 /* TX general registers */
496 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2))
497 #define MVPP22_TX_FIFO_SIZE_MASK 0xf
499 /* TX FIFO constants */
500 #define MVPP2_TX_FIFO_DATA_SIZE_10KB 0xa
501 #define MVPP2_TX_FIFO_DATA_SIZE_3KB 0x3
503 /* RX buffer constants */
504 #define MVPP2_SKB_SHINFO_SIZE \
507 #define MVPP2_RX_PKT_SIZE(mtu) \
508 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
509 ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
511 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
512 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
513 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
514 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
516 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
518 /* IPv6 max L3 address size */
519 #define MVPP2_MAX_L3_ADDR_SIZE 16
522 #define MVPP2_F_LOOPBACK BIT(0)
524 /* Marvell tag types */
525 enum mvpp2_tag_type
{
526 MVPP2_TAG_TYPE_NONE
= 0,
527 MVPP2_TAG_TYPE_MH
= 1,
528 MVPP2_TAG_TYPE_DSA
= 2,
529 MVPP2_TAG_TYPE_EDSA
= 3,
530 MVPP2_TAG_TYPE_VLAN
= 4,
531 MVPP2_TAG_TYPE_LAST
= 5
534 /* Parser constants */
535 #define MVPP2_PRS_TCAM_SRAM_SIZE 256
536 #define MVPP2_PRS_TCAM_WORDS 6
537 #define MVPP2_PRS_SRAM_WORDS 4
538 #define MVPP2_PRS_FLOW_ID_SIZE 64
539 #define MVPP2_PRS_FLOW_ID_MASK 0x3f
540 #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
541 #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
542 #define MVPP2_PRS_IPV4_HEAD 0x40
543 #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
544 #define MVPP2_PRS_IPV4_MC 0xe0
545 #define MVPP2_PRS_IPV4_MC_MASK 0xf0
546 #define MVPP2_PRS_IPV4_BC_MASK 0xff
547 #define MVPP2_PRS_IPV4_IHL 0x5
548 #define MVPP2_PRS_IPV4_IHL_MASK 0xf
549 #define MVPP2_PRS_IPV6_MC 0xff
550 #define MVPP2_PRS_IPV6_MC_MASK 0xff
551 #define MVPP2_PRS_IPV6_HOP_MASK 0xff
552 #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
553 #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
554 #define MVPP2_PRS_DBL_VLANS_MAX 100
557 * - lookup ID - 4 bits
559 * - additional information - 1 byte
560 * - header data - 8 bytes
561 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
563 #define MVPP2_PRS_AI_BITS 8
564 #define MVPP2_PRS_PORT_MASK 0xff
565 #define MVPP2_PRS_LU_MASK 0xf
566 #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
567 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
568 #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
569 (((offs) * 2) - ((offs) % 2) + 2)
570 #define MVPP2_PRS_TCAM_AI_BYTE 16
571 #define MVPP2_PRS_TCAM_PORT_BYTE 17
572 #define MVPP2_PRS_TCAM_LU_BYTE 20
573 #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
574 #define MVPP2_PRS_TCAM_INV_WORD 5
575 /* Tcam entries ID */
576 #define MVPP2_PE_DROP_ALL 0
577 #define MVPP2_PE_FIRST_FREE_TID 1
578 #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
579 #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
580 #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
581 #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
582 #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
583 #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
584 #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
585 #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
586 #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
587 #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
588 #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
589 #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
590 #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
591 #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
592 #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
593 #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
594 #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
595 #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
596 #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
597 #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
598 #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
599 #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
600 #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
601 #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
602 #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
605 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
607 #define MVPP2_PRS_SRAM_RI_OFFS 0
608 #define MVPP2_PRS_SRAM_RI_WORD 0
609 #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
610 #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
611 #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
612 #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
613 #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
614 #define MVPP2_PRS_SRAM_UDF_OFFS 73
615 #define MVPP2_PRS_SRAM_UDF_BITS 8
616 #define MVPP2_PRS_SRAM_UDF_MASK 0xff
617 #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
618 #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
619 #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
620 #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
621 #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
622 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
623 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
624 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
625 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
626 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
627 #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
628 #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
629 #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
630 #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
631 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
632 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
633 #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
634 #define MVPP2_PRS_SRAM_AI_OFFS 90
635 #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
636 #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
637 #define MVPP2_PRS_SRAM_AI_MASK 0xff
638 #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
639 #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
640 #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
641 #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
643 /* Sram result info bits assignment */
644 #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
645 #define MVPP2_PRS_RI_DSA_MASK 0x2
646 #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
647 #define MVPP2_PRS_RI_VLAN_NONE 0x0
648 #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
649 #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
650 #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
651 #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
652 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
653 #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
654 #define MVPP2_PRS_RI_L2_UCAST 0x0
655 #define MVPP2_PRS_RI_L2_MCAST BIT(9)
656 #define MVPP2_PRS_RI_L2_BCAST BIT(10)
657 #define MVPP2_PRS_RI_PPPOE_MASK 0x800
658 #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
659 #define MVPP2_PRS_RI_L3_UN 0x0
660 #define MVPP2_PRS_RI_L3_IP4 BIT(12)
661 #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
662 #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
663 #define MVPP2_PRS_RI_L3_IP6 BIT(14)
664 #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
665 #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
666 #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
667 #define MVPP2_PRS_RI_L3_UCAST 0x0
668 #define MVPP2_PRS_RI_L3_MCAST BIT(15)
669 #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
670 #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
671 #define MVPP2_PRS_RI_UDF3_MASK 0x300000
672 #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
673 #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
674 #define MVPP2_PRS_RI_L4_TCP BIT(22)
675 #define MVPP2_PRS_RI_L4_UDP BIT(23)
676 #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
677 #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
678 #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
679 #define MVPP2_PRS_RI_DROP_MASK 0x80000000
681 /* Sram additional info bits assignment */
682 #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
683 #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
684 #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
685 #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
686 #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
687 #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
688 #define MVPP2_PRS_SINGLE_VLAN_AI 0
689 #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
692 #define MVPP2_PRS_TAGGED true
693 #define MVPP2_PRS_UNTAGGED false
694 #define MVPP2_PRS_EDSA true
695 #define MVPP2_PRS_DSA false
697 /* MAC entries, shadow udf */
699 MVPP2_PRS_UDF_MAC_DEF
,
700 MVPP2_PRS_UDF_MAC_RANGE
,
701 MVPP2_PRS_UDF_L2_DEF
,
702 MVPP2_PRS_UDF_L2_DEF_COPY
,
703 MVPP2_PRS_UDF_L2_USER
,
707 enum mvpp2_prs_lookup
{
721 enum mvpp2_prs_l3_cast
{
722 MVPP2_PRS_L3_UNI_CAST
,
723 MVPP2_PRS_L3_MULTI_CAST
,
724 MVPP2_PRS_L3_BROAD_CAST
727 /* Classifier constants */
728 #define MVPP2_CLS_FLOWS_TBL_SIZE 512
729 #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
730 #define MVPP2_CLS_LKP_TBL_SIZE 64
733 #define MVPP2_BM_POOLS_NUM 1
734 #define MVPP2_BM_LONG_BUF_NUM 16
735 #define MVPP2_BM_SHORT_BUF_NUM 16
736 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
737 #define MVPP2_BM_POOL_PTR_ALIGN 128
738 #define MVPP2_BM_SWF_LONG_POOL(port) 0
740 /* BM cookie (32 bits) definition */
741 #define MVPP2_BM_COOKIE_POOL_OFFS 8
742 #define MVPP2_BM_COOKIE_CPU_OFFS 24
744 /* BM short pool packet size
745 * These value assure that for SWF the total number
746 * of bytes allocated for each buffer will be 512
748 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
758 /* Shared Packet Processor resources */
760 /* Shared registers' base addresses */
762 void __iomem
*lms_base
;
763 void __iomem
*iface_base
;
764 void __iomem
*mdio_base
;
766 /* List of pointers to port structures */
767 struct mvpp2_port
**port_list
;
769 /* Aggregated TXQs */
770 struct mvpp2_tx_queue
*aggr_txqs
;
773 struct mvpp2_bm_pool
*bm_pools
;
775 /* PRS shadow table */
776 struct mvpp2_prs_shadow
*prs_shadow
;
777 /* PRS auxiliary table for double vlan entries control */
778 bool *prs_double_vlans
;
784 enum { MVPP21
, MVPP22
} hw_version
;
786 /* Maximum number of RXQs per port */
787 unsigned int max_port_rxqs
;
794 struct mvpp2_pcpu_stats
{
804 /* Index of the port from the "group of ports" complex point
813 /* Per-port registers' base address */
816 struct mvpp2_rx_queue
**rxqs
;
817 struct mvpp2_tx_queue
**txqs
;
821 u32 pending_cause_rx
;
823 /* Per-CPU port control */
824 struct mvpp2_port_pcpu __percpu
*pcpu
;
831 struct mvpp2_pcpu_stats __percpu
*stats
;
833 struct phy_device
*phy_dev
;
834 phy_interface_t phy_interface
;
842 struct mvpp2_bm_pool
*pool_long
;
843 struct mvpp2_bm_pool
*pool_short
;
845 /* Index of first port's physical RXQ */
848 u8 dev_addr
[ETH_ALEN
];
851 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
852 * layout of the transmit and reception DMA descriptors, and their
853 * layout is therefore defined by the hardware design
856 #define MVPP2_TXD_L3_OFF_SHIFT 0
857 #define MVPP2_TXD_IP_HLEN_SHIFT 8
858 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
859 #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
860 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
861 #define MVPP2_TXD_PADDING_DISABLE BIT(23)
862 #define MVPP2_TXD_L4_UDP BIT(24)
863 #define MVPP2_TXD_L3_IP6 BIT(26)
864 #define MVPP2_TXD_L_DESC BIT(28)
865 #define MVPP2_TXD_F_DESC BIT(29)
867 #define MVPP2_RXD_ERR_SUMMARY BIT(15)
868 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
869 #define MVPP2_RXD_ERR_CRC 0x0
870 #define MVPP2_RXD_ERR_OVERRUN BIT(13)
871 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
872 #define MVPP2_RXD_BM_POOL_ID_OFFS 16
873 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
874 #define MVPP2_RXD_HWF_SYNC BIT(21)
875 #define MVPP2_RXD_L4_CSUM_OK BIT(22)
876 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
877 #define MVPP2_RXD_L4_TCP BIT(25)
878 #define MVPP2_RXD_L4_UDP BIT(26)
879 #define MVPP2_RXD_L3_IP4 BIT(28)
880 #define MVPP2_RXD_L3_IP6 BIT(30)
881 #define MVPP2_RXD_BUF_HDR BIT(31)
883 /* HW TX descriptor for PPv2.1 */
884 struct mvpp21_tx_desc
{
885 u32 command
; /* Options used by HW for packet transmitting.*/
886 u8 packet_offset
; /* the offset from the buffer beginning */
887 u8 phys_txq
; /* destination queue ID */
888 u16 data_size
; /* data size of transmitted packet in bytes */
889 u32 buf_dma_addr
; /* physical addr of transmitted buffer */
890 u32 buf_cookie
; /* cookie for access to TX buffer in tx path */
891 u32 reserved1
[3]; /* hw_cmd (for future use, BM, PON, PNC) */
892 u32 reserved2
; /* reserved (for future use) */
895 /* HW RX descriptor for PPv2.1 */
896 struct mvpp21_rx_desc
{
897 u32 status
; /* info about received packet */
898 u16 reserved1
; /* parser_info (for future use, PnC) */
899 u16 data_size
; /* size of received packet in bytes */
900 u32 buf_dma_addr
; /* physical address of the buffer */
901 u32 buf_cookie
; /* cookie for access to RX buffer in rx path */
902 u16 reserved2
; /* gem_port_id (for future use, PON) */
903 u16 reserved3
; /* csum_l4 (for future use, PnC) */
904 u8 reserved4
; /* bm_qset (for future use, BM) */
906 u16 reserved6
; /* classify_info (for future use, PnC) */
907 u32 reserved7
; /* flow_id (for future use, PnC) */
911 /* HW TX descriptor for PPv2.2 */
912 struct mvpp22_tx_desc
{
918 u64 buf_dma_addr_ptp
;
922 /* HW RX descriptor for PPv2.2 */
923 struct mvpp22_rx_desc
{
929 u64 buf_dma_addr_key_hash
;
933 /* Opaque type used by the driver to manipulate the HW TX and RX
936 struct mvpp2_tx_desc
{
938 struct mvpp21_tx_desc pp21
;
939 struct mvpp22_tx_desc pp22
;
943 struct mvpp2_rx_desc
{
945 struct mvpp21_rx_desc pp21
;
946 struct mvpp22_rx_desc pp22
;
950 /* Per-CPU Tx queue control */
951 struct mvpp2_txq_pcpu
{
954 /* Number of Tx DMA descriptors in the descriptor ring */
957 /* Number of currently used Tx DMA descriptor in the
962 /* Number of Tx DMA descriptors reserved for each CPU */
965 /* Index of last TX DMA descriptor that was inserted */
968 /* Index of the TX DMA descriptor to be cleaned up */
972 struct mvpp2_tx_queue
{
973 /* Physical number of this Tx queue */
976 /* Logical number of this Tx queue */
979 /* Number of Tx DMA descriptors in the descriptor ring */
982 /* Number of currently used Tx DMA descriptor in the descriptor ring */
985 /* Per-CPU control of physical Tx queues */
986 struct mvpp2_txq_pcpu __percpu
*pcpu
;
990 /* Virtual address of thex Tx DMA descriptors array */
991 struct mvpp2_tx_desc
*descs
;
993 /* DMA address of the Tx DMA descriptors array */
994 dma_addr_t descs_dma
;
996 /* Index of the last Tx DMA descriptor */
999 /* Index of the next Tx DMA descriptor to process */
1000 int next_desc_to_proc
;
1003 struct mvpp2_rx_queue
{
1004 /* RX queue number, in the range 0-31 for physical RXQs */
1007 /* Num of rx descriptors in the rx descriptor ring */
1013 /* Virtual address of the RX DMA descriptors array */
1014 struct mvpp2_rx_desc
*descs
;
1016 /* DMA address of the RX DMA descriptors array */
1017 dma_addr_t descs_dma
;
1019 /* Index of the last RX DMA descriptor */
1022 /* Index of the next RX DMA descriptor to process */
1023 int next_desc_to_proc
;
1025 /* ID of port to which physical RXQ is mapped */
1028 /* Port's logic RXQ number to which physical RXQ is mapped */
1032 union mvpp2_prs_tcam_entry
{
1033 u32 word
[MVPP2_PRS_TCAM_WORDS
];
1034 u8 byte
[MVPP2_PRS_TCAM_WORDS
* 4];
1037 union mvpp2_prs_sram_entry
{
1038 u32 word
[MVPP2_PRS_SRAM_WORDS
];
1039 u8 byte
[MVPP2_PRS_SRAM_WORDS
* 4];
1042 struct mvpp2_prs_entry
{
1044 union mvpp2_prs_tcam_entry tcam
;
1045 union mvpp2_prs_sram_entry sram
;
1048 struct mvpp2_prs_shadow
{
1055 /* User defined offset */
1063 struct mvpp2_cls_flow_entry
{
1065 u32 data
[MVPP2_CLS_FLOWS_TBL_DATA_WORDS
];
1068 struct mvpp2_cls_lookup_entry
{
1074 struct mvpp2_bm_pool
{
1075 /* Pool number in the range 0-7 */
1077 enum mvpp2_bm_type type
;
1079 /* Buffer Pointers Pool External (BPPE) size */
1081 /* Number of buffers for this pool */
1083 /* Pool buffer size */
1088 /* BPPE virtual base address */
1089 unsigned long *virt_addr
;
1090 /* BPPE DMA base address */
1091 dma_addr_t dma_addr
;
1093 /* Ports using BM pool */
1096 /* Occupied buffers indicator */
1100 /* Static declaractions */
1102 /* Number of RXQs used by single port */
1103 static int rxq_number
= MVPP2_DEFAULT_RXQ
;
1104 /* Number of TXQs used by single port */
1105 static int txq_number
= MVPP2_DEFAULT_TXQ
;
1109 #define MVPP2_DRIVER_NAME "mvpp2"
1110 #define MVPP2_DRIVER_VERSION "1.0"
1113 * U-Boot internal data, mostly uncached buffers for descriptors and data
1115 struct buffer_location
{
1116 struct mvpp2_tx_desc
*aggr_tx_descs
;
1117 struct mvpp2_tx_desc
*tx_descs
;
1118 struct mvpp2_rx_desc
*rx_descs
;
1119 unsigned long *bm_pool
[MVPP2_BM_POOLS_NUM
];
1120 unsigned long *rx_buffer
[MVPP2_BM_LONG_BUF_NUM
];
1125 * All 4 interfaces use the same global buffer, since only one interface
1126 * can be enabled at once
1128 static struct buffer_location buffer_loc
;
1131 * Page table entries are set to 1MB, or multiples of 1MB
1132 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
1134 #define BD_SPACE (1 << 20)
1136 /* Utility/helper methods */
1138 static void mvpp2_write(struct mvpp2
*priv
, u32 offset
, u32 data
)
1140 writel(data
, priv
->base
+ offset
);
1143 static u32
mvpp2_read(struct mvpp2
*priv
, u32 offset
)
1145 return readl(priv
->base
+ offset
);
1148 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port
*port
,
1149 struct mvpp2_tx_desc
*tx_desc
,
1150 dma_addr_t dma_addr
)
1152 if (port
->priv
->hw_version
== MVPP21
) {
1153 tx_desc
->pp21
.buf_dma_addr
= dma_addr
;
1155 u64 val
= (u64
)dma_addr
;
1157 tx_desc
->pp22
.buf_dma_addr_ptp
&= ~GENMASK_ULL(40, 0);
1158 tx_desc
->pp22
.buf_dma_addr_ptp
|= val
;
1162 static void mvpp2_txdesc_size_set(struct mvpp2_port
*port
,
1163 struct mvpp2_tx_desc
*tx_desc
,
1166 if (port
->priv
->hw_version
== MVPP21
)
1167 tx_desc
->pp21
.data_size
= size
;
1169 tx_desc
->pp22
.data_size
= size
;
1172 static void mvpp2_txdesc_txq_set(struct mvpp2_port
*port
,
1173 struct mvpp2_tx_desc
*tx_desc
,
1176 if (port
->priv
->hw_version
== MVPP21
)
1177 tx_desc
->pp21
.phys_txq
= txq
;
1179 tx_desc
->pp22
.phys_txq
= txq
;
1182 static void mvpp2_txdesc_cmd_set(struct mvpp2_port
*port
,
1183 struct mvpp2_tx_desc
*tx_desc
,
1184 unsigned int command
)
1186 if (port
->priv
->hw_version
== MVPP21
)
1187 tx_desc
->pp21
.command
= command
;
1189 tx_desc
->pp22
.command
= command
;
1192 static void mvpp2_txdesc_offset_set(struct mvpp2_port
*port
,
1193 struct mvpp2_tx_desc
*tx_desc
,
1194 unsigned int offset
)
1196 if (port
->priv
->hw_version
== MVPP21
)
1197 tx_desc
->pp21
.packet_offset
= offset
;
1199 tx_desc
->pp22
.packet_offset
= offset
;
1202 static dma_addr_t
mvpp2_rxdesc_dma_addr_get(struct mvpp2_port
*port
,
1203 struct mvpp2_rx_desc
*rx_desc
)
1205 if (port
->priv
->hw_version
== MVPP21
)
1206 return rx_desc
->pp21
.buf_dma_addr
;
1208 return rx_desc
->pp22
.buf_dma_addr_key_hash
& GENMASK_ULL(40, 0);
1211 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port
*port
,
1212 struct mvpp2_rx_desc
*rx_desc
)
1214 if (port
->priv
->hw_version
== MVPP21
)
1215 return rx_desc
->pp21
.buf_cookie
;
1217 return rx_desc
->pp22
.buf_cookie_misc
& GENMASK_ULL(40, 0);
1220 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port
*port
,
1221 struct mvpp2_rx_desc
*rx_desc
)
1223 if (port
->priv
->hw_version
== MVPP21
)
1224 return rx_desc
->pp21
.data_size
;
1226 return rx_desc
->pp22
.data_size
;
1229 static u32
mvpp2_rxdesc_status_get(struct mvpp2_port
*port
,
1230 struct mvpp2_rx_desc
*rx_desc
)
1232 if (port
->priv
->hw_version
== MVPP21
)
1233 return rx_desc
->pp21
.status
;
1235 return rx_desc
->pp22
.status
;
1238 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu
*txq_pcpu
)
1240 txq_pcpu
->txq_get_index
++;
1241 if (txq_pcpu
->txq_get_index
== txq_pcpu
->size
)
1242 txq_pcpu
->txq_get_index
= 0;
1245 /* Get number of physical egress port */
1246 static inline int mvpp2_egress_port(struct mvpp2_port
*port
)
1248 return MVPP2_MAX_TCONT
+ port
->id
;
1251 /* Get number of physical TXQ */
1252 static inline int mvpp2_txq_phys(int port
, int txq
)
1254 return (MVPP2_MAX_TCONT
+ port
) * MVPP2_MAX_TXQ
+ txq
;
1257 /* Parser configuration routines */
1259 /* Update parser tcam and sram hw entries */
1260 static int mvpp2_prs_hw_write(struct mvpp2
*priv
, struct mvpp2_prs_entry
*pe
)
1264 if (pe
->index
> MVPP2_PRS_TCAM_SRAM_SIZE
- 1)
1267 /* Clear entry invalidation bit */
1268 pe
->tcam
.word
[MVPP2_PRS_TCAM_INV_WORD
] &= ~MVPP2_PRS_TCAM_INV_MASK
;
1270 /* Write tcam index - indirect access */
1271 mvpp2_write(priv
, MVPP2_PRS_TCAM_IDX_REG
, pe
->index
);
1272 for (i
= 0; i
< MVPP2_PRS_TCAM_WORDS
; i
++)
1273 mvpp2_write(priv
, MVPP2_PRS_TCAM_DATA_REG(i
), pe
->tcam
.word
[i
]);
1275 /* Write sram index - indirect access */
1276 mvpp2_write(priv
, MVPP2_PRS_SRAM_IDX_REG
, pe
->index
);
1277 for (i
= 0; i
< MVPP2_PRS_SRAM_WORDS
; i
++)
1278 mvpp2_write(priv
, MVPP2_PRS_SRAM_DATA_REG(i
), pe
->sram
.word
[i
]);
1283 /* Read tcam entry from hw */
1284 static int mvpp2_prs_hw_read(struct mvpp2
*priv
, struct mvpp2_prs_entry
*pe
)
1288 if (pe
->index
> MVPP2_PRS_TCAM_SRAM_SIZE
- 1)
1291 /* Write tcam index - indirect access */
1292 mvpp2_write(priv
, MVPP2_PRS_TCAM_IDX_REG
, pe
->index
);
1294 pe
->tcam
.word
[MVPP2_PRS_TCAM_INV_WORD
] = mvpp2_read(priv
,
1295 MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD
));
1296 if (pe
->tcam
.word
[MVPP2_PRS_TCAM_INV_WORD
] & MVPP2_PRS_TCAM_INV_MASK
)
1297 return MVPP2_PRS_TCAM_ENTRY_INVALID
;
1299 for (i
= 0; i
< MVPP2_PRS_TCAM_WORDS
; i
++)
1300 pe
->tcam
.word
[i
] = mvpp2_read(priv
, MVPP2_PRS_TCAM_DATA_REG(i
));
1302 /* Write sram index - indirect access */
1303 mvpp2_write(priv
, MVPP2_PRS_SRAM_IDX_REG
, pe
->index
);
1304 for (i
= 0; i
< MVPP2_PRS_SRAM_WORDS
; i
++)
1305 pe
->sram
.word
[i
] = mvpp2_read(priv
, MVPP2_PRS_SRAM_DATA_REG(i
));
1310 /* Invalidate tcam hw entry */
1311 static void mvpp2_prs_hw_inv(struct mvpp2
*priv
, int index
)
1313 /* Write index - indirect access */
1314 mvpp2_write(priv
, MVPP2_PRS_TCAM_IDX_REG
, index
);
1315 mvpp2_write(priv
, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD
),
1316 MVPP2_PRS_TCAM_INV_MASK
);
1319 /* Enable shadow table entry and set its lookup ID */
1320 static void mvpp2_prs_shadow_set(struct mvpp2
*priv
, int index
, int lu
)
1322 priv
->prs_shadow
[index
].valid
= true;
1323 priv
->prs_shadow
[index
].lu
= lu
;
1326 /* Update ri fields in shadow table entry */
1327 static void mvpp2_prs_shadow_ri_set(struct mvpp2
*priv
, int index
,
1328 unsigned int ri
, unsigned int ri_mask
)
1330 priv
->prs_shadow
[index
].ri_mask
= ri_mask
;
1331 priv
->prs_shadow
[index
].ri
= ri
;
1334 /* Update lookup field in tcam sw entry */
1335 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry
*pe
, unsigned int lu
)
1337 int enable_off
= MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE
);
1339 pe
->tcam
.byte
[MVPP2_PRS_TCAM_LU_BYTE
] = lu
;
1340 pe
->tcam
.byte
[enable_off
] = MVPP2_PRS_LU_MASK
;
1343 /* Update mask for single port in tcam sw entry */
1344 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry
*pe
,
1345 unsigned int port
, bool add
)
1347 int enable_off
= MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE
);
1350 pe
->tcam
.byte
[enable_off
] &= ~(1 << port
);
1352 pe
->tcam
.byte
[enable_off
] |= 1 << port
;
1355 /* Update port map in tcam sw entry */
1356 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry
*pe
,
1359 unsigned char port_mask
= MVPP2_PRS_PORT_MASK
;
1360 int enable_off
= MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE
);
1362 pe
->tcam
.byte
[MVPP2_PRS_TCAM_PORT_BYTE
] = 0;
1363 pe
->tcam
.byte
[enable_off
] &= ~port_mask
;
1364 pe
->tcam
.byte
[enable_off
] |= ~ports
& MVPP2_PRS_PORT_MASK
;
1367 /* Obtain port map from tcam sw entry */
1368 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry
*pe
)
1370 int enable_off
= MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE
);
1372 return ~(pe
->tcam
.byte
[enable_off
]) & MVPP2_PRS_PORT_MASK
;
1375 /* Set byte of data and its enable bits in tcam sw entry */
1376 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry
*pe
,
1377 unsigned int offs
, unsigned char byte
,
1378 unsigned char enable
)
1380 pe
->tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE(offs
)] = byte
;
1381 pe
->tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs
)] = enable
;
1384 /* Get byte of data and its enable bits from tcam sw entry */
1385 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry
*pe
,
1386 unsigned int offs
, unsigned char *byte
,
1387 unsigned char *enable
)
1389 *byte
= pe
->tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE(offs
)];
1390 *enable
= pe
->tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs
)];
1393 /* Set ethertype in tcam sw entry */
1394 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry
*pe
, int offset
,
1395 unsigned short ethertype
)
1397 mvpp2_prs_tcam_data_byte_set(pe
, offset
+ 0, ethertype
>> 8, 0xff);
1398 mvpp2_prs_tcam_data_byte_set(pe
, offset
+ 1, ethertype
& 0xff, 0xff);
1401 /* Set bits in sram sw entry */
1402 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry
*pe
, int bit_num
,
1405 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(bit_num
)] |= (val
<< (bit_num
% 8));
1408 /* Clear bits in sram sw entry */
1409 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry
*pe
, int bit_num
,
1412 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(bit_num
)] &= ~(val
<< (bit_num
% 8));
1415 /* Update ri bits in sram sw entry */
1416 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry
*pe
,
1417 unsigned int bits
, unsigned int mask
)
1421 for (i
= 0; i
< MVPP2_PRS_SRAM_RI_CTRL_BITS
; i
++) {
1422 int ri_off
= MVPP2_PRS_SRAM_RI_OFFS
;
1424 if (!(mask
& BIT(i
)))
1428 mvpp2_prs_sram_bits_set(pe
, ri_off
+ i
, 1);
1430 mvpp2_prs_sram_bits_clear(pe
, ri_off
+ i
, 1);
1432 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_RI_CTRL_OFFS
+ i
, 1);
1436 /* Update ai bits in sram sw entry */
1437 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry
*pe
,
1438 unsigned int bits
, unsigned int mask
)
1441 int ai_off
= MVPP2_PRS_SRAM_AI_OFFS
;
1443 for (i
= 0; i
< MVPP2_PRS_SRAM_AI_CTRL_BITS
; i
++) {
1445 if (!(mask
& BIT(i
)))
1449 mvpp2_prs_sram_bits_set(pe
, ai_off
+ i
, 1);
1451 mvpp2_prs_sram_bits_clear(pe
, ai_off
+ i
, 1);
1453 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_AI_CTRL_OFFS
+ i
, 1);
1457 /* Read ai bits from sram sw entry */
1458 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry
*pe
)
1461 int ai_off
= MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS
);
1462 int ai_en_off
= ai_off
+ 1;
1463 int ai_shift
= MVPP2_PRS_SRAM_AI_OFFS
% 8;
1465 bits
= (pe
->sram
.byte
[ai_off
] >> ai_shift
) |
1466 (pe
->sram
.byte
[ai_en_off
] << (8 - ai_shift
));
1471 /* In sram sw entry set lookup ID field of the tcam key to be used in the next
1474 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry
*pe
,
1477 int sram_next_off
= MVPP2_PRS_SRAM_NEXT_LU_OFFS
;
1479 mvpp2_prs_sram_bits_clear(pe
, sram_next_off
,
1480 MVPP2_PRS_SRAM_NEXT_LU_MASK
);
1481 mvpp2_prs_sram_bits_set(pe
, sram_next_off
, lu
);
1484 /* In the sram sw entry set sign and value of the next lookup offset
1485 * and the offset value generated to the classifier
1487 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry
*pe
, int shift
,
1492 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT
, 1);
1495 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT
, 1);
1499 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS
)] =
1500 (unsigned char)shift
;
1502 /* Reset and set operation */
1503 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS
,
1504 MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK
);
1505 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS
, op
);
1507 /* Set base offset as current */
1508 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS
, 1);
1511 /* In the sram sw entry set sign and value of the user defined offset
1512 * generated to the classifier
1514 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry
*pe
,
1515 unsigned int type
, int offset
,
1520 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_UDF_SIGN_BIT
, 1);
1521 offset
= 0 - offset
;
1523 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_UDF_SIGN_BIT
, 1);
1527 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_UDF_OFFS
,
1528 MVPP2_PRS_SRAM_UDF_MASK
);
1529 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_UDF_OFFS
, offset
);
1530 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS
+
1531 MVPP2_PRS_SRAM_UDF_BITS
)] &=
1532 ~(MVPP2_PRS_SRAM_UDF_MASK
>> (8 - (MVPP2_PRS_SRAM_UDF_OFFS
% 8)));
1533 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS
+
1534 MVPP2_PRS_SRAM_UDF_BITS
)] |=
1535 (offset
>> (8 - (MVPP2_PRS_SRAM_UDF_OFFS
% 8)));
1537 /* Set offset type */
1538 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_UDF_TYPE_OFFS
,
1539 MVPP2_PRS_SRAM_UDF_TYPE_MASK
);
1540 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_UDF_TYPE_OFFS
, type
);
1542 /* Set offset operation */
1543 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
,
1544 MVPP2_PRS_SRAM_OP_SEL_UDF_MASK
);
1545 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
, op
);
1547 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
+
1548 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS
)] &=
1549 ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK
>>
1550 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
% 8)));
1552 pe
->sram
.byte
[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
+
1553 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS
)] |=
1554 (op
>> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
% 8)));
1556 /* Set base offset as current */
1557 mvpp2_prs_sram_bits_clear(pe
, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS
, 1);
1560 /* Find parser flow entry */
1561 static struct mvpp2_prs_entry
*mvpp2_prs_flow_find(struct mvpp2
*priv
, int flow
)
1563 struct mvpp2_prs_entry
*pe
;
1566 pe
= kzalloc(sizeof(*pe
), GFP_KERNEL
);
1569 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_FLOWS
);
1571 /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
1572 for (tid
= MVPP2_PRS_TCAM_SRAM_SIZE
- 1; tid
>= 0; tid
--) {
1575 if (!priv
->prs_shadow
[tid
].valid
||
1576 priv
->prs_shadow
[tid
].lu
!= MVPP2_PRS_LU_FLOWS
)
1580 mvpp2_prs_hw_read(priv
, pe
);
1581 bits
= mvpp2_prs_sram_ai_get(pe
);
1583 /* Sram store classification lookup ID in AI bits [5:0] */
1584 if ((bits
& MVPP2_PRS_FLOW_ID_MASK
) == flow
)
1592 /* Return first free tcam index, seeking from start to end */
1593 static int mvpp2_prs_tcam_first_free(struct mvpp2
*priv
, unsigned char start
,
1601 if (end
>= MVPP2_PRS_TCAM_SRAM_SIZE
)
1602 end
= MVPP2_PRS_TCAM_SRAM_SIZE
- 1;
1604 for (tid
= start
; tid
<= end
; tid
++) {
1605 if (!priv
->prs_shadow
[tid
].valid
)
1612 /* Enable/disable dropping all mac da's */
1613 static void mvpp2_prs_mac_drop_all_set(struct mvpp2
*priv
, int port
, bool add
)
1615 struct mvpp2_prs_entry pe
;
1617 if (priv
->prs_shadow
[MVPP2_PE_DROP_ALL
].valid
) {
1618 /* Entry exist - update port only */
1619 pe
.index
= MVPP2_PE_DROP_ALL
;
1620 mvpp2_prs_hw_read(priv
, &pe
);
1622 /* Entry doesn't exist - create new */
1623 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1624 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_MAC
);
1625 pe
.index
= MVPP2_PE_DROP_ALL
;
1627 /* Non-promiscuous mode for all ports - DROP unknown packets */
1628 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_DROP_MASK
,
1629 MVPP2_PRS_RI_DROP_MASK
);
1631 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
1632 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
1634 /* Update shadow table */
1635 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_MAC
);
1637 /* Mask all ports */
1638 mvpp2_prs_tcam_port_map_set(&pe
, 0);
1641 /* Update port mask */
1642 mvpp2_prs_tcam_port_set(&pe
, port
, add
);
1644 mvpp2_prs_hw_write(priv
, &pe
);
1647 /* Set port to promiscuous mode */
1648 static void mvpp2_prs_mac_promisc_set(struct mvpp2
*priv
, int port
, bool add
)
1650 struct mvpp2_prs_entry pe
;
1652 /* Promiscuous mode - Accept unknown packets */
1654 if (priv
->prs_shadow
[MVPP2_PE_MAC_PROMISCUOUS
].valid
) {
1655 /* Entry exist - update port only */
1656 pe
.index
= MVPP2_PE_MAC_PROMISCUOUS
;
1657 mvpp2_prs_hw_read(priv
, &pe
);
1659 /* Entry doesn't exist - create new */
1660 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1661 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_MAC
);
1662 pe
.index
= MVPP2_PE_MAC_PROMISCUOUS
;
1664 /* Continue - set next lookup */
1665 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_DSA
);
1667 /* Set result info bits */
1668 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L2_UCAST
,
1669 MVPP2_PRS_RI_L2_CAST_MASK
);
1671 /* Shift to ethertype */
1672 mvpp2_prs_sram_shift_set(&pe
, 2 * ETH_ALEN
,
1673 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
1675 /* Mask all ports */
1676 mvpp2_prs_tcam_port_map_set(&pe
, 0);
1678 /* Update shadow table */
1679 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_MAC
);
1682 /* Update port mask */
1683 mvpp2_prs_tcam_port_set(&pe
, port
, add
);
1685 mvpp2_prs_hw_write(priv
, &pe
);
1688 /* Accept multicast */
1689 static void mvpp2_prs_mac_multi_set(struct mvpp2
*priv
, int port
, int index
,
1692 struct mvpp2_prs_entry pe
;
1693 unsigned char da_mc
;
1695 /* Ethernet multicast address first byte is
1696 * 0x01 for IPv4 and 0x33 for IPv6
1698 da_mc
= (index
== MVPP2_PE_MAC_MC_ALL
) ? 0x01 : 0x33;
1700 if (priv
->prs_shadow
[index
].valid
) {
1701 /* Entry exist - update port only */
1703 mvpp2_prs_hw_read(priv
, &pe
);
1705 /* Entry doesn't exist - create new */
1706 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1707 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_MAC
);
1710 /* Continue - set next lookup */
1711 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_DSA
);
1713 /* Set result info bits */
1714 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L2_MCAST
,
1715 MVPP2_PRS_RI_L2_CAST_MASK
);
1717 /* Update tcam entry data first byte */
1718 mvpp2_prs_tcam_data_byte_set(&pe
, 0, da_mc
, 0xff);
1720 /* Shift to ethertype */
1721 mvpp2_prs_sram_shift_set(&pe
, 2 * ETH_ALEN
,
1722 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
1724 /* Mask all ports */
1725 mvpp2_prs_tcam_port_map_set(&pe
, 0);
1727 /* Update shadow table */
1728 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_MAC
);
1731 /* Update port mask */
1732 mvpp2_prs_tcam_port_set(&pe
, port
, add
);
1734 mvpp2_prs_hw_write(priv
, &pe
);
1737 /* Parser per-port initialization */
1738 static void mvpp2_prs_hw_port_init(struct mvpp2
*priv
, int port
, int lu_first
,
1739 int lu_max
, int offset
)
1744 val
= mvpp2_read(priv
, MVPP2_PRS_INIT_LOOKUP_REG
);
1745 val
&= ~MVPP2_PRS_PORT_LU_MASK(port
);
1746 val
|= MVPP2_PRS_PORT_LU_VAL(port
, lu_first
);
1747 mvpp2_write(priv
, MVPP2_PRS_INIT_LOOKUP_REG
, val
);
1749 /* Set maximum number of loops for packet received from port */
1750 val
= mvpp2_read(priv
, MVPP2_PRS_MAX_LOOP_REG(port
));
1751 val
&= ~MVPP2_PRS_MAX_LOOP_MASK(port
);
1752 val
|= MVPP2_PRS_MAX_LOOP_VAL(port
, lu_max
);
1753 mvpp2_write(priv
, MVPP2_PRS_MAX_LOOP_REG(port
), val
);
1755 /* Set initial offset for packet header extraction for the first
1758 val
= mvpp2_read(priv
, MVPP2_PRS_INIT_OFFS_REG(port
));
1759 val
&= ~MVPP2_PRS_INIT_OFF_MASK(port
);
1760 val
|= MVPP2_PRS_INIT_OFF_VAL(port
, offset
);
1761 mvpp2_write(priv
, MVPP2_PRS_INIT_OFFS_REG(port
), val
);
1764 /* Default flow entries initialization for all ports */
1765 static void mvpp2_prs_def_flow_init(struct mvpp2
*priv
)
1767 struct mvpp2_prs_entry pe
;
1770 for (port
= 0; port
< MVPP2_MAX_PORTS
; port
++) {
1771 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1772 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
1773 pe
.index
= MVPP2_PE_FIRST_DEFAULT_FLOW
- port
;
1775 /* Mask all ports */
1776 mvpp2_prs_tcam_port_map_set(&pe
, 0);
1779 mvpp2_prs_sram_ai_update(&pe
, port
, MVPP2_PRS_FLOW_ID_MASK
);
1780 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_DONE_BIT
, 1);
1782 /* Update shadow table and hw entry */
1783 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_FLOWS
);
1784 mvpp2_prs_hw_write(priv
, &pe
);
1788 /* Set default entry for Marvell Header field */
1789 static void mvpp2_prs_mh_init(struct mvpp2
*priv
)
1791 struct mvpp2_prs_entry pe
;
1793 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1795 pe
.index
= MVPP2_PE_MH_DEFAULT
;
1796 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_MH
);
1797 mvpp2_prs_sram_shift_set(&pe
, MVPP2_MH_SIZE
,
1798 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
1799 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_MAC
);
1801 /* Unmask all ports */
1802 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
1804 /* Update shadow table and hw entry */
1805 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_MH
);
1806 mvpp2_prs_hw_write(priv
, &pe
);
1809 /* Set default entires (place holder) for promiscuous, non-promiscuous and
1810 * multicast MAC addresses
1812 static void mvpp2_prs_mac_init(struct mvpp2
*priv
)
1814 struct mvpp2_prs_entry pe
;
1816 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1818 /* Non-promiscuous mode for all ports - DROP unknown packets */
1819 pe
.index
= MVPP2_PE_MAC_NON_PROMISCUOUS
;
1820 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_MAC
);
1822 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_DROP_MASK
,
1823 MVPP2_PRS_RI_DROP_MASK
);
1824 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
1825 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
1827 /* Unmask all ports */
1828 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
1830 /* Update shadow table and hw entry */
1831 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_MAC
);
1832 mvpp2_prs_hw_write(priv
, &pe
);
1834 /* place holders only - no ports */
1835 mvpp2_prs_mac_drop_all_set(priv
, 0, false);
1836 mvpp2_prs_mac_promisc_set(priv
, 0, false);
1837 mvpp2_prs_mac_multi_set(priv
, MVPP2_PE_MAC_MC_ALL
, 0, false);
1838 mvpp2_prs_mac_multi_set(priv
, MVPP2_PE_MAC_MC_IP6
, 0, false);
1841 /* Match basic ethertypes */
1842 static int mvpp2_prs_etype_init(struct mvpp2
*priv
)
1844 struct mvpp2_prs_entry pe
;
1847 /* Ethertype: PPPoE */
1848 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
1849 MVPP2_PE_LAST_FREE_TID
);
1853 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1854 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
1857 mvpp2_prs_match_etype(&pe
, 0, PROT_PPP_SES
);
1859 mvpp2_prs_sram_shift_set(&pe
, MVPP2_PPPOE_HDR_SIZE
,
1860 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
1861 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_PPPOE
);
1862 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_PPPOE_MASK
,
1863 MVPP2_PRS_RI_PPPOE_MASK
);
1865 /* Update shadow table and hw entry */
1866 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
1867 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
1868 priv
->prs_shadow
[pe
.index
].finish
= false;
1869 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_PPPOE_MASK
,
1870 MVPP2_PRS_RI_PPPOE_MASK
);
1871 mvpp2_prs_hw_write(priv
, &pe
);
1873 /* Ethertype: ARP */
1874 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
1875 MVPP2_PE_LAST_FREE_TID
);
1879 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1880 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
1883 mvpp2_prs_match_etype(&pe
, 0, PROT_ARP
);
1885 /* Generate flow in the next iteration*/
1886 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
1887 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
1888 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_ARP
,
1889 MVPP2_PRS_RI_L3_PROTO_MASK
);
1891 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
1893 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
1895 /* Update shadow table and hw entry */
1896 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
1897 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
1898 priv
->prs_shadow
[pe
.index
].finish
= true;
1899 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_L3_ARP
,
1900 MVPP2_PRS_RI_L3_PROTO_MASK
);
1901 mvpp2_prs_hw_write(priv
, &pe
);
1903 /* Ethertype: LBTD */
1904 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
1905 MVPP2_PE_LAST_FREE_TID
);
1909 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1910 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
1913 mvpp2_prs_match_etype(&pe
, 0, MVPP2_IP_LBDT_TYPE
);
1915 /* Generate flow in the next iteration*/
1916 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
1917 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
1918 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_CPU_CODE_RX_SPEC
|
1919 MVPP2_PRS_RI_UDF3_RX_SPECIAL
,
1920 MVPP2_PRS_RI_CPU_CODE_MASK
|
1921 MVPP2_PRS_RI_UDF3_MASK
);
1923 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
1925 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
1927 /* Update shadow table and hw entry */
1928 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
1929 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
1930 priv
->prs_shadow
[pe
.index
].finish
= true;
1931 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_CPU_CODE_RX_SPEC
|
1932 MVPP2_PRS_RI_UDF3_RX_SPECIAL
,
1933 MVPP2_PRS_RI_CPU_CODE_MASK
|
1934 MVPP2_PRS_RI_UDF3_MASK
);
1935 mvpp2_prs_hw_write(priv
, &pe
);
1937 /* Ethertype: IPv4 without options */
1938 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
1939 MVPP2_PE_LAST_FREE_TID
);
1943 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
1944 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
1947 mvpp2_prs_match_etype(&pe
, 0, PROT_IP
);
1948 mvpp2_prs_tcam_data_byte_set(&pe
, MVPP2_ETH_TYPE_LEN
,
1949 MVPP2_PRS_IPV4_HEAD
| MVPP2_PRS_IPV4_IHL
,
1950 MVPP2_PRS_IPV4_HEAD_MASK
|
1951 MVPP2_PRS_IPV4_IHL_MASK
);
1953 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_IP4
);
1954 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_IP4
,
1955 MVPP2_PRS_RI_L3_PROTO_MASK
);
1956 /* Skip eth_type + 4 bytes of IP header */
1957 mvpp2_prs_sram_shift_set(&pe
, MVPP2_ETH_TYPE_LEN
+ 4,
1958 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
1960 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
1962 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
1964 /* Update shadow table and hw entry */
1965 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
1966 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
1967 priv
->prs_shadow
[pe
.index
].finish
= false;
1968 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_L3_IP4
,
1969 MVPP2_PRS_RI_L3_PROTO_MASK
);
1970 mvpp2_prs_hw_write(priv
, &pe
);
1972 /* Ethertype: IPv4 with options */
1973 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
1974 MVPP2_PE_LAST_FREE_TID
);
1980 /* Clear tcam data before updating */
1981 pe
.tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN
)] = 0x0;
1982 pe
.tcam
.byte
[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN
)] = 0x0;
1984 mvpp2_prs_tcam_data_byte_set(&pe
, MVPP2_ETH_TYPE_LEN
,
1985 MVPP2_PRS_IPV4_HEAD
,
1986 MVPP2_PRS_IPV4_HEAD_MASK
);
1988 /* Clear ri before updating */
1989 pe
.sram
.word
[MVPP2_PRS_SRAM_RI_WORD
] = 0x0;
1990 pe
.sram
.word
[MVPP2_PRS_SRAM_RI_CTRL_WORD
] = 0x0;
1991 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_IP4_OPT
,
1992 MVPP2_PRS_RI_L3_PROTO_MASK
);
1994 /* Update shadow table and hw entry */
1995 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
1996 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
1997 priv
->prs_shadow
[pe
.index
].finish
= false;
1998 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_L3_IP4_OPT
,
1999 MVPP2_PRS_RI_L3_PROTO_MASK
);
2000 mvpp2_prs_hw_write(priv
, &pe
);
2002 /* Ethertype: IPv6 without options */
2003 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2004 MVPP2_PE_LAST_FREE_TID
);
2008 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2009 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
2012 mvpp2_prs_match_etype(&pe
, 0, PROT_IPV6
);
2014 /* Skip DIP of IPV6 header */
2015 mvpp2_prs_sram_shift_set(&pe
, MVPP2_ETH_TYPE_LEN
+ 8 +
2016 MVPP2_MAX_L3_ADDR_SIZE
,
2017 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2018 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_IP6
);
2019 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_IP6
,
2020 MVPP2_PRS_RI_L3_PROTO_MASK
);
2022 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
2024 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
2026 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
2027 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
2028 priv
->prs_shadow
[pe
.index
].finish
= false;
2029 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_L3_IP6
,
2030 MVPP2_PRS_RI_L3_PROTO_MASK
);
2031 mvpp2_prs_hw_write(priv
, &pe
);
2033 /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
2034 memset(&pe
, 0, sizeof(struct mvpp2_prs_entry
));
2035 mvpp2_prs_tcam_lu_set(&pe
, MVPP2_PRS_LU_L2
);
2036 pe
.index
= MVPP2_PE_ETH_TYPE_UN
;
2038 /* Unmask all ports */
2039 mvpp2_prs_tcam_port_map_set(&pe
, MVPP2_PRS_PORT_MASK
);
2041 /* Generate flow in the next iteration*/
2042 mvpp2_prs_sram_bits_set(&pe
, MVPP2_PRS_SRAM_LU_GEN_BIT
, 1);
2043 mvpp2_prs_sram_next_lu_set(&pe
, MVPP2_PRS_LU_FLOWS
);
2044 mvpp2_prs_sram_ri_update(&pe
, MVPP2_PRS_RI_L3_UN
,
2045 MVPP2_PRS_RI_L3_PROTO_MASK
);
2046 /* Set L3 offset even it's unknown L3 */
2047 mvpp2_prs_sram_offset_set(&pe
, MVPP2_PRS_SRAM_UDF_TYPE_L3
,
2049 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
);
2051 /* Update shadow table and hw entry */
2052 mvpp2_prs_shadow_set(priv
, pe
.index
, MVPP2_PRS_LU_L2
);
2053 priv
->prs_shadow
[pe
.index
].udf
= MVPP2_PRS_UDF_L2_DEF
;
2054 priv
->prs_shadow
[pe
.index
].finish
= true;
2055 mvpp2_prs_shadow_ri_set(priv
, pe
.index
, MVPP2_PRS_RI_L3_UN
,
2056 MVPP2_PRS_RI_L3_PROTO_MASK
);
2057 mvpp2_prs_hw_write(priv
, &pe
);
2062 /* Parser default initialization */
2063 static int mvpp2_prs_default_init(struct udevice
*dev
,
2068 /* Enable tcam table */
2069 mvpp2_write(priv
, MVPP2_PRS_TCAM_CTRL_REG
, MVPP2_PRS_TCAM_EN_MASK
);
2071 /* Clear all tcam and sram entries */
2072 for (index
= 0; index
< MVPP2_PRS_TCAM_SRAM_SIZE
; index
++) {
2073 mvpp2_write(priv
, MVPP2_PRS_TCAM_IDX_REG
, index
);
2074 for (i
= 0; i
< MVPP2_PRS_TCAM_WORDS
; i
++)
2075 mvpp2_write(priv
, MVPP2_PRS_TCAM_DATA_REG(i
), 0);
2077 mvpp2_write(priv
, MVPP2_PRS_SRAM_IDX_REG
, index
);
2078 for (i
= 0; i
< MVPP2_PRS_SRAM_WORDS
; i
++)
2079 mvpp2_write(priv
, MVPP2_PRS_SRAM_DATA_REG(i
), 0);
2082 /* Invalidate all tcam entries */
2083 for (index
= 0; index
< MVPP2_PRS_TCAM_SRAM_SIZE
; index
++)
2084 mvpp2_prs_hw_inv(priv
, index
);
2086 priv
->prs_shadow
= devm_kcalloc(dev
, MVPP2_PRS_TCAM_SRAM_SIZE
,
2087 sizeof(struct mvpp2_prs_shadow
),
2089 if (!priv
->prs_shadow
)
2092 /* Always start from lookup = 0 */
2093 for (index
= 0; index
< MVPP2_MAX_PORTS
; index
++)
2094 mvpp2_prs_hw_port_init(priv
, index
, MVPP2_PRS_LU_MH
,
2095 MVPP2_PRS_PORT_LU_MAX
, 0);
2097 mvpp2_prs_def_flow_init(priv
);
2099 mvpp2_prs_mh_init(priv
);
2101 mvpp2_prs_mac_init(priv
);
2103 err
= mvpp2_prs_etype_init(priv
);
2110 /* Compare MAC DA with tcam entry data */
2111 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry
*pe
,
2112 const u8
*da
, unsigned char *mask
)
2114 unsigned char tcam_byte
, tcam_mask
;
2117 for (index
= 0; index
< ETH_ALEN
; index
++) {
2118 mvpp2_prs_tcam_data_byte_get(pe
, index
, &tcam_byte
, &tcam_mask
);
2119 if (tcam_mask
!= mask
[index
])
2122 if ((tcam_mask
& tcam_byte
) != (da
[index
] & mask
[index
]))
2129 /* Find tcam entry with matched pair <MAC DA, port> */
2130 static struct mvpp2_prs_entry
*
2131 mvpp2_prs_mac_da_range_find(struct mvpp2
*priv
, int pmap
, const u8
*da
,
2132 unsigned char *mask
, int udf_type
)
2134 struct mvpp2_prs_entry
*pe
;
2137 pe
= kzalloc(sizeof(*pe
), GFP_KERNEL
);
2140 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_MAC
);
2142 /* Go through the all entires with MVPP2_PRS_LU_MAC */
2143 for (tid
= MVPP2_PE_FIRST_FREE_TID
;
2144 tid
<= MVPP2_PE_LAST_FREE_TID
; tid
++) {
2145 unsigned int entry_pmap
;
2147 if (!priv
->prs_shadow
[tid
].valid
||
2148 (priv
->prs_shadow
[tid
].lu
!= MVPP2_PRS_LU_MAC
) ||
2149 (priv
->prs_shadow
[tid
].udf
!= udf_type
))
2153 mvpp2_prs_hw_read(priv
, pe
);
2154 entry_pmap
= mvpp2_prs_tcam_port_map_get(pe
);
2156 if (mvpp2_prs_mac_range_equals(pe
, da
, mask
) &&
2165 /* Update parser's mac da entry */
2166 static int mvpp2_prs_mac_da_accept(struct mvpp2
*priv
, int port
,
2167 const u8
*da
, bool add
)
2169 struct mvpp2_prs_entry
*pe
;
2170 unsigned int pmap
, len
, ri
;
2171 unsigned char mask
[ETH_ALEN
] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
2174 /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
2175 pe
= mvpp2_prs_mac_da_range_find(priv
, (1 << port
), da
, mask
,
2176 MVPP2_PRS_UDF_MAC_DEF
);
2183 /* Create new TCAM entry */
2184 /* Find first range mac entry*/
2185 for (tid
= MVPP2_PE_FIRST_FREE_TID
;
2186 tid
<= MVPP2_PE_LAST_FREE_TID
; tid
++)
2187 if (priv
->prs_shadow
[tid
].valid
&&
2188 (priv
->prs_shadow
[tid
].lu
== MVPP2_PRS_LU_MAC
) &&
2189 (priv
->prs_shadow
[tid
].udf
==
2190 MVPP2_PRS_UDF_MAC_RANGE
))
2193 /* Go through the all entries from first to last */
2194 tid
= mvpp2_prs_tcam_first_free(priv
, MVPP2_PE_FIRST_FREE_TID
,
2199 pe
= kzalloc(sizeof(*pe
), GFP_KERNEL
);
2202 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_MAC
);
2205 /* Mask all ports */
2206 mvpp2_prs_tcam_port_map_set(pe
, 0);
2209 /* Update port mask */
2210 mvpp2_prs_tcam_port_set(pe
, port
, add
);
2212 /* Invalidate the entry if no ports are left enabled */
2213 pmap
= mvpp2_prs_tcam_port_map_get(pe
);
2219 mvpp2_prs_hw_inv(priv
, pe
->index
);
2220 priv
->prs_shadow
[pe
->index
].valid
= false;
2225 /* Continue - set next lookup */
2226 mvpp2_prs_sram_next_lu_set(pe
, MVPP2_PRS_LU_DSA
);
2228 /* Set match on DA */
2231 mvpp2_prs_tcam_data_byte_set(pe
, len
, da
[len
], 0xff);
2233 /* Set result info bits */
2234 ri
= MVPP2_PRS_RI_L2_UCAST
| MVPP2_PRS_RI_MAC_ME_MASK
;
2236 mvpp2_prs_sram_ri_update(pe
, ri
, MVPP2_PRS_RI_L2_CAST_MASK
|
2237 MVPP2_PRS_RI_MAC_ME_MASK
);
2238 mvpp2_prs_shadow_ri_set(priv
, pe
->index
, ri
, MVPP2_PRS_RI_L2_CAST_MASK
|
2239 MVPP2_PRS_RI_MAC_ME_MASK
);
2241 /* Shift to ethertype */
2242 mvpp2_prs_sram_shift_set(pe
, 2 * ETH_ALEN
,
2243 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
);
2245 /* Update shadow table and hw entry */
2246 priv
->prs_shadow
[pe
->index
].udf
= MVPP2_PRS_UDF_MAC_DEF
;
2247 mvpp2_prs_shadow_set(priv
, pe
->index
, MVPP2_PRS_LU_MAC
);
2248 mvpp2_prs_hw_write(priv
, pe
);
2255 static int mvpp2_prs_update_mac_da(struct mvpp2_port
*port
, const u8
*da
)
2259 /* Remove old parser entry */
2260 err
= mvpp2_prs_mac_da_accept(port
->priv
, port
->id
, port
->dev_addr
,
2265 /* Add new parser entry */
2266 err
= mvpp2_prs_mac_da_accept(port
->priv
, port
->id
, da
, true);
2270 /* Set addr in the device */
2271 memcpy(port
->dev_addr
, da
, ETH_ALEN
);
2276 /* Set prs flow for the port */
2277 static int mvpp2_prs_def_flow(struct mvpp2_port
*port
)
2279 struct mvpp2_prs_entry
*pe
;
2282 pe
= mvpp2_prs_flow_find(port
->priv
, port
->id
);
2284 /* Such entry not exist */
2286 /* Go through the all entires from last to first */
2287 tid
= mvpp2_prs_tcam_first_free(port
->priv
,
2288 MVPP2_PE_LAST_FREE_TID
,
2289 MVPP2_PE_FIRST_FREE_TID
);
2293 pe
= kzalloc(sizeof(*pe
), GFP_KERNEL
);
2297 mvpp2_prs_tcam_lu_set(pe
, MVPP2_PRS_LU_FLOWS
);
2301 mvpp2_prs_sram_ai_update(pe
, port
->id
, MVPP2_PRS_FLOW_ID_MASK
);
2302 mvpp2_prs_sram_bits_set(pe
, MVPP2_PRS_SRAM_LU_DONE_BIT
, 1);
2304 /* Update shadow table */
2305 mvpp2_prs_shadow_set(port
->priv
, pe
->index
, MVPP2_PRS_LU_FLOWS
);
2308 mvpp2_prs_tcam_port_map_set(pe
, (1 << port
->id
));
2309 mvpp2_prs_hw_write(port
->priv
, pe
);
2315 /* Classifier configuration routines */
2317 /* Update classification flow table registers */
2318 static void mvpp2_cls_flow_write(struct mvpp2
*priv
,
2319 struct mvpp2_cls_flow_entry
*fe
)
2321 mvpp2_write(priv
, MVPP2_CLS_FLOW_INDEX_REG
, fe
->index
);
2322 mvpp2_write(priv
, MVPP2_CLS_FLOW_TBL0_REG
, fe
->data
[0]);
2323 mvpp2_write(priv
, MVPP2_CLS_FLOW_TBL1_REG
, fe
->data
[1]);
2324 mvpp2_write(priv
, MVPP2_CLS_FLOW_TBL2_REG
, fe
->data
[2]);
2327 /* Update classification lookup table register */
2328 static void mvpp2_cls_lookup_write(struct mvpp2
*priv
,
2329 struct mvpp2_cls_lookup_entry
*le
)
2333 val
= (le
->way
<< MVPP2_CLS_LKP_INDEX_WAY_OFFS
) | le
->lkpid
;
2334 mvpp2_write(priv
, MVPP2_CLS_LKP_INDEX_REG
, val
);
2335 mvpp2_write(priv
, MVPP2_CLS_LKP_TBL_REG
, le
->data
);
2338 /* Classifier default initialization */
2339 static void mvpp2_cls_init(struct mvpp2
*priv
)
2341 struct mvpp2_cls_lookup_entry le
;
2342 struct mvpp2_cls_flow_entry fe
;
2345 /* Enable classifier */
2346 mvpp2_write(priv
, MVPP2_CLS_MODE_REG
, MVPP2_CLS_MODE_ACTIVE_MASK
);
2348 /* Clear classifier flow table */
2349 memset(&fe
.data
, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS
);
2350 for (index
= 0; index
< MVPP2_CLS_FLOWS_TBL_SIZE
; index
++) {
2352 mvpp2_cls_flow_write(priv
, &fe
);
2355 /* Clear classifier lookup table */
2357 for (index
= 0; index
< MVPP2_CLS_LKP_TBL_SIZE
; index
++) {
2360 mvpp2_cls_lookup_write(priv
, &le
);
2363 mvpp2_cls_lookup_write(priv
, &le
);
2367 static void mvpp2_cls_port_config(struct mvpp2_port
*port
)
2369 struct mvpp2_cls_lookup_entry le
;
2372 /* Set way for the port */
2373 val
= mvpp2_read(port
->priv
, MVPP2_CLS_PORT_WAY_REG
);
2374 val
&= ~MVPP2_CLS_PORT_WAY_MASK(port
->id
);
2375 mvpp2_write(port
->priv
, MVPP2_CLS_PORT_WAY_REG
, val
);
2377 /* Pick the entry to be accessed in lookup ID decoding table
2378 * according to the way and lkpid.
2380 le
.lkpid
= port
->id
;
2384 /* Set initial CPU queue for receiving packets */
2385 le
.data
&= ~MVPP2_CLS_LKP_TBL_RXQ_MASK
;
2386 le
.data
|= port
->first_rxq
;
2388 /* Disable classification engines */
2389 le
.data
&= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK
;
2391 /* Update lookup ID table entry */
2392 mvpp2_cls_lookup_write(port
->priv
, &le
);
2395 /* Set CPU queue number for oversize packets */
2396 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port
*port
)
2400 mvpp2_write(port
->priv
, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port
->id
),
2401 port
->first_rxq
& MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK
);
2403 mvpp2_write(port
->priv
, MVPP2_CLS_SWFWD_P2HQ_REG(port
->id
),
2404 (port
->first_rxq
>> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS
));
2406 val
= mvpp2_read(port
->priv
, MVPP2_CLS_SWFWD_PCTRL_REG
);
2407 val
|= MVPP2_CLS_SWFWD_PCTRL_MASK(port
->id
);
2408 mvpp2_write(port
->priv
, MVPP2_CLS_SWFWD_PCTRL_REG
, val
);
2411 /* Buffer Manager configuration routines */
2414 static int mvpp2_bm_pool_create(struct udevice
*dev
,
2416 struct mvpp2_bm_pool
*bm_pool
, int size
)
2420 /* Number of buffer pointers must be a multiple of 16, as per
2421 * hardware constraints
2423 if (!IS_ALIGNED(size
, 16))
2426 bm_pool
->virt_addr
= buffer_loc
.bm_pool
[bm_pool
->id
];
2427 bm_pool
->dma_addr
= (dma_addr_t
)buffer_loc
.bm_pool
[bm_pool
->id
];
2428 if (!bm_pool
->virt_addr
)
2431 if (!IS_ALIGNED((unsigned long)bm_pool
->virt_addr
,
2432 MVPP2_BM_POOL_PTR_ALIGN
)) {
2433 dev_err(&pdev
->dev
, "BM pool %d is not %d bytes aligned\n",
2434 bm_pool
->id
, MVPP2_BM_POOL_PTR_ALIGN
);
2438 mvpp2_write(priv
, MVPP2_BM_POOL_BASE_REG(bm_pool
->id
),
2439 lower_32_bits(bm_pool
->dma_addr
));
2440 mvpp2_write(priv
, MVPP2_BM_POOL_SIZE_REG(bm_pool
->id
), size
);
2442 val
= mvpp2_read(priv
, MVPP2_BM_POOL_CTRL_REG(bm_pool
->id
));
2443 val
|= MVPP2_BM_START_MASK
;
2444 mvpp2_write(priv
, MVPP2_BM_POOL_CTRL_REG(bm_pool
->id
), val
);
2446 bm_pool
->type
= MVPP2_BM_FREE
;
2447 bm_pool
->size
= size
;
2448 bm_pool
->pkt_size
= 0;
2449 bm_pool
->buf_num
= 0;
2454 /* Set pool buffer size */
2455 static void mvpp2_bm_pool_bufsize_set(struct mvpp2
*priv
,
2456 struct mvpp2_bm_pool
*bm_pool
,
2461 bm_pool
->buf_size
= buf_size
;
2463 val
= ALIGN(buf_size
, 1 << MVPP2_POOL_BUF_SIZE_OFFSET
);
2464 mvpp2_write(priv
, MVPP2_POOL_BUF_SIZE_REG(bm_pool
->id
), val
);
2467 /* Free all buffers from the pool */
2468 static void mvpp2_bm_bufs_free(struct udevice
*dev
, struct mvpp2
*priv
,
2469 struct mvpp2_bm_pool
*bm_pool
)
2471 bm_pool
->buf_num
= 0;
2475 static int mvpp2_bm_pool_destroy(struct udevice
*dev
,
2477 struct mvpp2_bm_pool
*bm_pool
)
2481 mvpp2_bm_bufs_free(dev
, priv
, bm_pool
);
2482 if (bm_pool
->buf_num
) {
2483 dev_err(dev
, "cannot free all buffers in pool %d\n", bm_pool
->id
);
2487 val
= mvpp2_read(priv
, MVPP2_BM_POOL_CTRL_REG(bm_pool
->id
));
2488 val
|= MVPP2_BM_STOP_MASK
;
2489 mvpp2_write(priv
, MVPP2_BM_POOL_CTRL_REG(bm_pool
->id
), val
);
2494 static int mvpp2_bm_pools_init(struct udevice
*dev
,
2498 struct mvpp2_bm_pool
*bm_pool
;
2500 /* Create all pools with maximum size */
2501 size
= MVPP2_BM_POOL_SIZE_MAX
;
2502 for (i
= 0; i
< MVPP2_BM_POOLS_NUM
; i
++) {
2503 bm_pool
= &priv
->bm_pools
[i
];
2505 err
= mvpp2_bm_pool_create(dev
, priv
, bm_pool
, size
);
2507 goto err_unroll_pools
;
2508 mvpp2_bm_pool_bufsize_set(priv
, bm_pool
, 0);
2513 dev_err(&pdev
->dev
, "failed to create BM pool %d, size %d\n", i
, size
);
2514 for (i
= i
- 1; i
>= 0; i
--)
2515 mvpp2_bm_pool_destroy(dev
, priv
, &priv
->bm_pools
[i
]);
2519 static int mvpp2_bm_init(struct udevice
*dev
, struct mvpp2
*priv
)
2523 for (i
= 0; i
< MVPP2_BM_POOLS_NUM
; i
++) {
2524 /* Mask BM all interrupts */
2525 mvpp2_write(priv
, MVPP2_BM_INTR_MASK_REG(i
), 0);
2526 /* Clear BM cause register */
2527 mvpp2_write(priv
, MVPP2_BM_INTR_CAUSE_REG(i
), 0);
2530 /* Allocate and initialize BM pools */
2531 priv
->bm_pools
= devm_kcalloc(dev
, MVPP2_BM_POOLS_NUM
,
2532 sizeof(struct mvpp2_bm_pool
), GFP_KERNEL
);
2533 if (!priv
->bm_pools
)
2536 err
= mvpp2_bm_pools_init(dev
, priv
);
2542 /* Attach long pool to rxq */
2543 static void mvpp2_rxq_long_pool_set(struct mvpp2_port
*port
,
2544 int lrxq
, int long_pool
)
2549 /* Get queue physical ID */
2550 prxq
= port
->rxqs
[lrxq
]->id
;
2552 if (port
->priv
->hw_version
== MVPP21
)
2553 mask
= MVPP21_RXQ_POOL_LONG_MASK
;
2555 mask
= MVPP22_RXQ_POOL_LONG_MASK
;
2557 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_CONFIG_REG(prxq
));
2559 val
|= (long_pool
<< MVPP2_RXQ_POOL_LONG_OFFS
) & mask
;
2560 mvpp2_write(port
->priv
, MVPP2_RXQ_CONFIG_REG(prxq
), val
);
2563 /* Set pool number in a BM cookie */
2564 static inline u32
mvpp2_bm_cookie_pool_set(u32 cookie
, int pool
)
2568 bm
= cookie
& ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS
);
2569 bm
|= ((pool
& 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS
);
2574 /* Get pool number from a BM cookie */
2575 static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie
)
2577 return (cookie
>> MVPP2_BM_COOKIE_POOL_OFFS
) & 0xFF;
2580 /* Release buffer to BM */
2581 static inline void mvpp2_bm_pool_put(struct mvpp2_port
*port
, int pool
,
2582 dma_addr_t buf_dma_addr
,
2583 unsigned long buf_phys_addr
)
2585 if (port
->priv
->hw_version
== MVPP22
) {
2588 if (sizeof(dma_addr_t
) == 8)
2589 val
|= upper_32_bits(buf_dma_addr
) &
2590 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK
;
2592 if (sizeof(phys_addr_t
) == 8)
2593 val
|= (upper_32_bits(buf_phys_addr
)
2594 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT
) &
2595 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK
;
2597 mvpp2_write(port
->priv
, MVPP22_BM_ADDR_HIGH_RLS_REG
, val
);
2600 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
2601 * returned in the "cookie" field of the RX
2602 * descriptor. Instead of storing the virtual address, we
2603 * store the physical address
2605 mvpp2_write(port
->priv
, MVPP2_BM_VIRT_RLS_REG
, buf_phys_addr
);
2606 mvpp2_write(port
->priv
, MVPP2_BM_PHY_RLS_REG(pool
), buf_dma_addr
);
2609 /* Refill BM pool */
2610 static void mvpp2_pool_refill(struct mvpp2_port
*port
, u32 bm
,
2611 dma_addr_t dma_addr
,
2612 phys_addr_t phys_addr
)
2614 int pool
= mvpp2_bm_cookie_pool_get(bm
);
2616 mvpp2_bm_pool_put(port
, pool
, dma_addr
, phys_addr
);
2619 /* Allocate buffers for the pool */
2620 static int mvpp2_bm_bufs_add(struct mvpp2_port
*port
,
2621 struct mvpp2_bm_pool
*bm_pool
, int buf_num
)
2626 (buf_num
+ bm_pool
->buf_num
> bm_pool
->size
)) {
2627 netdev_err(port
->dev
,
2628 "cannot allocate %d buffers for pool %d\n",
2629 buf_num
, bm_pool
->id
);
2633 for (i
= 0; i
< buf_num
; i
++) {
2634 mvpp2_bm_pool_put(port
, bm_pool
->id
,
2635 (dma_addr_t
)buffer_loc
.rx_buffer
[i
],
2636 (unsigned long)buffer_loc
.rx_buffer
[i
]);
2640 /* Update BM driver with number of buffers added to pool */
2641 bm_pool
->buf_num
+= i
;
2642 bm_pool
->in_use_thresh
= bm_pool
->buf_num
/ 4;
2647 /* Notify the driver that BM pool is being used as specific type and return the
2648 * pool pointer on success
2650 static struct mvpp2_bm_pool
*
2651 mvpp2_bm_pool_use(struct mvpp2_port
*port
, int pool
, enum mvpp2_bm_type type
,
2654 struct mvpp2_bm_pool
*new_pool
= &port
->priv
->bm_pools
[pool
];
2657 if (new_pool
->type
!= MVPP2_BM_FREE
&& new_pool
->type
!= type
) {
2658 netdev_err(port
->dev
, "mixing pool types is forbidden\n");
2662 if (new_pool
->type
== MVPP2_BM_FREE
)
2663 new_pool
->type
= type
;
2665 /* Allocate buffers in case BM pool is used as long pool, but packet
2666 * size doesn't match MTU or BM pool hasn't being used yet
2668 if (((type
== MVPP2_BM_SWF_LONG
) && (pkt_size
> new_pool
->pkt_size
)) ||
2669 (new_pool
->pkt_size
== 0)) {
2672 /* Set default buffer number or free all the buffers in case
2673 * the pool is not empty
2675 pkts_num
= new_pool
->buf_num
;
2677 pkts_num
= type
== MVPP2_BM_SWF_LONG
?
2678 MVPP2_BM_LONG_BUF_NUM
:
2679 MVPP2_BM_SHORT_BUF_NUM
;
2681 mvpp2_bm_bufs_free(NULL
,
2682 port
->priv
, new_pool
);
2684 new_pool
->pkt_size
= pkt_size
;
2686 /* Allocate buffers for this pool */
2687 num
= mvpp2_bm_bufs_add(port
, new_pool
, pkts_num
);
2688 if (num
!= pkts_num
) {
2689 dev_err(dev
, "pool %d: %d of %d allocated\n",
2690 new_pool
->id
, num
, pkts_num
);
2695 mvpp2_bm_pool_bufsize_set(port
->priv
, new_pool
,
2696 MVPP2_RX_BUF_SIZE(new_pool
->pkt_size
));
2701 /* Initialize pools for swf */
2702 static int mvpp2_swf_bm_pool_init(struct mvpp2_port
*port
)
2706 if (!port
->pool_long
) {
2708 mvpp2_bm_pool_use(port
, MVPP2_BM_SWF_LONG_POOL(port
->id
),
2711 if (!port
->pool_long
)
2714 port
->pool_long
->port_map
|= (1 << port
->id
);
2716 for (rxq
= 0; rxq
< rxq_number
; rxq
++)
2717 mvpp2_rxq_long_pool_set(port
, rxq
, port
->pool_long
->id
);
2723 /* Port configuration routines */
2725 static void mvpp2_port_mii_set(struct mvpp2_port
*port
)
2729 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_2_REG
);
2731 switch (port
->phy_interface
) {
2732 case PHY_INTERFACE_MODE_SGMII
:
2733 val
|= MVPP2_GMAC_INBAND_AN_MASK
;
2735 case PHY_INTERFACE_MODE_RGMII
:
2736 val
|= MVPP2_GMAC_PORT_RGMII_MASK
;
2738 val
&= ~MVPP2_GMAC_PCS_ENABLE_MASK
;
2741 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_2_REG
);
2744 static void mvpp2_port_fc_adv_enable(struct mvpp2_port
*port
)
2748 val
= readl(port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
2749 val
|= MVPP2_GMAC_FC_ADV_EN
;
2750 writel(val
, port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
2753 static void mvpp2_port_enable(struct mvpp2_port
*port
)
2757 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
2758 val
|= MVPP2_GMAC_PORT_EN_MASK
;
2759 val
|= MVPP2_GMAC_MIB_CNTR_EN_MASK
;
2760 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
2763 static void mvpp2_port_disable(struct mvpp2_port
*port
)
2767 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
2768 val
&= ~(MVPP2_GMAC_PORT_EN_MASK
);
2769 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
2772 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
2773 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port
*port
)
2777 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_1_REG
) &
2778 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK
;
2779 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_1_REG
);
2782 /* Configure loopback port */
2783 static void mvpp2_port_loopback_set(struct mvpp2_port
*port
)
2787 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_1_REG
);
2789 if (port
->speed
== 1000)
2790 val
|= MVPP2_GMAC_GMII_LB_EN_MASK
;
2792 val
&= ~MVPP2_GMAC_GMII_LB_EN_MASK
;
2794 if (port
->phy_interface
== PHY_INTERFACE_MODE_SGMII
)
2795 val
|= MVPP2_GMAC_PCS_LB_EN_MASK
;
2797 val
&= ~MVPP2_GMAC_PCS_LB_EN_MASK
;
2799 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_1_REG
);
2802 static void mvpp2_port_reset(struct mvpp2_port
*port
)
2806 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_2_REG
) &
2807 ~MVPP2_GMAC_PORT_RESET_MASK
;
2808 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_2_REG
);
2810 while (readl(port
->base
+ MVPP2_GMAC_CTRL_2_REG
) &
2811 MVPP2_GMAC_PORT_RESET_MASK
)
2815 /* Change maximum receive size of the port */
2816 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port
*port
)
2820 val
= readl(port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
2821 val
&= ~MVPP2_GMAC_MAX_RX_SIZE_MASK
;
2822 val
|= (((port
->pkt_size
- MVPP2_MH_SIZE
) / 2) <<
2823 MVPP2_GMAC_MAX_RX_SIZE_OFFS
);
2824 writel(val
, port
->base
+ MVPP2_GMAC_CTRL_0_REG
);
2827 /* Set defaults to the MVPP2 port */
2828 static void mvpp2_defaults_set(struct mvpp2_port
*port
)
2830 int tx_port_num
, val
, queue
, ptxq
, lrxq
;
2832 if (port
->priv
->hw_version
== MVPP21
) {
2833 /* Configure port to loopback if needed */
2834 if (port
->flags
& MVPP2_F_LOOPBACK
)
2835 mvpp2_port_loopback_set(port
);
2837 /* Update TX FIFO MIN Threshold */
2838 val
= readl(port
->base
+ MVPP2_GMAC_PORT_FIFO_CFG_1_REG
);
2839 val
&= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK
;
2840 /* Min. TX threshold must be less than minimal packet length */
2841 val
|= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
2842 writel(val
, port
->base
+ MVPP2_GMAC_PORT_FIFO_CFG_1_REG
);
2845 /* Disable Legacy WRR, Disable EJP, Release from reset */
2846 tx_port_num
= mvpp2_egress_port(port
);
2847 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PORT_INDEX_REG
,
2849 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_CMD_1_REG
, 0);
2851 /* Close bandwidth for all queues */
2852 for (queue
= 0; queue
< MVPP2_MAX_TXQ
; queue
++) {
2853 ptxq
= mvpp2_txq_phys(port
->id
, queue
);
2854 mvpp2_write(port
->priv
,
2855 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq
), 0);
2858 /* Set refill period to 1 usec, refill tokens
2859 * and bucket size to maximum
2861 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PERIOD_REG
, 0xc8);
2862 val
= mvpp2_read(port
->priv
, MVPP2_TXP_SCHED_REFILL_REG
);
2863 val
&= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK
;
2864 val
|= MVPP2_TXP_REFILL_PERIOD_MASK(1);
2865 val
|= MVPP2_TXP_REFILL_TOKENS_ALL_MASK
;
2866 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_REFILL_REG
, val
);
2867 val
= MVPP2_TXP_TOKEN_SIZE_MAX
;
2868 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_TOKEN_SIZE_REG
, val
);
2870 /* Set MaximumLowLatencyPacketSize value to 256 */
2871 mvpp2_write(port
->priv
, MVPP2_RX_CTRL_REG(port
->id
),
2872 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK
|
2873 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
2875 /* Enable Rx cache snoop */
2876 for (lrxq
= 0; lrxq
< rxq_number
; lrxq
++) {
2877 queue
= port
->rxqs
[lrxq
]->id
;
2878 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
));
2879 val
|= MVPP2_SNOOP_PKT_SIZE_MASK
|
2880 MVPP2_SNOOP_BUF_HDR_MASK
;
2881 mvpp2_write(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
), val
);
2885 /* Enable/disable receiving packets */
2886 static void mvpp2_ingress_enable(struct mvpp2_port
*port
)
2891 for (lrxq
= 0; lrxq
< rxq_number
; lrxq
++) {
2892 queue
= port
->rxqs
[lrxq
]->id
;
2893 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
));
2894 val
&= ~MVPP2_RXQ_DISABLE_MASK
;
2895 mvpp2_write(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
), val
);
2899 static void mvpp2_ingress_disable(struct mvpp2_port
*port
)
2904 for (lrxq
= 0; lrxq
< rxq_number
; lrxq
++) {
2905 queue
= port
->rxqs
[lrxq
]->id
;
2906 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
));
2907 val
|= MVPP2_RXQ_DISABLE_MASK
;
2908 mvpp2_write(port
->priv
, MVPP2_RXQ_CONFIG_REG(queue
), val
);
2912 /* Enable transmit via physical egress queue
2913 * - HW starts take descriptors from DRAM
2915 static void mvpp2_egress_enable(struct mvpp2_port
*port
)
2919 int tx_port_num
= mvpp2_egress_port(port
);
2921 /* Enable all initialized TXs. */
2923 for (queue
= 0; queue
< txq_number
; queue
++) {
2924 struct mvpp2_tx_queue
*txq
= port
->txqs
[queue
];
2926 if (txq
->descs
!= NULL
)
2927 qmap
|= (1 << queue
);
2930 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PORT_INDEX_REG
, tx_port_num
);
2931 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_Q_CMD_REG
, qmap
);
2934 /* Disable transmit via physical egress queue
2935 * - HW doesn't take descriptors from DRAM
2937 static void mvpp2_egress_disable(struct mvpp2_port
*port
)
2941 int tx_port_num
= mvpp2_egress_port(port
);
2943 /* Issue stop command for active channels only */
2944 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PORT_INDEX_REG
, tx_port_num
);
2945 reg_data
= (mvpp2_read(port
->priv
, MVPP2_TXP_SCHED_Q_CMD_REG
)) &
2946 MVPP2_TXP_SCHED_ENQ_MASK
;
2948 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_Q_CMD_REG
,
2949 (reg_data
<< MVPP2_TXP_SCHED_DISQ_OFFSET
));
2951 /* Wait for all Tx activity to terminate. */
2954 if (delay
>= MVPP2_TX_DISABLE_TIMEOUT_MSEC
) {
2955 netdev_warn(port
->dev
,
2956 "Tx stop timed out, status=0x%08x\n",
2963 /* Check port TX Command register that all
2964 * Tx queues are stopped
2966 reg_data
= mvpp2_read(port
->priv
, MVPP2_TXP_SCHED_Q_CMD_REG
);
2967 } while (reg_data
& MVPP2_TXP_SCHED_ENQ_MASK
);
2970 /* Rx descriptors helper methods */
2972 /* Get number of Rx descriptors occupied by received packets */
2974 mvpp2_rxq_received(struct mvpp2_port
*port
, int rxq_id
)
2976 u32 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_STATUS_REG(rxq_id
));
2978 return val
& MVPP2_RXQ_OCCUPIED_MASK
;
2981 /* Update Rx queue status with the number of occupied and available
2982 * Rx descriptor slots.
2985 mvpp2_rxq_status_update(struct mvpp2_port
*port
, int rxq_id
,
2986 int used_count
, int free_count
)
2988 /* Decrement the number of used descriptors and increment count
2989 * increment the number of free descriptors.
2991 u32 val
= used_count
| (free_count
<< MVPP2_RXQ_NUM_NEW_OFFSET
);
2993 mvpp2_write(port
->priv
, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id
), val
);
2996 /* Get pointer to next RX descriptor to be processed by SW */
2997 static inline struct mvpp2_rx_desc
*
2998 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue
*rxq
)
3000 int rx_desc
= rxq
->next_desc_to_proc
;
3002 rxq
->next_desc_to_proc
= MVPP2_QUEUE_NEXT_DESC(rxq
, rx_desc
);
3003 prefetch(rxq
->descs
+ rxq
->next_desc_to_proc
);
3004 return rxq
->descs
+ rx_desc
;
3007 /* Set rx queue offset */
3008 static void mvpp2_rxq_offset_set(struct mvpp2_port
*port
,
3009 int prxq
, int offset
)
3013 /* Convert offset from bytes to units of 32 bytes */
3014 offset
= offset
>> 5;
3016 val
= mvpp2_read(port
->priv
, MVPP2_RXQ_CONFIG_REG(prxq
));
3017 val
&= ~MVPP2_RXQ_PACKET_OFFSET_MASK
;
3020 val
|= ((offset
<< MVPP2_RXQ_PACKET_OFFSET_OFFS
) &
3021 MVPP2_RXQ_PACKET_OFFSET_MASK
);
3023 mvpp2_write(port
->priv
, MVPP2_RXQ_CONFIG_REG(prxq
), val
);
3026 /* Obtain BM cookie information from descriptor */
3027 static u32
mvpp2_bm_cookie_build(struct mvpp2_port
*port
,
3028 struct mvpp2_rx_desc
*rx_desc
)
3030 int cpu
= smp_processor_id();
3033 pool
= (mvpp2_rxdesc_status_get(port
, rx_desc
) &
3034 MVPP2_RXD_BM_POOL_ID_MASK
) >>
3035 MVPP2_RXD_BM_POOL_ID_OFFS
;
3037 return ((pool
& 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS
) |
3038 ((cpu
& 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS
);
3041 /* Tx descriptors helper methods */
3043 /* Get number of Tx descriptors waiting to be transmitted by HW */
3044 static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port
*port
,
3045 struct mvpp2_tx_queue
*txq
)
3049 mvpp2_write(port
->priv
, MVPP2_TXQ_NUM_REG
, txq
->id
);
3050 val
= mvpp2_read(port
->priv
, MVPP2_TXQ_PENDING_REG
);
3052 return val
& MVPP2_TXQ_PENDING_MASK
;
3055 /* Get pointer to next Tx descriptor to be processed (send) by HW */
3056 static struct mvpp2_tx_desc
*
3057 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue
*txq
)
3059 int tx_desc
= txq
->next_desc_to_proc
;
3061 txq
->next_desc_to_proc
= MVPP2_QUEUE_NEXT_DESC(txq
, tx_desc
);
3062 return txq
->descs
+ tx_desc
;
3065 /* Update HW with number of aggregated Tx descriptors to be sent */
3066 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port
*port
, int pending
)
3068 /* aggregated access - relevant TXQ number is written in TX desc */
3069 mvpp2_write(port
->priv
, MVPP2_AGGR_TXQ_UPDATE_REG
, pending
);
3072 /* Get number of sent descriptors and decrement counter.
3073 * The number of sent descriptors is returned.
3076 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port
*port
,
3077 struct mvpp2_tx_queue
*txq
)
3081 /* Reading status reg resets transmitted descriptor counter */
3082 val
= mvpp2_read(port
->priv
, MVPP2_TXQ_SENT_REG(txq
->id
));
3084 return (val
& MVPP2_TRANSMITTED_COUNT_MASK
) >>
3085 MVPP2_TRANSMITTED_COUNT_OFFSET
;
3088 static void mvpp2_txq_sent_counter_clear(void *arg
)
3090 struct mvpp2_port
*port
= arg
;
3093 for (queue
= 0; queue
< txq_number
; queue
++) {
3094 int id
= port
->txqs
[queue
]->id
;
3096 mvpp2_read(port
->priv
, MVPP2_TXQ_SENT_REG(id
));
3100 /* Set max sizes for Tx queues */
3101 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port
*port
)
3104 int txq
, tx_port_num
;
3106 mtu
= port
->pkt_size
* 8;
3107 if (mtu
> MVPP2_TXP_MTU_MAX
)
3108 mtu
= MVPP2_TXP_MTU_MAX
;
3110 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
3113 /* Indirect access to registers */
3114 tx_port_num
= mvpp2_egress_port(port
);
3115 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PORT_INDEX_REG
, tx_port_num
);
3118 val
= mvpp2_read(port
->priv
, MVPP2_TXP_SCHED_MTU_REG
);
3119 val
&= ~MVPP2_TXP_MTU_MAX
;
3121 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_MTU_REG
, val
);
3123 /* TXP token size and all TXQs token size must be larger that MTU */
3124 val
= mvpp2_read(port
->priv
, MVPP2_TXP_SCHED_TOKEN_SIZE_REG
);
3125 size
= val
& MVPP2_TXP_TOKEN_SIZE_MAX
;
3128 val
&= ~MVPP2_TXP_TOKEN_SIZE_MAX
;
3130 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_TOKEN_SIZE_REG
, val
);
3133 for (txq
= 0; txq
< txq_number
; txq
++) {
3134 val
= mvpp2_read(port
->priv
,
3135 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq
));
3136 size
= val
& MVPP2_TXQ_TOKEN_SIZE_MAX
;
3140 val
&= ~MVPP2_TXQ_TOKEN_SIZE_MAX
;
3142 mvpp2_write(port
->priv
,
3143 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq
),
3149 /* Free Tx queue skbuffs */
3150 static void mvpp2_txq_bufs_free(struct mvpp2_port
*port
,
3151 struct mvpp2_tx_queue
*txq
,
3152 struct mvpp2_txq_pcpu
*txq_pcpu
, int num
)
3156 for (i
= 0; i
< num
; i
++)
3157 mvpp2_txq_inc_get(txq_pcpu
);
3160 static inline struct mvpp2_rx_queue
*mvpp2_get_rx_queue(struct mvpp2_port
*port
,
3163 int queue
= fls(cause
) - 1;
3165 return port
->rxqs
[queue
];
3168 static inline struct mvpp2_tx_queue
*mvpp2_get_tx_queue(struct mvpp2_port
*port
,
3171 int queue
= fls(cause
) - 1;
3173 return port
->txqs
[queue
];
3176 /* Rx/Tx queue initialization/cleanup methods */
3178 /* Allocate and initialize descriptors for aggr TXQ */
3179 static int mvpp2_aggr_txq_init(struct udevice
*dev
,
3180 struct mvpp2_tx_queue
*aggr_txq
,
3181 int desc_num
, int cpu
,
3186 /* Allocate memory for TX descriptors */
3187 aggr_txq
->descs
= buffer_loc
.aggr_tx_descs
;
3188 aggr_txq
->descs_dma
= (dma_addr_t
)buffer_loc
.aggr_tx_descs
;
3189 if (!aggr_txq
->descs
)
3192 /* Make sure descriptor address is cache line size aligned */
3193 BUG_ON(aggr_txq
->descs
!=
3194 PTR_ALIGN(aggr_txq
->descs
, MVPP2_CPU_D_CACHE_LINE_SIZE
));
3196 aggr_txq
->last_desc
= aggr_txq
->size
- 1;
3198 /* Aggr TXQ no reset WA */
3199 aggr_txq
->next_desc_to_proc
= mvpp2_read(priv
,
3200 MVPP2_AGGR_TXQ_INDEX_REG(cpu
));
3202 /* Set Tx descriptors queue starting address indirect
3205 if (priv
->hw_version
== MVPP21
)
3206 txq_dma
= aggr_txq
->descs_dma
;
3208 txq_dma
= aggr_txq
->descs_dma
>>
3209 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS
;
3211 mvpp2_write(priv
, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu
), txq_dma
);
3212 mvpp2_write(priv
, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu
), desc_num
);
3217 /* Create a specified Rx queue */
3218 static int mvpp2_rxq_init(struct mvpp2_port
*port
,
3219 struct mvpp2_rx_queue
*rxq
)
3224 rxq
->size
= port
->rx_ring_size
;
3226 /* Allocate memory for RX descriptors */
3227 rxq
->descs
= buffer_loc
.rx_descs
;
3228 rxq
->descs_dma
= (dma_addr_t
)buffer_loc
.rx_descs
;
3232 BUG_ON(rxq
->descs
!=
3233 PTR_ALIGN(rxq
->descs
, MVPP2_CPU_D_CACHE_LINE_SIZE
));
3235 rxq
->last_desc
= rxq
->size
- 1;
3237 /* Zero occupied and non-occupied counters - direct access */
3238 mvpp2_write(port
->priv
, MVPP2_RXQ_STATUS_REG(rxq
->id
), 0);
3240 /* Set Rx descriptors queue starting address - indirect access */
3241 mvpp2_write(port
->priv
, MVPP2_RXQ_NUM_REG
, rxq
->id
);
3242 if (port
->priv
->hw_version
== MVPP21
)
3243 rxq_dma
= rxq
->descs_dma
;
3245 rxq_dma
= rxq
->descs_dma
>> MVPP22_DESC_ADDR_OFFS
;
3246 mvpp2_write(port
->priv
, MVPP2_RXQ_DESC_ADDR_REG
, rxq_dma
);
3247 mvpp2_write(port
->priv
, MVPP2_RXQ_DESC_SIZE_REG
, rxq
->size
);
3248 mvpp2_write(port
->priv
, MVPP2_RXQ_INDEX_REG
, 0);
3251 mvpp2_rxq_offset_set(port
, rxq
->id
, NET_SKB_PAD
);
3253 /* Add number of descriptors ready for receiving packets */
3254 mvpp2_rxq_status_update(port
, rxq
->id
, 0, rxq
->size
);
3259 /* Push packets received by the RXQ to BM pool */
3260 static void mvpp2_rxq_drop_pkts(struct mvpp2_port
*port
,
3261 struct mvpp2_rx_queue
*rxq
)
3265 rx_received
= mvpp2_rxq_received(port
, rxq
->id
);
3269 for (i
= 0; i
< rx_received
; i
++) {
3270 struct mvpp2_rx_desc
*rx_desc
= mvpp2_rxq_next_desc_get(rxq
);
3271 u32 bm
= mvpp2_bm_cookie_build(port
, rx_desc
);
3273 mvpp2_pool_refill(port
, bm
,
3274 mvpp2_rxdesc_dma_addr_get(port
, rx_desc
),
3275 mvpp2_rxdesc_cookie_get(port
, rx_desc
));
3277 mvpp2_rxq_status_update(port
, rxq
->id
, rx_received
, rx_received
);
3280 /* Cleanup Rx queue */
3281 static void mvpp2_rxq_deinit(struct mvpp2_port
*port
,
3282 struct mvpp2_rx_queue
*rxq
)
3284 mvpp2_rxq_drop_pkts(port
, rxq
);
3288 rxq
->next_desc_to_proc
= 0;
3291 /* Clear Rx descriptors queue starting address and size;
3292 * free descriptor number
3294 mvpp2_write(port
->priv
, MVPP2_RXQ_STATUS_REG(rxq
->id
), 0);
3295 mvpp2_write(port
->priv
, MVPP2_RXQ_NUM_REG
, rxq
->id
);
3296 mvpp2_write(port
->priv
, MVPP2_RXQ_DESC_ADDR_REG
, 0);
3297 mvpp2_write(port
->priv
, MVPP2_RXQ_DESC_SIZE_REG
, 0);
3300 /* Create and initialize a Tx queue */
3301 static int mvpp2_txq_init(struct mvpp2_port
*port
,
3302 struct mvpp2_tx_queue
*txq
)
3305 int cpu
, desc
, desc_per_txq
, tx_port_num
;
3306 struct mvpp2_txq_pcpu
*txq_pcpu
;
3308 txq
->size
= port
->tx_ring_size
;
3310 /* Allocate memory for Tx descriptors */
3311 txq
->descs
= buffer_loc
.tx_descs
;
3312 txq
->descs_dma
= (dma_addr_t
)buffer_loc
.tx_descs
;
3316 /* Make sure descriptor address is cache line size aligned */
3317 BUG_ON(txq
->descs
!=
3318 PTR_ALIGN(txq
->descs
, MVPP2_CPU_D_CACHE_LINE_SIZE
));
3320 txq
->last_desc
= txq
->size
- 1;
3322 /* Set Tx descriptors queue starting address - indirect access */
3323 mvpp2_write(port
->priv
, MVPP2_TXQ_NUM_REG
, txq
->id
);
3324 mvpp2_write(port
->priv
, MVPP2_TXQ_DESC_ADDR_REG
, txq
->descs_dma
);
3325 mvpp2_write(port
->priv
, MVPP2_TXQ_DESC_SIZE_REG
, txq
->size
&
3326 MVPP2_TXQ_DESC_SIZE_MASK
);
3327 mvpp2_write(port
->priv
, MVPP2_TXQ_INDEX_REG
, 0);
3328 mvpp2_write(port
->priv
, MVPP2_TXQ_RSVD_CLR_REG
,
3329 txq
->id
<< MVPP2_TXQ_RSVD_CLR_OFFSET
);
3330 val
= mvpp2_read(port
->priv
, MVPP2_TXQ_PENDING_REG
);
3331 val
&= ~MVPP2_TXQ_PENDING_MASK
;
3332 mvpp2_write(port
->priv
, MVPP2_TXQ_PENDING_REG
, val
);
3334 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
3335 * for each existing TXQ.
3336 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
3337 * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
3340 desc
= (port
->id
* MVPP2_MAX_TXQ
* desc_per_txq
) +
3341 (txq
->log_id
* desc_per_txq
);
3343 mvpp2_write(port
->priv
, MVPP2_TXQ_PREF_BUF_REG
,
3344 MVPP2_PREF_BUF_PTR(desc
) | MVPP2_PREF_BUF_SIZE_16
|
3345 MVPP2_PREF_BUF_THRESH(desc_per_txq
/ 2));
3347 /* WRR / EJP configuration - indirect access */
3348 tx_port_num
= mvpp2_egress_port(port
);
3349 mvpp2_write(port
->priv
, MVPP2_TXP_SCHED_PORT_INDEX_REG
, tx_port_num
);
3351 val
= mvpp2_read(port
->priv
, MVPP2_TXQ_SCHED_REFILL_REG(txq
->log_id
));
3352 val
&= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK
;
3353 val
|= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
3354 val
|= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK
;
3355 mvpp2_write(port
->priv
, MVPP2_TXQ_SCHED_REFILL_REG(txq
->log_id
), val
);
3357 val
= MVPP2_TXQ_TOKEN_SIZE_MAX
;
3358 mvpp2_write(port
->priv
, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq
->log_id
),
3361 for_each_present_cpu(cpu
) {
3362 txq_pcpu
= per_cpu_ptr(txq
->pcpu
, cpu
);
3363 txq_pcpu
->size
= txq
->size
;
3369 /* Free allocated TXQ resources */
3370 static void mvpp2_txq_deinit(struct mvpp2_port
*port
,
3371 struct mvpp2_tx_queue
*txq
)
3375 txq
->next_desc_to_proc
= 0;
3378 /* Set minimum bandwidth for disabled TXQs */
3379 mvpp2_write(port
->priv
, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq
->id
), 0);
3381 /* Set Tx descriptors queue starting address and size */
3382 mvpp2_write(port
->priv
, MVPP2_TXQ_NUM_REG
, txq
->id
);
3383 mvpp2_write(port
->priv
, MVPP2_TXQ_DESC_ADDR_REG
, 0);
3384 mvpp2_write(port
->priv
, MVPP2_TXQ_DESC_SIZE_REG
, 0);
3387 /* Cleanup Tx ports */
3388 static void mvpp2_txq_clean(struct mvpp2_port
*port
, struct mvpp2_tx_queue
*txq
)
3390 struct mvpp2_txq_pcpu
*txq_pcpu
;
3391 int delay
, pending
, cpu
;
3394 mvpp2_write(port
->priv
, MVPP2_TXQ_NUM_REG
, txq
->id
);
3395 val
= mvpp2_read(port
->priv
, MVPP2_TXQ_PREF_BUF_REG
);
3396 val
|= MVPP2_TXQ_DRAIN_EN_MASK
;
3397 mvpp2_write(port
->priv
, MVPP2_TXQ_PREF_BUF_REG
, val
);
3399 /* The napi queue has been stopped so wait for all packets
3400 * to be transmitted.
3404 if (delay
>= MVPP2_TX_PENDING_TIMEOUT_MSEC
) {
3405 netdev_warn(port
->dev
,
3406 "port %d: cleaning queue %d timed out\n",
3407 port
->id
, txq
->log_id
);
3413 pending
= mvpp2_txq_pend_desc_num_get(port
, txq
);
3416 val
&= ~MVPP2_TXQ_DRAIN_EN_MASK
;
3417 mvpp2_write(port
->priv
, MVPP2_TXQ_PREF_BUF_REG
, val
);
3419 for_each_present_cpu(cpu
) {
3420 txq_pcpu
= per_cpu_ptr(txq
->pcpu
, cpu
);
3422 /* Release all packets */
3423 mvpp2_txq_bufs_free(port
, txq
, txq_pcpu
, txq_pcpu
->count
);
3426 txq_pcpu
->count
= 0;
3427 txq_pcpu
->txq_put_index
= 0;
3428 txq_pcpu
->txq_get_index
= 0;
3432 /* Cleanup all Tx queues */
3433 static void mvpp2_cleanup_txqs(struct mvpp2_port
*port
)
3435 struct mvpp2_tx_queue
*txq
;
3439 val
= mvpp2_read(port
->priv
, MVPP2_TX_PORT_FLUSH_REG
);
3441 /* Reset Tx ports and delete Tx queues */
3442 val
|= MVPP2_TX_PORT_FLUSH_MASK(port
->id
);
3443 mvpp2_write(port
->priv
, MVPP2_TX_PORT_FLUSH_REG
, val
);
3445 for (queue
= 0; queue
< txq_number
; queue
++) {
3446 txq
= port
->txqs
[queue
];
3447 mvpp2_txq_clean(port
, txq
);
3448 mvpp2_txq_deinit(port
, txq
);
3451 mvpp2_txq_sent_counter_clear(port
);
3453 val
&= ~MVPP2_TX_PORT_FLUSH_MASK(port
->id
);
3454 mvpp2_write(port
->priv
, MVPP2_TX_PORT_FLUSH_REG
, val
);
3457 /* Cleanup all Rx queues */
3458 static void mvpp2_cleanup_rxqs(struct mvpp2_port
*port
)
3462 for (queue
= 0; queue
< rxq_number
; queue
++)
3463 mvpp2_rxq_deinit(port
, port
->rxqs
[queue
]);
3466 /* Init all Rx queues for port */
3467 static int mvpp2_setup_rxqs(struct mvpp2_port
*port
)
3471 for (queue
= 0; queue
< rxq_number
; queue
++) {
3472 err
= mvpp2_rxq_init(port
, port
->rxqs
[queue
]);
3479 mvpp2_cleanup_rxqs(port
);
3483 /* Init all tx queues for port */
3484 static int mvpp2_setup_txqs(struct mvpp2_port
*port
)
3486 struct mvpp2_tx_queue
*txq
;
3489 for (queue
= 0; queue
< txq_number
; queue
++) {
3490 txq
= port
->txqs
[queue
];
3491 err
= mvpp2_txq_init(port
, txq
);
3496 mvpp2_txq_sent_counter_clear(port
);
3500 mvpp2_cleanup_txqs(port
);
3505 static void mvpp2_link_event(struct mvpp2_port
*port
)
3507 struct phy_device
*phydev
= port
->phy_dev
;
3508 int status_change
= 0;
3512 if ((port
->speed
!= phydev
->speed
) ||
3513 (port
->duplex
!= phydev
->duplex
)) {
3516 val
= readl(port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
3517 val
&= ~(MVPP2_GMAC_CONFIG_MII_SPEED
|
3518 MVPP2_GMAC_CONFIG_GMII_SPEED
|
3519 MVPP2_GMAC_CONFIG_FULL_DUPLEX
|
3520 MVPP2_GMAC_AN_SPEED_EN
|
3521 MVPP2_GMAC_AN_DUPLEX_EN
);
3524 val
|= MVPP2_GMAC_CONFIG_FULL_DUPLEX
;
3526 if (phydev
->speed
== SPEED_1000
)
3527 val
|= MVPP2_GMAC_CONFIG_GMII_SPEED
;
3528 else if (phydev
->speed
== SPEED_100
)
3529 val
|= MVPP2_GMAC_CONFIG_MII_SPEED
;
3531 writel(val
, port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
3533 port
->duplex
= phydev
->duplex
;
3534 port
->speed
= phydev
->speed
;
3538 if (phydev
->link
!= port
->link
) {
3539 if (!phydev
->link
) {
3544 port
->link
= phydev
->link
;
3548 if (status_change
) {
3550 val
= readl(port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
3551 val
|= (MVPP2_GMAC_FORCE_LINK_PASS
|
3552 MVPP2_GMAC_FORCE_LINK_DOWN
);
3553 writel(val
, port
->base
+ MVPP2_GMAC_AUTONEG_CONFIG
);
3554 mvpp2_egress_enable(port
);
3555 mvpp2_ingress_enable(port
);
3557 mvpp2_ingress_disable(port
);
3558 mvpp2_egress_disable(port
);
3563 /* Main RX/TX processing routines */
3565 /* Display more error info */
3566 static void mvpp2_rx_error(struct mvpp2_port
*port
,
3567 struct mvpp2_rx_desc
*rx_desc
)
3569 u32 status
= mvpp2_rxdesc_status_get(port
, rx_desc
);
3570 size_t sz
= mvpp2_rxdesc_size_get(port
, rx_desc
);
3572 switch (status
& MVPP2_RXD_ERR_CODE_MASK
) {
3573 case MVPP2_RXD_ERR_CRC
:
3574 netdev_err(port
->dev
, "bad rx status %08x (crc error), size=%zu\n",
3577 case MVPP2_RXD_ERR_OVERRUN
:
3578 netdev_err(port
->dev
, "bad rx status %08x (overrun error), size=%zu\n",
3581 case MVPP2_RXD_ERR_RESOURCE
:
3582 netdev_err(port
->dev
, "bad rx status %08x (resource error), size=%zu\n",
3588 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
3589 static int mvpp2_rx_refill(struct mvpp2_port
*port
,
3590 struct mvpp2_bm_pool
*bm_pool
,
3591 u32 bm
, dma_addr_t dma_addr
)
3593 mvpp2_pool_refill(port
, bm
, dma_addr
, (unsigned long)dma_addr
);
3597 /* Set hw internals when starting port */
3598 static void mvpp2_start_dev(struct mvpp2_port
*port
)
3600 mvpp2_gmac_max_rx_size_set(port
);
3601 mvpp2_txp_max_tx_size_set(port
);
3603 mvpp2_port_enable(port
);
3606 /* Set hw internals when stopping port */
3607 static void mvpp2_stop_dev(struct mvpp2_port
*port
)
3609 /* Stop new packets from arriving to RXQs */
3610 mvpp2_ingress_disable(port
);
3612 mvpp2_egress_disable(port
);
3613 mvpp2_port_disable(port
);
3616 static int mvpp2_phy_connect(struct udevice
*dev
, struct mvpp2_port
*port
)
3618 struct phy_device
*phy_dev
;
3620 if (!port
->init
|| port
->link
== 0) {
3621 phy_dev
= phy_connect(port
->priv
->bus
, port
->phyaddr
, dev
,
3622 port
->phy_interface
);
3623 port
->phy_dev
= phy_dev
;
3625 netdev_err(port
->dev
, "cannot connect to phy\n");
3628 phy_dev
->supported
&= PHY_GBIT_FEATURES
;
3629 phy_dev
->advertising
= phy_dev
->supported
;
3631 port
->phy_dev
= phy_dev
;
3636 phy_config(phy_dev
);
3637 phy_startup(phy_dev
);
3638 if (!phy_dev
->link
) {
3639 printf("%s: No link\n", phy_dev
->dev
->name
);
3645 mvpp2_egress_enable(port
);
3646 mvpp2_ingress_enable(port
);
3652 static int mvpp2_open(struct udevice
*dev
, struct mvpp2_port
*port
)
3654 unsigned char mac_bcast
[ETH_ALEN
] = {
3655 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3658 err
= mvpp2_prs_mac_da_accept(port
->priv
, port
->id
, mac_bcast
, true);
3660 netdev_err(dev
, "mvpp2_prs_mac_da_accept BC failed\n");
3663 err
= mvpp2_prs_mac_da_accept(port
->priv
, port
->id
,
3664 port
->dev_addr
, true);
3666 netdev_err(dev
, "mvpp2_prs_mac_da_accept MC failed\n");
3669 err
= mvpp2_prs_def_flow(port
);
3671 netdev_err(dev
, "mvpp2_prs_def_flow failed\n");
3675 /* Allocate the Rx/Tx queues */
3676 err
= mvpp2_setup_rxqs(port
);
3678 netdev_err(port
->dev
, "cannot allocate Rx queues\n");
3682 err
= mvpp2_setup_txqs(port
);
3684 netdev_err(port
->dev
, "cannot allocate Tx queues\n");
3688 err
= mvpp2_phy_connect(dev
, port
);
3692 mvpp2_link_event(port
);
3694 mvpp2_start_dev(port
);
3699 /* No Device ops here in U-Boot */
3701 /* Driver initialization */
3703 static void mvpp2_port_power_up(struct mvpp2_port
*port
)
3705 struct mvpp2
*priv
= port
->priv
;
3707 mvpp2_port_mii_set(port
);
3708 mvpp2_port_periodic_xon_disable(port
);
3709 if (priv
->hw_version
== MVPP21
)
3710 mvpp2_port_fc_adv_enable(port
);
3711 mvpp2_port_reset(port
);
3714 /* Initialize port HW */
3715 static int mvpp2_port_init(struct udevice
*dev
, struct mvpp2_port
*port
)
3717 struct mvpp2
*priv
= port
->priv
;
3718 struct mvpp2_txq_pcpu
*txq_pcpu
;
3719 int queue
, cpu
, err
;
3721 if (port
->first_rxq
+ rxq_number
>
3722 MVPP2_MAX_PORTS
* priv
->max_port_rxqs
)
3726 mvpp2_egress_disable(port
);
3727 mvpp2_port_disable(port
);
3729 port
->txqs
= devm_kcalloc(dev
, txq_number
, sizeof(*port
->txqs
),
3734 /* Associate physical Tx queues to this port and initialize.
3735 * The mapping is predefined.
3737 for (queue
= 0; queue
< txq_number
; queue
++) {
3738 int queue_phy_id
= mvpp2_txq_phys(port
->id
, queue
);
3739 struct mvpp2_tx_queue
*txq
;
3741 txq
= devm_kzalloc(dev
, sizeof(*txq
), GFP_KERNEL
);
3745 txq
->pcpu
= devm_kzalloc(dev
, sizeof(struct mvpp2_txq_pcpu
),
3750 txq
->id
= queue_phy_id
;
3751 txq
->log_id
= queue
;
3752 txq
->done_pkts_coal
= MVPP2_TXDONE_COAL_PKTS_THRESH
;
3753 for_each_present_cpu(cpu
) {
3754 txq_pcpu
= per_cpu_ptr(txq
->pcpu
, cpu
);
3755 txq_pcpu
->cpu
= cpu
;
3758 port
->txqs
[queue
] = txq
;
3761 port
->rxqs
= devm_kcalloc(dev
, rxq_number
, sizeof(*port
->rxqs
),
3766 /* Allocate and initialize Rx queue for this port */
3767 for (queue
= 0; queue
< rxq_number
; queue
++) {
3768 struct mvpp2_rx_queue
*rxq
;
3770 /* Map physical Rx queue to port's logical Rx queue */
3771 rxq
= devm_kzalloc(dev
, sizeof(*rxq
), GFP_KERNEL
);
3774 /* Map this Rx queue to a physical queue */
3775 rxq
->id
= port
->first_rxq
+ queue
;
3776 rxq
->port
= port
->id
;
3777 rxq
->logic_rxq
= queue
;
3779 port
->rxqs
[queue
] = rxq
;
3782 /* Configure Rx queue group interrupt for this port */
3783 if (priv
->hw_version
== MVPP21
) {
3784 mvpp2_write(priv
, MVPP21_ISR_RXQ_GROUP_REG(port
->id
),
3789 val
= (port
->id
<< MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET
);
3790 mvpp2_write(priv
, MVPP22_ISR_RXQ_GROUP_INDEX_REG
, val
);
3792 val
= (CONFIG_MV_ETH_RXQ
<<
3793 MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET
);
3794 mvpp2_write(priv
, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG
, val
);
3797 /* Create Rx descriptor rings */
3798 for (queue
= 0; queue
< rxq_number
; queue
++) {
3799 struct mvpp2_rx_queue
*rxq
= port
->rxqs
[queue
];
3801 rxq
->size
= port
->rx_ring_size
;
3802 rxq
->pkts_coal
= MVPP2_RX_COAL_PKTS
;
3803 rxq
->time_coal
= MVPP2_RX_COAL_USEC
;
3806 mvpp2_ingress_disable(port
);
3808 /* Port default configuration */
3809 mvpp2_defaults_set(port
);
3811 /* Port's classifier configuration */
3812 mvpp2_cls_oversize_rxq_set(port
);
3813 mvpp2_cls_port_config(port
);
3815 /* Provide an initial Rx packet size */
3816 port
->pkt_size
= MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN
);
3818 /* Initialize pools for swf */
3819 err
= mvpp2_swf_bm_pool_init(port
);
3826 /* Ports initialization */
3827 static int mvpp2_port_probe(struct udevice
*dev
,
3828 struct mvpp2_port
*port
,
3835 const char *phy_mode_str
;
3837 int priv_common_regs_num
= 2;
3840 phy_node
= fdtdec_lookup_phandle(gd
->fdt_blob
, port_node
, "phy");
3842 dev_err(&pdev
->dev
, "missing phy\n");
3846 phy_mode_str
= fdt_getprop(gd
->fdt_blob
, port_node
, "phy-mode", NULL
);
3848 phy_mode
= phy_get_interface_by_name(phy_mode_str
);
3849 if (phy_mode
== -1) {
3850 dev_err(&pdev
->dev
, "incorrect phy mode\n");
3854 id
= fdtdec_get_int(gd
->fdt_blob
, port_node
, "port-id", -1);
3856 dev_err(&pdev
->dev
, "missing port-id value\n");
3860 phyaddr
= fdtdec_get_int(gd
->fdt_blob
, phy_node
, "reg", 0);
3864 if (priv
->hw_version
== MVPP21
)
3865 port
->first_rxq
= port
->id
* rxq_number
;
3867 port
->first_rxq
= port
->id
* priv
->max_port_rxqs
;
3868 port
->phy_node
= phy_node
;
3869 port
->phy_interface
= phy_mode
;
3870 port
->phyaddr
= phyaddr
;
3872 if (priv
->hw_version
== MVPP21
) {
3873 port
->base
= (void __iomem
*)dev_get_addr_index(
3874 dev
->parent
, priv_common_regs_num
+ id
);
3875 if (IS_ERR(port
->base
))
3876 return PTR_ERR(port
->base
);
3880 gop_id
= fdtdec_get_int(gd
->fdt_blob
, port_node
,
3883 dev_err(&pdev
->dev
, "missing gop-port-id value\n");
3887 port
->base
= priv
->iface_base
+ MVPP22_PORT_BASE
+
3888 gop_id
* MVPP22_PORT_OFFSET
;
3891 port
->tx_ring_size
= MVPP2_MAX_TXD
;
3892 port
->rx_ring_size
= MVPP2_MAX_RXD
;
3894 err
= mvpp2_port_init(dev
, port
);
3896 dev_err(&pdev
->dev
, "failed to init port %d\n", id
);
3899 mvpp2_port_power_up(port
);
3901 priv
->port_list
[id
] = port
;
3905 /* Initialize decoding windows */
3906 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info
*dram
,
3912 for (i
= 0; i
< 6; i
++) {
3913 mvpp2_write(priv
, MVPP2_WIN_BASE(i
), 0);
3914 mvpp2_write(priv
, MVPP2_WIN_SIZE(i
), 0);
3917 mvpp2_write(priv
, MVPP2_WIN_REMAP(i
), 0);
3922 for (i
= 0; i
< dram
->num_cs
; i
++) {
3923 const struct mbus_dram_window
*cs
= dram
->cs
+ i
;
3925 mvpp2_write(priv
, MVPP2_WIN_BASE(i
),
3926 (cs
->base
& 0xffff0000) | (cs
->mbus_attr
<< 8) |
3927 dram
->mbus_dram_target_id
);
3929 mvpp2_write(priv
, MVPP2_WIN_SIZE(i
),
3930 (cs
->size
- 1) & 0xffff0000);
3932 win_enable
|= (1 << i
);
3935 mvpp2_write(priv
, MVPP2_BASE_ADDR_ENABLE
, win_enable
);
3938 /* Initialize Rx FIFO's */
3939 static void mvpp2_rx_fifo_init(struct mvpp2
*priv
)
3943 for (port
= 0; port
< MVPP2_MAX_PORTS
; port
++) {
3944 if (priv
->hw_version
== MVPP22
) {
3947 MVPP2_RX_DATA_FIFO_SIZE_REG(port
),
3948 MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE
);
3950 MVPP2_RX_ATTR_FIFO_SIZE_REG(port
),
3951 MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE
);
3952 } else if (port
== 1) {
3954 MVPP2_RX_DATA_FIFO_SIZE_REG(port
),
3955 MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE
);
3957 MVPP2_RX_ATTR_FIFO_SIZE_REG(port
),
3958 MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE
);
3961 MVPP2_RX_DATA_FIFO_SIZE_REG(port
),
3962 MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE
);
3964 MVPP2_RX_ATTR_FIFO_SIZE_REG(port
),
3965 MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE
);
3968 mvpp2_write(priv
, MVPP2_RX_DATA_FIFO_SIZE_REG(port
),
3969 MVPP21_RX_FIFO_PORT_DATA_SIZE
);
3970 mvpp2_write(priv
, MVPP2_RX_ATTR_FIFO_SIZE_REG(port
),
3971 MVPP21_RX_FIFO_PORT_ATTR_SIZE
);
3975 mvpp2_write(priv
, MVPP2_RX_MIN_PKT_SIZE_REG
,
3976 MVPP2_RX_FIFO_PORT_MIN_PKT
);
3977 mvpp2_write(priv
, MVPP2_RX_FIFO_INIT_REG
, 0x1);
3980 /* Initialize Tx FIFO's */
3981 static void mvpp2_tx_fifo_init(struct mvpp2
*priv
)
3985 for (port
= 0; port
< MVPP2_MAX_PORTS
; port
++) {
3986 /* Port 0 supports 10KB TX FIFO */
3988 val
= MVPP2_TX_FIFO_DATA_SIZE_10KB
&
3989 MVPP22_TX_FIFO_SIZE_MASK
;
3991 val
= MVPP2_TX_FIFO_DATA_SIZE_3KB
&
3992 MVPP22_TX_FIFO_SIZE_MASK
;
3994 mvpp2_write(priv
, MVPP22_TX_FIFO_SIZE_REG(port
), val
);
3998 static void mvpp2_axi_init(struct mvpp2
*priv
)
4000 u32 val
, rdval
, wrval
;
4002 mvpp2_write(priv
, MVPP22_BM_ADDR_HIGH_RLS_REG
, 0x0);
4004 /* AXI Bridge Configuration */
4006 rdval
= MVPP22_AXI_CODE_CACHE_RD_CACHE
4007 << MVPP22_AXI_ATTR_CACHE_OFFS
;
4008 rdval
|= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4009 << MVPP22_AXI_ATTR_DOMAIN_OFFS
;
4011 wrval
= MVPP22_AXI_CODE_CACHE_WR_CACHE
4012 << MVPP22_AXI_ATTR_CACHE_OFFS
;
4013 wrval
|= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4014 << MVPP22_AXI_ATTR_DOMAIN_OFFS
;
4017 mvpp2_write(priv
, MVPP22_AXI_BM_WR_ATTR_REG
, wrval
);
4018 mvpp2_write(priv
, MVPP22_AXI_BM_RD_ATTR_REG
, rdval
);
4021 mvpp2_write(priv
, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG
, rdval
);
4022 mvpp2_write(priv
, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG
, wrval
);
4023 mvpp2_write(priv
, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG
, rdval
);
4024 mvpp2_write(priv
, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG
, wrval
);
4027 mvpp2_write(priv
, MVPP22_AXI_TX_DATA_RD_ATTR_REG
, rdval
);
4028 mvpp2_write(priv
, MVPP22_AXI_RX_DATA_WR_ATTR_REG
, wrval
);
4030 val
= MVPP22_AXI_CODE_CACHE_NON_CACHE
4031 << MVPP22_AXI_CODE_CACHE_OFFS
;
4032 val
|= MVPP22_AXI_CODE_DOMAIN_SYSTEM
4033 << MVPP22_AXI_CODE_DOMAIN_OFFS
;
4034 mvpp2_write(priv
, MVPP22_AXI_RD_NORMAL_CODE_REG
, val
);
4035 mvpp2_write(priv
, MVPP22_AXI_WR_NORMAL_CODE_REG
, val
);
4037 val
= MVPP22_AXI_CODE_CACHE_RD_CACHE
4038 << MVPP22_AXI_CODE_CACHE_OFFS
;
4039 val
|= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4040 << MVPP22_AXI_CODE_DOMAIN_OFFS
;
4042 mvpp2_write(priv
, MVPP22_AXI_RD_SNOOP_CODE_REG
, val
);
4044 val
= MVPP22_AXI_CODE_CACHE_WR_CACHE
4045 << MVPP22_AXI_CODE_CACHE_OFFS
;
4046 val
|= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4047 << MVPP22_AXI_CODE_DOMAIN_OFFS
;
4049 mvpp2_write(priv
, MVPP22_AXI_WR_SNOOP_CODE_REG
, val
);
4052 /* Initialize network controller common part HW */
4053 static int mvpp2_init(struct udevice
*dev
, struct mvpp2
*priv
)
4055 const struct mbus_dram_target_info
*dram_target_info
;
4059 /* Checks for hardware constraints (U-Boot uses only one rxq) */
4060 if ((rxq_number
> priv
->max_port_rxqs
) ||
4061 (txq_number
> MVPP2_MAX_TXQ
)) {
4062 dev_err(&pdev
->dev
, "invalid queue size parameter\n");
4066 /* MBUS windows configuration */
4067 dram_target_info
= mvebu_mbus_dram_info();
4068 if (dram_target_info
)
4069 mvpp2_conf_mbus_windows(dram_target_info
, priv
);
4071 if (priv
->hw_version
== MVPP22
)
4072 mvpp2_axi_init(priv
);
4074 /* Disable HW PHY polling */
4075 if (priv
->hw_version
== MVPP21
) {
4076 val
= readl(priv
->lms_base
+ MVPP2_PHY_AN_CFG0_REG
);
4077 val
|= MVPP2_PHY_AN_STOP_SMI0_MASK
;
4078 writel(val
, priv
->lms_base
+ MVPP2_PHY_AN_CFG0_REG
);
4080 val
= readl(priv
->iface_base
+ MVPP22_SMI_MISC_CFG_REG
);
4081 val
&= ~MVPP22_SMI_POLLING_EN
;
4082 writel(val
, priv
->iface_base
+ MVPP22_SMI_MISC_CFG_REG
);
4085 /* Allocate and initialize aggregated TXQs */
4086 priv
->aggr_txqs
= devm_kcalloc(dev
, num_present_cpus(),
4087 sizeof(struct mvpp2_tx_queue
),
4089 if (!priv
->aggr_txqs
)
4092 for_each_present_cpu(i
) {
4093 priv
->aggr_txqs
[i
].id
= i
;
4094 priv
->aggr_txqs
[i
].size
= MVPP2_AGGR_TXQ_SIZE
;
4095 err
= mvpp2_aggr_txq_init(dev
, &priv
->aggr_txqs
[i
],
4096 MVPP2_AGGR_TXQ_SIZE
, i
, priv
);
4102 mvpp2_rx_fifo_init(priv
);
4105 if (priv
->hw_version
== MVPP22
)
4106 mvpp2_tx_fifo_init(priv
);
4108 /* Reset Rx queue group interrupt configuration */
4109 for (i
= 0; i
< MVPP2_MAX_PORTS
; i
++) {
4110 if (priv
->hw_version
== MVPP21
) {
4111 mvpp2_write(priv
, MVPP21_ISR_RXQ_GROUP_REG(i
),
4117 val
= (i
<< MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET
);
4118 mvpp2_write(priv
, MVPP22_ISR_RXQ_GROUP_INDEX_REG
, val
);
4120 val
= (CONFIG_MV_ETH_RXQ
<<
4121 MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET
);
4123 MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG
, val
);
4127 if (priv
->hw_version
== MVPP21
)
4128 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT
,
4129 priv
->lms_base
+ MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG
);
4131 /* Allow cache snoop when transmiting packets */
4132 mvpp2_write(priv
, MVPP2_TX_SNOOP_REG
, 0x1);
4134 /* Buffer Manager initialization */
4135 err
= mvpp2_bm_init(dev
, priv
);
4139 /* Parser default initialization */
4140 err
= mvpp2_prs_default_init(dev
, priv
);
4144 /* Classifier default initialization */
4145 mvpp2_cls_init(priv
);
4150 /* SMI / MDIO functions */
4152 static int smi_wait_ready(struct mvpp2
*priv
)
4154 u32 timeout
= MVPP2_SMI_TIMEOUT
;
4157 /* wait till the SMI is not busy */
4159 /* read smi register */
4160 smi_reg
= readl(priv
->mdio_base
);
4161 if (timeout
-- == 0) {
4162 printf("Error: SMI busy timeout\n");
4165 } while (smi_reg
& MVPP2_SMI_BUSY
);
4171 * mpp2_mdio_read - miiphy_read callback function.
4173 * Returns 16bit phy register value, or 0xffff on error
4175 static int mpp2_mdio_read(struct mii_dev
*bus
, int addr
, int devad
, int reg
)
4177 struct mvpp2
*priv
= bus
->priv
;
4181 /* check parameters */
4182 if (addr
> MVPP2_PHY_ADDR_MASK
) {
4183 printf("Error: Invalid PHY address %d\n", addr
);
4187 if (reg
> MVPP2_PHY_REG_MASK
) {
4188 printf("Err: Invalid register offset %d\n", reg
);
4192 /* wait till the SMI is not busy */
4193 if (smi_wait_ready(priv
) < 0)
4196 /* fill the phy address and regiser offset and read opcode */
4197 smi_reg
= (addr
<< MVPP2_SMI_DEV_ADDR_OFFS
)
4198 | (reg
<< MVPP2_SMI_REG_ADDR_OFFS
)
4199 | MVPP2_SMI_OPCODE_READ
;
4201 /* write the smi register */
4202 writel(smi_reg
, priv
->mdio_base
);
4204 /* wait till read value is ready */
4205 timeout
= MVPP2_SMI_TIMEOUT
;
4208 /* read smi register */
4209 smi_reg
= readl(priv
->mdio_base
);
4210 if (timeout
-- == 0) {
4211 printf("Err: SMI read ready timeout\n");
4214 } while (!(smi_reg
& MVPP2_SMI_READ_VALID
));
4216 /* Wait for the data to update in the SMI register */
4217 for (timeout
= 0; timeout
< MVPP2_SMI_TIMEOUT
; timeout
++)
4220 return readl(priv
->mdio_base
) & MVPP2_SMI_DATA_MASK
;
4224 * mpp2_mdio_write - miiphy_write callback function.
4226 * Returns 0 if write succeed, -EINVAL on bad parameters
4229 static int mpp2_mdio_write(struct mii_dev
*bus
, int addr
, int devad
, int reg
,
4232 struct mvpp2
*priv
= bus
->priv
;
4235 /* check parameters */
4236 if (addr
> MVPP2_PHY_ADDR_MASK
) {
4237 printf("Error: Invalid PHY address %d\n", addr
);
4241 if (reg
> MVPP2_PHY_REG_MASK
) {
4242 printf("Err: Invalid register offset %d\n", reg
);
4246 /* wait till the SMI is not busy */
4247 if (smi_wait_ready(priv
) < 0)
4250 /* fill the phy addr and reg offset and write opcode and data */
4251 smi_reg
= value
<< MVPP2_SMI_DATA_OFFS
;
4252 smi_reg
|= (addr
<< MVPP2_SMI_DEV_ADDR_OFFS
)
4253 | (reg
<< MVPP2_SMI_REG_ADDR_OFFS
);
4254 smi_reg
&= ~MVPP2_SMI_OPCODE_READ
;
4256 /* write the smi register */
4257 writel(smi_reg
, priv
->mdio_base
);
4262 static int mvpp2_recv(struct udevice
*dev
, int flags
, uchar
**packetp
)
4264 struct mvpp2_port
*port
= dev_get_priv(dev
);
4265 struct mvpp2_rx_desc
*rx_desc
;
4266 struct mvpp2_bm_pool
*bm_pool
;
4267 dma_addr_t dma_addr
;
4269 int pool
, rx_bytes
, err
;
4271 struct mvpp2_rx_queue
*rxq
;
4272 u32 cause_rx_tx
, cause_rx
, cause_misc
;
4275 cause_rx_tx
= mvpp2_read(port
->priv
,
4276 MVPP2_ISR_RX_TX_CAUSE_REG(port
->id
));
4277 cause_rx_tx
&= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK
;
4278 cause_misc
= cause_rx_tx
& MVPP2_CAUSE_MISC_SUM_MASK
;
4279 if (!cause_rx_tx
&& !cause_misc
)
4282 cause_rx
= cause_rx_tx
& MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK
;
4284 /* Process RX packets */
4285 cause_rx
|= port
->pending_cause_rx
;
4286 rxq
= mvpp2_get_rx_queue(port
, cause_rx
);
4288 /* Get number of received packets and clamp the to-do */
4289 rx_received
= mvpp2_rxq_received(port
, rxq
->id
);
4291 /* Return if no packets are received */
4295 rx_desc
= mvpp2_rxq_next_desc_get(rxq
);
4296 rx_status
= mvpp2_rxdesc_status_get(port
, rx_desc
);
4297 rx_bytes
= mvpp2_rxdesc_size_get(port
, rx_desc
);
4298 rx_bytes
-= MVPP2_MH_SIZE
;
4299 dma_addr
= mvpp2_rxdesc_dma_addr_get(port
, rx_desc
);
4301 bm
= mvpp2_bm_cookie_build(port
, rx_desc
);
4302 pool
= mvpp2_bm_cookie_pool_get(bm
);
4303 bm_pool
= &port
->priv
->bm_pools
[pool
];
4305 /* In case of an error, release the requested buffer pointer
4306 * to the Buffer Manager. This request process is controlled
4307 * by the hardware, and the information about the buffer is
4308 * comprised by the RX descriptor.
4310 if (rx_status
& MVPP2_RXD_ERR_SUMMARY
) {
4311 mvpp2_rx_error(port
, rx_desc
);
4312 /* Return the buffer to the pool */
4313 mvpp2_pool_refill(port
, bm
, dma_addr
, dma_addr
);
4317 err
= mvpp2_rx_refill(port
, bm_pool
, bm
, dma_addr
);
4319 netdev_err(port
->dev
, "failed to refill BM pools\n");
4323 /* Update Rx queue management counters */
4325 mvpp2_rxq_status_update(port
, rxq
->id
, 1, 1);
4327 /* give packet to stack - skip on first n bytes */
4328 data
= (u8
*)dma_addr
+ 2 + 32;
4334 * No cache invalidation needed here, since the rx_buffer's are
4335 * located in a uncached memory region
4343 static void mvpp2_txq_drain(struct mvpp2_port
*port
, struct mvpp2_tx_queue
*txq
,
4348 mvpp2_write(port
->priv
, MVPP2_TXQ_NUM_REG
, txq
->id
);
4349 val
= mvpp2_read(port
->priv
, MVPP2_TXQ_PREF_BUF_REG
);
4351 val
|= MVPP2_TXQ_DRAIN_EN_MASK
;
4353 val
&= ~MVPP2_TXQ_DRAIN_EN_MASK
;
4354 mvpp2_write(port
->priv
, MVPP2_TXQ_PREF_BUF_REG
, val
);
4357 static int mvpp2_send(struct udevice
*dev
, void *packet
, int length
)
4359 struct mvpp2_port
*port
= dev_get_priv(dev
);
4360 struct mvpp2_tx_queue
*txq
, *aggr_txq
;
4361 struct mvpp2_tx_desc
*tx_desc
;
4365 txq
= port
->txqs
[0];
4366 aggr_txq
= &port
->priv
->aggr_txqs
[smp_processor_id()];
4368 /* Get a descriptor for the first part of the packet */
4369 tx_desc
= mvpp2_txq_next_desc_get(aggr_txq
);
4370 mvpp2_txdesc_txq_set(port
, tx_desc
, txq
->id
);
4371 mvpp2_txdesc_size_set(port
, tx_desc
, length
);
4372 mvpp2_txdesc_offset_set(port
, tx_desc
,
4373 (dma_addr_t
)packet
& MVPP2_TX_DESC_ALIGN
);
4374 mvpp2_txdesc_dma_addr_set(port
, tx_desc
,
4375 (dma_addr_t
)packet
& ~MVPP2_TX_DESC_ALIGN
);
4376 /* First and Last descriptor */
4377 mvpp2_txdesc_cmd_set(port
, tx_desc
,
4378 MVPP2_TXD_L4_CSUM_NOT
| MVPP2_TXD_IP_CSUM_DISABLE
4379 | MVPP2_TXD_F_DESC
| MVPP2_TXD_L_DESC
);
4382 flush_dcache_range((unsigned long)packet
,
4383 (unsigned long)packet
+ ALIGN(length
, PKTALIGN
));
4385 /* Enable transmit */
4387 mvpp2_aggr_txq_pend_desc_add(port
, 1);
4389 mvpp2_write(port
->priv
, MVPP2_TXQ_NUM_REG
, txq
->id
);
4393 if (timeout
++ > 10000) {
4394 printf("timeout: packet not sent from aggregated to phys TXQ\n");
4397 tx_done
= mvpp2_txq_pend_desc_num_get(port
, txq
);
4400 /* Enable TXQ drain */
4401 mvpp2_txq_drain(port
, txq
, 1);
4405 if (timeout
++ > 10000) {
4406 printf("timeout: packet not sent\n");
4409 tx_done
= mvpp2_txq_sent_desc_proc(port
, txq
);
4412 /* Disable TXQ drain */
4413 mvpp2_txq_drain(port
, txq
, 0);
4418 static int mvpp2_start(struct udevice
*dev
)
4420 struct eth_pdata
*pdata
= dev_get_platdata(dev
);
4421 struct mvpp2_port
*port
= dev_get_priv(dev
);
4423 /* Load current MAC address */
4424 memcpy(port
->dev_addr
, pdata
->enetaddr
, ETH_ALEN
);
4426 /* Reconfigure parser accept the original MAC address */
4427 mvpp2_prs_update_mac_da(port
, port
->dev_addr
);
4429 mvpp2_port_power_up(port
);
4431 mvpp2_open(dev
, port
);
4436 static void mvpp2_stop(struct udevice
*dev
)
4438 struct mvpp2_port
*port
= dev_get_priv(dev
);
4440 mvpp2_stop_dev(port
);
4441 mvpp2_cleanup_rxqs(port
);
4442 mvpp2_cleanup_txqs(port
);
4445 static int mvpp2_base_probe(struct udevice
*dev
)
4447 struct mvpp2
*priv
= dev_get_priv(dev
);
4448 struct mii_dev
*bus
;
4453 /* Save hw-version */
4454 priv
->hw_version
= dev_get_driver_data(dev
);
4457 * U-Boot special buffer handling:
4459 * Allocate buffer area for descs and rx_buffers. This is only
4460 * done once for all interfaces. As only one interface can
4461 * be active. Make this area DMA-safe by disabling the D-cache
4464 /* Align buffer area for descs and rx_buffers to 1MiB */
4465 bd_space
= memalign(1 << MMU_SECTION_SHIFT
, BD_SPACE
);
4466 mmu_set_region_dcache_behaviour((unsigned long)bd_space
,
4467 BD_SPACE
, DCACHE_OFF
);
4469 buffer_loc
.aggr_tx_descs
= (struct mvpp2_tx_desc
*)bd_space
;
4470 size
+= MVPP2_AGGR_TXQ_SIZE
* MVPP2_DESC_ALIGNED_SIZE
;
4472 buffer_loc
.tx_descs
=
4473 (struct mvpp2_tx_desc
*)((unsigned long)bd_space
+ size
);
4474 size
+= MVPP2_MAX_TXD
* MVPP2_DESC_ALIGNED_SIZE
;
4476 buffer_loc
.rx_descs
=
4477 (struct mvpp2_rx_desc
*)((unsigned long)bd_space
+ size
);
4478 size
+= MVPP2_MAX_RXD
* MVPP2_DESC_ALIGNED_SIZE
;
4480 for (i
= 0; i
< MVPP2_BM_POOLS_NUM
; i
++) {
4481 buffer_loc
.bm_pool
[i
] =
4482 (unsigned long *)((unsigned long)bd_space
+ size
);
4483 if (priv
->hw_version
== MVPP21
)
4484 size
+= MVPP2_BM_POOL_SIZE_MAX
* 2 * sizeof(u32
);
4486 size
+= MVPP2_BM_POOL_SIZE_MAX
* 2 * sizeof(u64
);
4489 for (i
= 0; i
< MVPP2_BM_LONG_BUF_NUM
; i
++) {
4490 buffer_loc
.rx_buffer
[i
] =
4491 (unsigned long *)((unsigned long)bd_space
+ size
);
4492 size
+= RX_BUFFER_SIZE
;
4495 /* Clear the complete area so that all descriptors are cleared */
4496 memset(bd_space
, 0, size
);
4498 /* Save base addresses for later use */
4499 priv
->base
= (void *)dev_get_addr_index(dev
, 0);
4500 if (IS_ERR(priv
->base
))
4501 return PTR_ERR(priv
->base
);
4503 if (priv
->hw_version
== MVPP21
) {
4504 priv
->lms_base
= (void *)dev_get_addr_index(dev
, 1);
4505 if (IS_ERR(priv
->lms_base
))
4506 return PTR_ERR(priv
->lms_base
);
4508 priv
->mdio_base
= priv
->lms_base
+ MVPP21_SMI
;
4510 priv
->iface_base
= (void *)dev_get_addr_index(dev
, 1);
4511 if (IS_ERR(priv
->iface_base
))
4512 return PTR_ERR(priv
->iface_base
);
4514 priv
->mdio_base
= priv
->iface_base
+ MVPP22_SMI
;
4517 if (priv
->hw_version
== MVPP21
)
4518 priv
->max_port_rxqs
= 8;
4520 priv
->max_port_rxqs
= 32;
4522 /* Finally create and register the MDIO bus driver */
4525 printf("Failed to allocate MDIO bus\n");
4529 bus
->read
= mpp2_mdio_read
;
4530 bus
->write
= mpp2_mdio_write
;
4531 snprintf(bus
->name
, sizeof(bus
->name
), dev
->name
);
4532 bus
->priv
= (void *)priv
;
4535 return mdio_register(bus
);
4538 static int mvpp2_probe(struct udevice
*dev
)
4540 struct mvpp2_port
*port
= dev_get_priv(dev
);
4541 struct mvpp2
*priv
= dev_get_priv(dev
->parent
);
4544 /* Only call the probe function for the parent once */
4545 if (!priv
->probe_done
) {
4546 err
= mvpp2_base_probe(dev
->parent
);
4547 priv
->probe_done
= 1;
4549 /* Initialize network controller */
4550 err
= mvpp2_init(dev
, priv
);
4552 dev_err(&pdev
->dev
, "failed to initialize controller\n");
4556 return mvpp2_port_probe(dev
, port
, dev_of_offset(dev
), priv
);
4559 static const struct eth_ops mvpp2_ops
= {
4560 .start
= mvpp2_start
,
4566 static struct driver mvpp2_driver
= {
4569 .probe
= mvpp2_probe
,
4571 .priv_auto_alloc_size
= sizeof(struct mvpp2_port
),
4572 .platdata_auto_alloc_size
= sizeof(struct eth_pdata
),
4576 * Use a MISC device to bind the n instances (child nodes) of the
4577 * network base controller in UCLASS_ETH.
4579 static int mvpp2_base_bind(struct udevice
*parent
)
4581 const void *blob
= gd
->fdt_blob
;
4582 int node
= dev_of_offset(parent
);
4583 struct uclass_driver
*drv
;
4584 struct udevice
*dev
;
4585 struct eth_pdata
*plat
;
4591 /* Lookup eth driver */
4592 drv
= lists_uclass_lookup(UCLASS_ETH
);
4594 puts("Cannot find eth driver\n");
4598 base_id_add
= base_id
;
4600 fdt_for_each_subnode(subnode
, blob
, node
) {
4601 /* Increment base_id for all subnodes, also the disabled ones */
4604 /* Skip disabled ports */
4605 if (!fdtdec_get_is_enabled(blob
, subnode
))
4608 plat
= calloc(1, sizeof(*plat
));
4612 id
= fdtdec_get_int(blob
, subnode
, "port-id", -1);
4615 name
= calloc(1, 16);
4616 sprintf(name
, "mvpp2-%d", id
);
4618 /* Create child device UCLASS_ETH and bind it */
4619 device_bind(parent
, &mvpp2_driver
, name
, plat
, subnode
, &dev
);
4620 dev_set_of_offset(dev
, subnode
);
4626 static const struct udevice_id mvpp2_ids
[] = {
4628 .compatible
= "marvell,armada-375-pp2",
4632 .compatible
= "marvell,armada-7k-pp22",
4638 U_BOOT_DRIVER(mvpp2_base
) = {
4639 .name
= "mvpp2_base",
4641 .of_match
= mvpp2_ids
,
4642 .bind
= mvpp2_base_bind
,
4643 .priv_auto_alloc_size
= sizeof(struct mvpp2
),