drivers/net/phy/mv88e61xx.h

   1 /*
   2  * (C) Copyright 2009
   3  * Marvell Semiconductor <www.marvell.com>
   4  * Prafulla Wadaskar <prafulla@marvell.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef _MV88E61XX_H
  10 #define _MV88E61XX_H
  11
  12 #include <miiphy.h>
  13
  14 #define MV88E61XX_CPU_PORT              0x5
  15
  16 #define MV88E61XX_PHY_TIMEOUT           100000
  17
  18 /* port dev-addr (= port + 0x10) */
  19 #define MV88E61XX_PRT_OFST              0x10
  20 /* port registers */
  21 #define MV88E61XX_PCS_CTRL_REG          0x1
  22 #define MV88E61XX_PRT_CTRL_REG          0x4
  23 #define MV88E61XX_PRT_VMAP_REG          0x6
  24 #define MV88E61XX_PRT_VID_REG           0x7
  25 #define MV88E61XX_RGMII_TIMECTRL_REG    0x1A
  26
  27 /* global registers dev-addr */
  28 #define MV88E61XX_GLBREG_DEVADR 0x1B
  29 /* global registers */
  30 #define MV88E61XX_SGSR                  0x00
  31 #define MV88E61XX_SGCR                  0x04
  32
  33 /* global 2 registers dev-addr */
  34 #define MV88E61XX_GLB2REG_DEVADR        0x1C
  35 /* global 2 registers */
  36 #define MV88E61XX_PHY_CMD               0x18
  37 #define MV88E61XX_PHY_DATA              0x19
  38 /* global 2 phy commands */
  39 #define MV88E61XX_PHY_WRITE_CMD         0x9400
  40 #define MV88E61XX_PHY_READ_CMD          0x9800
  41
  42 #define MV88E61XX_BUSY_OFST             15
  43 #define MV88E61XX_MODE_OFST             12
  44 #define MV88E61XX_OP_OFST               10
  45 #define MV88E61XX_ADDR_OFST             5
  46
  47 #ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
  48 static int mv88e61xx_busychk_multic(char *name, u32 devaddr);
  49 static void mv88e61xx_switch_write(char *name, u32 phy_adr,
  50         u32 reg_ofs, u16 data);
  51 static void mv88e61xx_switch_read(char *name, u32 phy_adr,
  52         u32 reg_ofs, u16 *data);
  53 #define wr_switch_reg mv88e61xx_switch_write
  54 #define rd_switch_reg mv88e61xx_switch_read
  55 #else
  56 /* switch appears a s simple PHY and can thus use miiphy */
  57 #define wr_switch_reg miiphy_write
  58 #define rd_switch_reg miiphy_read
  59 #endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
  60
  61 #endif /* _MV88E61XX_H */