drivers/net/sh_eth.h

   1 /*
   2  * sh_eth.h - Driver for Renesas SH7763's gigabit ethernet controler.
   3  *
   4  * Copyright (C) 2008 Renesas Solutions Corp.
   5  * Copyright (c) 2008 Nobuhiro Iwamatsu
   6  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <netdev.h>
  24 #include <asm/types.h>
  25
  26 #define SHETHER_NAME "sh_eth"
  27
  28 /* Malloc returns addresses in the P1 area (cacheable). However we need to
  29    use area P2 (non-cacheable) */
  30 #define ADDR_TO_P2(addr)        ((((int)(addr) & ~0xe0000000) | 0xa0000000))
  31
  32 /* The ethernet controller needs to use physical addresses */
  33 #define ADDR_TO_PHY(addr)       ((int)(addr) & ~0xe0000000)
  34
  35 /* Number of supported ports */
  36 #define MAX_PORT_NUM    2
  37
  38 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx
  39    buffers must be a multiple of 32 bytes */
  40 #define MAX_BUF_SIZE    (48 * 32)
  41
  42 /* The number of tx descriptors must be large enough to point to 5 or more
  43    frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
  44    We use one descriptor per frame */
  45 #define NUM_TX_DESC             8
  46
  47 /* The size of the tx descriptor is determined by how much padding is used.
  48    4, 20, or 52 bytes of padding can be used */
  49 #define TX_DESC_PADDING         4
  50 #define TX_DESC_SIZE            (12 + TX_DESC_PADDING)
  51
  52 /* Tx descriptor. We always use 3 bytes of padding */
  53 struct tx_desc_s {
  54         volatile u32 td0;
  55         u32 td1;
  56         u32 td2;                /* Buffer start */
  57         u32 padding;
  58 };
  59
  60 /* There is no limitation in the number of rx descriptors */
  61 #define NUM_RX_DESC     8
  62
  63 /* The size of the rx descriptor is determined by how much padding is used.
  64    4, 20, or 52 bytes of padding can be used */
  65 #define RX_DESC_PADDING         4
  66 #define RX_DESC_SIZE            (12 + RX_DESC_PADDING)
  67
  68 /* Rx descriptor. We always use 4 bytes of padding */
  69 struct rx_desc_s {
  70         volatile u32 rd0;
  71         volatile u32 rd1;
  72         u32 rd2;                /* Buffer start */
  73         u32 padding;
  74 };
  75
  76 struct sh_eth_info {
  77         struct tx_desc_s *tx_desc_malloc;
  78         struct tx_desc_s *tx_desc_base;
  79         struct tx_desc_s *tx_desc_cur;
  80         struct rx_desc_s *rx_desc_malloc;
  81         struct rx_desc_s *rx_desc_base;
  82         struct rx_desc_s *rx_desc_cur;
  83         u8 *rx_buf_malloc;
  84         u8 *rx_buf_base;
  85         u8 mac_addr[6];
  86         u8 phy_addr;
  87         struct eth_device *dev;
  88 };
  89
  90 struct sh_eth_dev {
  91         int port;
  92         struct sh_eth_info port_info[MAX_PORT_NUM];
  93 };
  94
  95 /* Register Address */
  96 #define BASE_IO_ADDR    0xfee00000
  97
  98 #define EDSR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x0000)
  99
 100 #define TDLAR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x0010)
 101 #define TDFAR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x0014)
 102 #define TDFXR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x0018)
 103 #define TDFFR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x001c)
 104
 105 #define RDLAR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x0030)
 106 #define RDFAR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x0034)
 107 #define RDFXR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x0038)
 108 #define RDFFR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x003c)
 109
 110 #define EDMR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x0400)
 111 #define EDTRR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x0408)
 112 #define EDRRR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x0410)
 113 #define EESR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x0428)
 114 #define EESIPR(port)    (BASE_IO_ADDR + 0x800 * (port) + 0x0430)
 115 #define TRSCER(port)    (BASE_IO_ADDR + 0x800 * (port) + 0x0438)
 116 #define TFTR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x0448)
 117 #define FDR(port)               (BASE_IO_ADDR + 0x800 * (port) + 0x0450)
 118 #define RMCR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x0458)
 119 #define RPADIR(port)    (BASE_IO_ADDR + 0x800 * (port) + 0x0460)
 120 #define FCFTR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x0468)
 121 #define ECMR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x0500)
 122 #define RFLR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x0508)
 123 #define ECSIPR(port)    (BASE_IO_ADDR + 0x800 * (port) + 0x0518)
 124 #define PIR(port)               (BASE_IO_ADDR + 0x800 * (port) + 0x0520)
 125 #define PIPR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x052c)
 126 #define APR(port)               (BASE_IO_ADDR + 0x800 * (port) + 0x0554)
 127 #define MPR(port)               (BASE_IO_ADDR + 0x800 * (port) + 0x0558)
 128 #define TPAUSER(port)   (BASE_IO_ADDR + 0x800 * (port) + 0x0564)
 129 #define GECMR(port)             (BASE_IO_ADDR + 0x800 * (port) + 0x05b0)
 130 #define MALR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x05c8)
 131 #define MAHR(port)              (BASE_IO_ADDR + 0x800 * (port) + 0x05c0)
 132
 133 /*
 134  * Register's bits
 135  * Copy from Linux driver source code
 136  */
 137 #ifdef CONFIG_CPU_SH7763
 138 /* EDSR */
 139 enum EDSR_BIT {
 140         EDSR_ENT = 0x01, EDSR_ENR = 0x02,
 141 };
 142 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
 143 #endif
 144
 145 /* EDMR */
 146 enum DMAC_M_BIT {
 147         EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
 148 #ifdef CONFIG_CPU_SH7763
 149         EDMR_SRST       = 0x03,
 150         EMDR_DESC_R     = 0x30, /* Descriptor reserve size */
 151         EDMR_EL         = 0x40, /* Litte endian */
 152 #else /* CONFIG_CPU_SH7763 */
 153         EDMR_SRST = 0x01,
 154 #endif
 155 };
 156
 157 /* RFLR */
 158 #define RFLR_RFL_MIN    0x05EE  /* Recv Frame length 1518 byte */
 159
 160 /* EDTRR */
 161 enum DMAC_T_BIT {
 162 #ifdef CONFIG_CPU_SH7763
 163         EDTRR_TRNS = 0x03,
 164 #else
 165         EDTRR_TRNS = 0x01,
 166 #endif
 167 };
 168
 169 /* GECMR */
 170 enum GECMR_BIT {
 171         GECMR_1000B = 0x01, GECMR_100B = 0x40, GECMR_10B = 0x00,
 172 };
 173
 174 /* EDRRR*/
 175 enum EDRRR_R_BIT {
 176         EDRRR_R = 0x01,
 177 };
 178
 179 /* TPAUSER */
 180 enum TPAUSER_BIT {
 181         TPAUSER_TPAUSE = 0x0000ffff,
 182         TPAUSER_UNLIMITED = 0,
 183 };
 184
 185 /* BCFR */
 186 enum BCFR_BIT {
 187         BCFR_RPAUSE = 0x0000ffff,
 188         BCFR_UNLIMITED = 0,
 189 };
 190
 191 /* PIR */
 192 enum PIR_BIT {
 193         PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
 194 };
 195
 196 /* PSR */
 197 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
 198
 199 /* EESR */
 200 enum EESR_BIT {
 201 #ifndef CONFIG_CPU_SH7763
 202         EESR_TWB  = 0x40000000,
 203 #else
 204         EESR_TWB  = 0xC0000000,
 205         EESR_TC1  = 0x20000000,
 206         EESR_TUC  = 0x10000000,
 207         EESR_ROC  = 0x80000000,
 208 #endif
 209         EESR_TABT = 0x04000000,
 210         EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
 211 #ifndef CONFIG_CPU_SH7763
 212         EESR_ADE  = 0x00800000,
 213 #endif
 214         EESR_ECI  = 0x00400000,
 215         EESR_FTC  = 0x00200000, EESR_TDE  = 0x00100000,
 216         EESR_TFE  = 0x00080000, EESR_FRC  = 0x00040000,
 217         EESR_RDE  = 0x00020000, EESR_RFE  = 0x00010000,
 218 #ifndef CONFIG_CPU_SH7763
 219         EESR_CND  = 0x00000800,
 220 #endif
 221         EESR_DLC  = 0x00000400,
 222         EESR_CD   = 0x00000200, EESR_RTO  = 0x00000100,
 223         EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
 224         EESR_CELF = 0x00000020, EESR_RRF  = 0x00000010,
 225         rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
 226         EESR_PRE  = 0x00000002, EESR_CERF = 0x00000001,
 227 };
 228
 229
 230 #ifdef CONFIG_CPU_SH7763
 231 # define TX_CHECK (EESR_TC1 | EESR_FTC)
 232 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
 233                 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
 234 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
 235
 236 #else
 237 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
 238 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
 239                 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
 240 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
 241 #endif
 242
 243 /* EESIPR */
 244 enum DMAC_IM_BIT {
 245         DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
 246         DMAC_M_RABT = 0x02000000,
 247         DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
 248         DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
 249         DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
 250         DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
 251         DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
 252         DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
 253         DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
 254         DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
 255         DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
 256         DMAC_M_RINT1 = 0x00000001,
 257 };
 258
 259 /* Receive descriptor bit */
 260 enum RD_STS_BIT {
 261         RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
 262         RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
 263         RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
 264         RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
 265         RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
 266         RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
 267         RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
 268         RD_RFS1 = 0x00000001,
 269 };
 270 #define RDF1ST  RD_RFP1
 271 #define RDFEND  RD_RFP0
 272 #define RD_RFP  (RD_RFP1|RD_RFP0)
 273
 274 /* RDFFR*/
 275 enum RDFFR_BIT {
 276         RDFFR_RDLF = 0x01,
 277 };
 278
 279 /* FCFTR */
 280 enum FCFTR_BIT {
 281         FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
 282         FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
 283         FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
 284 };
 285 #define FIFO_F_D_RFF    (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
 286 #define FIFO_F_D_RFD    (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
 287
 288 /* Transfer descriptor bit */
 289 enum TD_STS_BIT {
 290 #ifdef CONFIG_CPU_SH7763
 291         TD_TACT = 0x80000000,
 292 #else
 293         TD_TACT = 0x7fffffff,
 294 #endif
 295         TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
 296         TD_TFP0 = 0x10000000,
 297 };
 298 #define TDF1ST  TD_TFP1
 299 #define TDFEND  TD_TFP0
 300 #define TD_TFP  (TD_TFP1|TD_TFP0)
 301
 302 /* RMCR */
 303 enum RECV_RST_BIT { RMCR_RST = 0x01, };
 304 /* ECMR */
 305 enum FELIC_MODE_BIT {
 306 #ifdef CONFIG_CPU_SH7763
 307         ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000,
 308         ECMR_RZPF = 0x00100000,
 309 #endif
 310         ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
 311         ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
 312         ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
 313         ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
 314         ECMR_PRM = 0x00000001,
 315 };
 316
 317 #ifdef CONFIG_CPU_SH7763
 318 #define ECMR_CHG_DM     (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \
 319                                                 ECMR_TXF | ECMR_MCT)
 320 #else
 321 #define ECMR_CHG_DM     (ECMR_ZPF | ECMR_PFR ECMR_RXF | ECMR_TXF | ECMR_MCT)
 322 #endif
 323
 324 /* ECSR */
 325 enum ECSR_STATUS_BIT {
 326 #ifndef CONFIG_CPU_SH7763
 327         ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
 328 #endif
 329         ECSR_LCHNG = 0x04,
 330         ECSR_MPD = 0x02, ECSR_ICD = 0x01,
 331 };
 332
 333 #ifdef CONFIG_CPU_SH7763
 334 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
 335 #else
 336 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
 337                         ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
 338 #endif
 339
 340 /* ECSIPR */
 341 enum ECSIPR_STATUS_MASK_BIT {
 342 #ifndef CONFIG_CPU_SH7763
 343         ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
 344 #endif
 345         ECSIPR_LCHNGIP = 0x04,
 346         ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
 347 };
 348
 349 #ifdef CONFIG_CPU_SH7763
 350 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
 351 #else
 352 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
 353                                 ECSIPR_ICDIP | ECSIPR_MPDIP)
 354 #endif
 355
 356 /* APR */
 357 enum APR_BIT {
 358         APR_AP = 0x00000004,
 359 };
 360
 361 /* MPR */
 362 enum MPR_BIT {
 363         MPR_MP = 0x00000006,
 364 };
 365
 366 /* TRSCER */
 367 enum DESC_I_BIT {
 368         DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
 369         DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
 370         DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
 371         DESC_I_RINT1 = 0x0001,
 372 };
 373
 374 /* RPADIR */
 375 enum RPADIR_BIT {
 376         RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
 377         RPADIR_PADR = 0x0003f,
 378 };
 379
 380 #ifdef CONFIG_CPU_SH7763
 381 # define RPADIR_INIT (0x00)
 382 #else
 383 # define RPADIR_INIT (RPADIR_PADS1)
 384 #endif
 385
 386 /* FDR */
 387 enum FIFO_SIZE_BIT {
 388         FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
 389 };
 390
 391 enum PHY_OFFSETS {
 392         PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
 393         PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6,
 394         PHY_16 = 16,
 395 };
 396
 397 /* PHY_CTRL */
 398 enum PHY_CTRL_BIT {
 399         PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000,
 400         PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400,
 401         PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080,
 402 };
 403 #define DM9161_PHY_C_ANEGEN 0   /* auto nego special */
 404
 405 /* PHY_STAT */
 406 enum PHY_STAT_BIT {
 407         PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000,
 408         PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020,
 409         PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004,
 410         PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001,
 411 };
 412
 413 /* PHY_ANA */
 414 enum PHY_ANA_BIT {
 415         PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000,
 416         PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100,
 417         PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020,
 418         PHY_A_SEL = 0x001e,
 419         PHY_A_EXT = 0x0001,
 420 };
 421
 422 /* PHY_ANL */
 423 enum PHY_ANL_BIT {
 424         PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000,
 425         PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100,
 426         PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020,
 427         PHY_L_SEL = 0x001f,
 428 };
 429
 430 /* PHY_ANE */
 431 enum PHY_ANE_BIT {
 432         PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004,
 433         PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001,
 434 };
 435
 436 /* DM9161 */
 437 enum PHY_16_BIT {
 438         PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000,
 439         PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800,
 440         PHY_16_TXselect = 0x0400,
 441         PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100,
 442         PHY_16_Force100LNK = 0x0080,
 443         PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020,
 444         PHY_16_RPDCTR_EN = 0x0010,
 445         PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004,
 446         PHY_16_Sleepmode = 0x0002,
 447         PHY_16_RemoteLoopOut = 0x0001,
 448 };