]>
git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/net/sk98lin/skgeinit.c
1 /******************************************************************************
4 * Project: GEnesis, PCI Gigabit Ethernet Adapter
5 * Version: $Revision: 1.85 $
6 * Date: $Date: 2003/02/05 15:30:33 $
7 * Purpose: Contains functions to initialize the GE HW
9 ******************************************************************************/
11 /******************************************************************************
13 * (C)Copyright 1998-2003 SysKonnect GmbH.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * The information in this file is provided "AS IS" without warranty.
22 ******************************************************************************/
24 /******************************************************************************
28 * $Log: skgeinit.c,v $
29 * Revision 1.85 2003/02/05 15:30:33 rschmidt
30 * Corrected setting of GIHstClkFact (Host Clock Factor) and
31 * GIPollTimerVal (Descr. Poll Timer Init Value) for YUKON.
34 * Revision 1.84 2003/01/28 09:57:25 rschmidt
35 * Added detection of YUKON-Lite Rev. A0 (stored in GIYukonLite).
36 * Disabled Rx GMAC FIFO Flush for YUKON-Lite Rev. A0.
37 * Added support for CLK_RUN (YUKON-Lite).
38 * Added additional check of PME from D3cold for setting GIVauxAvail.
41 * Revision 1.83 2002/12/17 16:15:41 rschmidt
42 * Added default setting of PhyType (Copper) for YUKON.
43 * Added define around check for HW self test results.
46 * Revision 1.82 2002/12/05 13:40:21 rschmidt
47 * Added setting of Rx GMAC FIFO Flush Mask register.
48 * Corrected PhyType with new define SK_PHY_MARV_FIBER when
49 * YUKON Fiber board was found.
52 * Revision 1.81 2002/11/15 12:48:35 rschmidt
53 * Replaced message SKERR_HWI_E018 with SKERR_HWI_E024 for Rx queue error
55 * Added init for pAC->GIni.GIGenesis with SK_FALSE in YUKON-branch.
58 * Revision 1.80 2002/11/12 17:28:30 rschmidt
59 * Initialized GIPciSlot64 and GIPciClock66 in SkGeInit1().
60 * Reduced PCI FIFO watermarks for 32bit/33MHz bus in SkGeInitBmu().
63 * Revision 1.79 2002/10/21 09:31:02 mkarl
64 * Changed SkGeInitAssignRamToQueues(), removed call to
65 * SkGeInitAssignRamToQueues in SkGeInit1 and fixed compiler warning in
68 * Revision 1.78 2002/10/16 15:55:07 mkarl
69 * Fixed a bug in SkGeInitAssignRamToQueues.
71 * Revision 1.77 2002/10/14 15:07:22 rschmidt
72 * Corrected timeout handling for Rx queue in SkGeStopPort() (#10748)
75 * Revision 1.76 2002/10/11 09:24:38 mkarl
76 * Added check for HW self test results.
78 * Revision 1.75 2002/10/09 16:56:44 mkarl
79 * Now call SkGeInitAssignRamToQueues() in Init Level 1 in order to assign
80 * the adapter memory to the queues. This default assignment is not suitable
83 * Revision 1.74 2002/09/12 08:45:06 rwahl
84 * Set defaults for PMSCap, PLinkSpeed & PLinkSpeedCap dependent on PHY.
86 * Revision 1.73 2002/08/16 15:19:45 rschmidt
87 * Corrected check for Tx queues in SkGeCheckQSize().
88 * Added init for new entry GIGenesis and GICopperType
89 * Replaced all if(GIChipId == CHIP_ID_GENESIS) with new entry GIGenesis.
90 * Replaced wrong 1st para pAC with IoC in SK_IN/OUT macros.
92 * Revision 1.72 2002/08/12 13:38:55 rschmidt
93 * Added check if VAUX is available (stored in GIVauxAvail)
94 * Initialized PLinkSpeedCap in Port struct with SK_LSPEED_CAP_1000MBPS
97 * Revision 1.71 2002/08/08 16:32:58 rschmidt
98 * Added check for Tx queues in SkGeCheckQSize().
99 * Added start of Time Stamp Timer (YUKON) in SkGeInit2().
102 * Revision 1.70 2002/07/23 16:04:26 rschmidt
103 * Added init for GIWolOffs (HW-Bug in YUKON 1st rev.)
106 * Revision 1.69 2002/07/17 17:07:08 rwahl
107 * - SkGeInit1(): fixed PHY type debug output; corrected init of GIFunc
109 * - Editorial changes.
111 * Revision 1.68 2002/07/15 18:38:31 rwahl
112 * Added initialization for MAC type dependent function table.
114 * Revision 1.67 2002/07/15 15:45:39 rschmidt
115 * Added Tx Store & Forward for YUKON (GMAC Tx FIFO is only 1 kB)
116 * Replaced SK_PHY_MARV by SK_PHY_MARV_COPPER
119 * Revision 1.66 2002/06/10 09:35:08 rschmidt
120 * Replaced C++ comments (//)
123 * Revision 1.65 2002/06/05 08:33:37 rschmidt
124 * Changed GIRamSize and Reset sequence for YUKON.
125 * SkMacInit() replaced by SkXmInitMac() resp. SkGmInitMac()
127 * Revision 1.64 2002/04/25 13:03:20 rschmidt
128 * Changes for handling YUKON.
129 * Removed reference to xmac_ii.h (not necessary).
130 * Moved all defines into header file.
131 * Replaced all SkXm...() functions with SkMac...() to handle also
133 * Added handling for GMAC FIFO in SkGeInitMacFifo(), SkGeStopPort().
134 * Removed 'goto'-directive from SkGeCfgSync(), SkGeCheckQSize().
135 * Replaced all XMAC-access macros by functions: SkMacRxTxDisable(),
136 * SkMacFlushTxFifo().
137 * Optimized timeout handling in SkGeStopPort().
138 * Initialized PLinkSpeed in Port struct with SK_LSPEED_AUTO.
139 * Release of GMAC Link Control reset in SkGeInit1().
140 * Initialized GIChipId and GIChipRev in GE Init structure.
141 * Added GIRamSize and PhyType values for YUKON.
142 * Removed use of PRxCmd to setup XMAC.
143 * Moved setting of XM_RX_DIS_CEXT to SkXmInitMac().
144 * Use of SkGeXmitLED() only for GENESIS.
145 * Changes for V-CPU support.
148 * Revision 1.63 2001/04/05 11:02:09 rassmann
149 * Stop Port check of the STOP bit did not take 2/18 sec as wanted.
151 * Revision 1.62 2001/02/07 07:54:21 rassmann
152 * Corrected copyright.
154 * Revision 1.61 2001/01/31 15:31:40 gklug
155 * fix: problem with autosensing an SR8800 switch
157 * Revision 1.60 2000/10/18 12:22:21 cgoos
158 * Added workaround for half duplex hangup.
160 * Revision 1.59 2000/10/10 11:22:06 gklug
161 * add: in manual half duplex mode ignore carrier extension errors
163 * Revision 1.58 2000/10/02 14:10:27 rassmann
164 * Reading BCOM PHY after releasing reset until it returns a valid value.
166 * Revision 1.57 2000/08/03 14:55:28 rassmann
167 * Waiting for I2C to be ready before de-initializing adapter
168 * (prevents sensors from hanging up).
170 * Revision 1.56 2000/07/27 12:16:48 gklug
171 * fix: Stop Port check of the STOP bit does now take 2/18 sec as wanted
173 * Revision 1.55 1999/11/22 13:32:26 cgoos
174 * Changed license header to GPL.
176 * Revision 1.54 1999/10/26 07:32:54 malthoff
177 * Initialize PHWLinkUp with SK_FALSE. Required for Diagnostics.
179 * Revision 1.53 1999/08/12 19:13:50 malthoff
180 * Fix for 1000BT. Do not owerwrite XM_MMU_CMD when
181 * disabling receiver and transmitter. Other bits
184 * Revision 1.52 1999/07/01 09:29:54 gklug
185 * fix: DoInitRamQueue needs pAC
187 * Revision 1.51 1999/07/01 08:42:21 gklug
188 * chg: use Store & forward for RAM buffer when Jumbos are used
190 * Revision 1.50 1999/05/27 13:19:38 cgoos
191 * Added Tx PCI watermark initialization.
192 * Removed Tx RAM queue Store & Forward setting.
194 * Revision 1.49 1999/05/20 14:32:45 malthoff
195 * SkGeLinkLED() is completly removed now.
197 * Revision 1.48 1999/05/19 07:28:24 cgoos
198 * SkGeLinkLED no more available for drivers.
199 * Changes for 1000Base-T.
201 * Revision 1.47 1999/04/08 13:57:45 gklug
202 * add: Init of new port struct fiels PLinkResCt
203 * chg: StopPort Timer check
205 * Revision 1.46 1999/03/25 07:42:15 malthoff
206 * SkGeStopPort(): Add workaround for cache incoherency.
207 * Create error log entry, disable port, and
208 * exit loop if it does not terminate.
209 * Add XM_RX_LENERR_OK to the default value for the
210 * XMAC receive command register.
212 * Revision 1.45 1999/03/12 16:24:47 malthoff
213 * Remove PPollRxD and PPollTxD.
214 * Add check for GIPollTimerVal.
216 * Revision 1.44 1999/03/12 13:40:23 malthoff
217 * Fix: SkGeXmitLED(), SK_LED_TST mode does not work.
218 * Add: Jumbo frame support.
219 * Chg: Resolution of parameter IntTime in SkGeCfgSync().
221 * Revision 1.43 1999/02/09 10:29:46 malthoff
222 * Bugfix: The previous modification again also for the second location.
224 * Revision 1.42 1999/02/09 09:35:16 malthoff
225 * Bugfix: The bits '66 MHz Capable' and 'NEWCAP are reset while
226 * clearing the error bits in the PCI status register.
228 * Revision 1.41 1999/01/18 13:07:02 malthoff
229 * Bugfix: Do not use CFG cycles after during Init- or Runtime, because
230 * they may not be available after Boottime.
232 * Revision 1.40 1999/01/11 12:40:49 malthoff
233 * Bug fix: PCI_STATUS: clearing error bits sets the UDF bit.
235 * Revision 1.39 1998/12/11 15:17:33 gklug
236 * chg: Init LipaAutoNeg with Unknown
238 * Revision 1.38 1998/12/10 11:02:57 malthoff
239 * Disable Error Log Message when calling SkGeInit(level 2)
242 * Revision 1.37 1998/12/07 12:18:25 gklug
243 * add: refinement of autosense mode: take into account the autoneg cap of LiPa
245 * Revision 1.36 1998/12/07 07:10:39 gklug
246 * fix: init values of LinkBroken/ Capabilities for management
248 * Revision 1.35 1998/12/02 10:56:20 gklug
249 * fix: do NOT init LoinkSync Counter.
251 * Revision 1.34 1998/12/01 10:53:21 gklug
252 * add: init of additional Counters for workaround
254 * Revision 1.33 1998/12/01 10:00:49 gklug
255 * add: init PIsave var in Port struct
257 * Revision 1.32 1998/11/26 14:50:40 gklug
258 * chg: Default is autosensing with AUTOFULL mode
260 * Revision 1.31 1998/11/25 15:36:16 gklug
261 * fix: do NOT stop LED Timer when port should be stopped
263 * Revision 1.30 1998/11/24 13:15:28 gklug
264 * add: Init PCkeckPar struct member
266 * Revision 1.29 1998/11/18 13:19:27 malthoff
267 * Disable packet arbiter timeouts on receive side.
268 * Use maximum timeout value for packet arbiter
270 * Add TestStopBit() function to handle stop RX/TX
271 * problem with active descriptor poll timers.
272 * Bug Fix: Descriptor Poll Timer not started, because
273 * GIPollTimerVal was initialized with 0.
275 * Revision 1.28 1998/11/13 14:24:26 malthoff
276 * Bug Fix: SkGeStopPort() may hang if a Packet Arbiter Timout
277 * is pending or occurs while waiting for TX_STOP and RX_STOP.
278 * The PA timeout is cleared now while waiting for TX- or RX_STOP.
280 * Revision 1.27 1998/11/02 11:04:36 malthoff
283 * Revision 1.26 1998/11/02 10:37:03 malthoff
284 * Fix: SkGePollTxD() enables always the synchronounous poll timer.
286 * Revision 1.25 1998/10/28 07:12:43 cgoos
287 * Fixed "LED_STOP" in SkGeLnkSyncCnt, "== SK_INIT_IO" in SkGeInit.
288 * Removed: Reset of RAM Interface in SkGeStopPort.
290 * Revision 1.24 1998/10/27 08:13:12 malthoff
291 * Remove temporary code.
293 * Revision 1.23 1998/10/26 07:45:03 malthoff
294 * Add Address Calculation Workaround: If the EPROM byte
295 * Id is 3, the address offset is 512 kB.
296 * Initialize default values for PLinkMode and PFlowCtrlMode.
298 * Revision 1.22 1998/10/22 09:46:47 gklug
299 * fix SysKonnectFileId typo
301 * Revision 1.21 1998/10/20 12:11:56 malthoff
302 * Don't dendy the Queue config if the size of the unused
305 * Revision 1.20 1998/10/19 07:27:58 malthoff
306 * SkGeInitRamIface() is public to be called by diagnostics.
308 * Revision 1.19 1998/10/16 13:33:45 malthoff
309 * Fix: enabling descriptor polling is not allowed until
310 * the descriptor addresses are set. Descriptor polling
311 * must be handled by the driver.
313 * Revision 1.18 1998/10/16 10:58:27 malthoff
314 * Remove temp. code for Diag prototype.
315 * Remove lint warning for dummy reads.
316 * Call SkGeLoadLnkSyncCnt() during SkGeInitPort().
318 * Revision 1.17 1998/10/14 09:16:06 malthoff
319 * Change parameter LimCount and programming of
320 * the limit counter in SkGeCfgSync().
322 * Revision 1.16 1998/10/13 09:21:16 malthoff
323 * Don't set XM_RX_SELF_RX in RxCmd Reg, because it's
324 * like a Loopback Mode in half duplex.
326 * Revision 1.15 1998/10/09 06:47:40 malthoff
327 * SkGeInitMacArb(): set recovery counters init value
328 * to zero although this counters are not uesd.
329 * Bug fix in Rx Upper/Lower Pause Threshold calculation.
330 * Add XM_RX_SELF_RX to RxCmd.
332 * Revision 1.14 1998/10/06 15:15:53 malthoff
333 * Make sure no pending IRQ is cleared in SkGeLoadLnkSyncCnt().
335 * Revision 1.13 1998/10/06 14:09:36 malthoff
336 * Add SkGeLoadLnkSyncCnt(). Modify
337 * the 'port stopped' condition according
338 * to the current problem report.
340 * Revision 1.12 1998/10/05 08:17:21 malthoff
341 * Add functions: SkGePollRxD(), SkGePollTxD(),
342 * DoCalcAddr(), SkGeCheckQSize(),
343 * DoInitRamQueue(), and SkGeCfgSync().
344 * Add coding for SkGeInitMacArb(), SkGeInitPktArb(),
345 * SkGeInitMacFifo(), SkGeInitRamBufs(),
346 * SkGeInitRamIface(), and SkGeInitBmu().
348 * Revision 1.11 1998/09/29 08:26:29 malthoff
349 * bug fix: SkGeInit0() 'i' should be increment.
351 * Revision 1.10 1998/09/28 13:19:01 malthoff
352 * Coding time: Save the done work.
353 * Modify SkGeLinkLED(), add SkGeXmitLED(),
354 * define SkGeCheckQSize(), SkGeInitMacArb(),
355 * SkGeInitPktArb(), SkGeInitMacFifo(),
356 * SkGeInitRamBufs(), SkGeInitRamIface(),
357 * and SkGeInitBmu(). Do coding for SkGeStopPort(),
358 * SkGeInit1(), SkGeInit2(), and SkGeInit3().
359 * Do coding for SkGeDinit() and SkGeInitPort().
361 * Revision 1.9 1998/09/16 14:29:05 malthoff
362 * Some minor changes.
364 * Revision 1.8 1998/09/11 05:29:14 gklug
365 * add: init state of a port
367 * Revision 1.7 1998/09/04 09:26:25 malthoff
368 * Short temporary modification.
370 * Revision 1.6 1998/09/04 08:27:59 malthoff
371 * Remark the do-while in StopPort() because it never ends
372 * without a GE adapter.
374 * Revision 1.5 1998/09/03 14:05:45 malthoff
375 * Change comment for SkGeInitPort(). Do not
376 * repair the queue sizes if invalid.
378 * Revision 1.4 1998/09/03 10:03:19 malthoff
379 * Implement the new interface according to the
380 * reviewed interface specification.
382 * Revision 1.3 1998/08/19 09:11:25 gklug
383 * fix: struct are removed from c-source (see CCC)
385 * Revision 1.2 1998/07/28 12:33:58 malthoff
386 * Add 'IoC' parameter in function declaration and SK IO macros.
388 * Revision 1.1 1998/07/23 09:48:57 malthoff
389 * Creation. First dummy 'C' file.
390 * SkGeInit(Level 0) is card_start for GE.
391 * SkGeDeInit() is card_stop for GE.
394 ******************************************************************************/
398 #include "h/skdrv1st.h"
399 #include "h/skdrv2nd.h"
401 /* global variables ***********************************************************/
403 /* local variables ************************************************************/
405 static const char SysKonnectFileId
[] =
406 "@(#)$Id: skgeinit.c,v 1.85 2003/02/05 15:30:33 rschmidt Exp $ (C) SK ";
409 int RxQOff
; /* Receive Queue Address Offset */
410 int XsQOff
; /* Sync Tx Queue Address Offset */
411 int XaQOff
; /* Async Tx Queue Address Offset */
413 static struct s_QOffTab QOffTab
[] = {
414 {Q_R1
, Q_XS1
, Q_XA1
}, {Q_R2
, Q_XS2
, Q_XA2
}
418 /******************************************************************************
420 * SkGePollRxD() - Enable / Disable Descriptor Polling of RxD Ring
423 * Enable or disable the descriptor polling of the receive descriptor
424 * ring (RxD) for port 'Port'.
425 * The new configuration is *not* saved over any SkGeStopPort() and
426 * SkGeInitPort() calls.
432 SK_AC
*pAC
, /* adapter context */
433 SK_IOC IoC
, /* IO context */
434 int Port
, /* Port Index (MAC_1 + n) */
435 SK_BOOL PollRxD
) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
439 pPrt
= &pAC
->GIni
.GP
[Port
];
441 SK_OUT32(IoC
, Q_ADDR(pPrt
->PRxQOff
, Q_CSR
), (PollRxD
) ?
442 CSR_ENA_POL
: CSR_DIS_POL
);
446 /******************************************************************************
448 * SkGePollTxD() - Enable / Disable Descriptor Polling of TxD Rings
451 * Enable or disable the descriptor polling of the transmit descriptor
452 * ring(s) (TxD) for port 'Port'.
453 * The new configuration is *not* saved over any SkGeStopPort() and
454 * SkGeInitPort() calls.
460 SK_AC
*pAC
, /* adapter context */
461 SK_IOC IoC
, /* IO context */
462 int Port
, /* Port Index (MAC_1 + n) */
463 SK_BOOL PollTxD
) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
468 pPrt
= &pAC
->GIni
.GP
[Port
];
470 DWord
= (PollTxD
) ? CSR_ENA_POL
: CSR_DIS_POL
;
472 if (pPrt
->PXSQSize
!= 0) {
473 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXsQOff
, Q_CSR
), DWord
);
476 if (pPrt
->PXAQSize
!= 0) {
477 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXaQOff
, Q_CSR
), DWord
);
482 /******************************************************************************
484 * SkGeYellowLED() - Switch the yellow LED on or off.
487 * Switch the yellow LED on or off.
490 * This function may be called any time after SkGeInit(Level 1).
496 SK_AC
*pAC
, /* adapter context */
497 SK_IOC IoC
, /* IO context */
498 int State
) /* yellow LED state, 0 = OFF, 0 != ON */
501 /* Switch yellow LED OFF */
502 SK_OUT8(IoC
, B0_LED
, LED_STAT_OFF
);
505 /* Switch yellow LED ON */
506 SK_OUT8(IoC
, B0_LED
, LED_STAT_ON
);
508 } /* SkGeYellowLED */
511 /******************************************************************************
513 * SkGeXmitLED() - Modify the Operational Mode of a transmission LED.
516 * The Rx or Tx LED which is specified by 'Led' will be
517 * enabled, disabled or switched on in test mode.
520 * 'Led' must contain the address offset of the LEDs INI register.
523 * SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA);
529 SK_AC
*pAC
, /* adapter context */
530 SK_IOC IoC
, /* IO context */
531 int Led
, /* offset to the LED Init Value register */
532 int Mode
) /* Mode may be SK_LED_DIS, SK_LED_ENA, SK_LED_TST */
538 LedIni
= SK_XMIT_DUR
* (SK_U32
)pAC
->GIni
.GIHstClkFact
/ 100;
539 SK_OUT32(IoC
, Led
+ XMIT_LED_INI
, LedIni
);
540 SK_OUT8(IoC
, Led
+ XMIT_LED_CTRL
, LED_START
);
543 SK_OUT8(IoC
, Led
+ XMIT_LED_TST
, LED_T_ON
);
544 SK_OUT32(IoC
, Led
+ XMIT_LED_CNT
, 100);
545 SK_OUT8(IoC
, Led
+ XMIT_LED_CTRL
, LED_START
);
550 * Do NOT stop the LED Timer here. The LED might be
551 * in on state. But it needs to go off.
553 SK_OUT32(IoC
, Led
+ XMIT_LED_CNT
, 0);
554 SK_OUT8(IoC
, Led
+ XMIT_LED_TST
, LED_T_OFF
);
559 * 1000BT: The Transmit LED is driven by the PHY.
560 * But the default LED configuration is used for
561 * Level One and Broadcom PHYs.
562 * (Broadcom: It may be that PHY_B_PEC_EN_LTR has to be set.)
563 * (In this case it has to be added here. But we will see. XXX)
568 /******************************************************************************
570 * DoCalcAddr() - Calculates the start and the end address of a queue.
573 * This function calculates the start and the end address of a queue.
574 * Afterwards the 'StartVal' is incremented to the next start position.
575 * If the port is already initialized the calculated values
576 * will be checked against the configured values and an
577 * error will be returned, if they are not equal.
578 * If the port is not initialized the values will be written to
579 * *StartAdr and *EndAddr.
583 * 1: configuration error
585 static int DoCalcAddr(
586 SK_AC
*pAC
, /* adapter context */
587 SK_GEPORT
*pPrt
, /* port index */
588 int QuSize
, /* size of the queue to configure in kB */
589 SK_U32
*StartVal
, /* start value for address calculation */
590 SK_U32
*QuStartAddr
, /* start addr to calculate */
591 SK_U32
*QuEndAddr
) /* end address to calculate */
603 EndVal
= *StartVal
+ ((SK_U32
)QuSize
* 1024) - 1;
604 NextStart
= EndVal
+ 1;
607 if (pPrt
->PState
>= SK_PRT_INIT
) {
608 if (*StartVal
!= *QuStartAddr
|| EndVal
!= *QuEndAddr
) {
613 *QuStartAddr
= *StartVal
;
617 *StartVal
= NextStart
;
621 /******************************************************************************
623 * SkGeInitAssignRamToQueues() - allocate default queue sizes
626 * This function assigns the memory to the different queues and ports.
627 * When DualNet is set to SK_TRUE all ports get the same amount of memory.
628 * Otherwise the first port gets most of the memory and all the
629 * other ports just the required minimum.
630 * This function can only be called when pAC->GIni.GIRamSize and
631 * pAC->GIni.GIMacsFound have been initialized, usually this happens
636 * 1 - invalid input values
637 * 2 - not enough memory
640 int SkGeInitAssignRamToQueues(
641 SK_AC
*pAC
, /* Adapter context */
642 int ActivePort
, /* Active Port in RLMT mode */
643 SK_BOOL DualNet
) /* adapter context */
646 int UsedKilobytes
; /* memory already assigned */
647 int ActivePortKilobytes
; /* memory available for active port */
652 if (ActivePort
>= pAC
->GIni
.GIMacsFound
) {
653 SK_DBG_MSG(pAC
, SK_DBGMOD_HWM
, SK_DBGCAT_INIT
,
654 ("SkGeInitAssignRamToQueues: ActivePort (%d) invalid\n",
658 if (((pAC
->GIni
.GIMacsFound
* (SK_MIN_RXQ_SIZE
+ SK_MIN_TXQ_SIZE
)) +
659 ((RAM_QUOTA_SYNC
== 0) ? 0 : SK_MIN_TXQ_SIZE
)) > pAC
->GIni
.GIRamSize
) {
660 SK_DBG_MSG(pAC
, SK_DBGMOD_HWM
, SK_DBGCAT_INIT
,
661 ("SkGeInitAssignRamToQueues: Not enough memory (%d)\n",
662 pAC
->GIni
.GIRamSize
));
668 /* every port gets the same amount of memory */
669 ActivePortKilobytes
= pAC
->GIni
.GIRamSize
/ pAC
->GIni
.GIMacsFound
;
670 for (i
= 0; i
< pAC
->GIni
.GIMacsFound
; i
++) {
672 pGePort
= &pAC
->GIni
.GP
[i
];
674 /* take away the minimum memory for active queues */
675 ActivePortKilobytes
-= (SK_MIN_RXQ_SIZE
+ SK_MIN_TXQ_SIZE
);
677 /* receive queue gets the minimum + 80% of the rest */
678 pGePort
->PRxQSize
= (int) (ROUND_QUEUE_SIZE_KB((
679 ActivePortKilobytes
* (unsigned long) RAM_QUOTA_RX
) / 100))
682 ActivePortKilobytes
-= (pGePort
->PRxQSize
- SK_MIN_RXQ_SIZE
);
684 /* synchronous transmit queue */
685 pGePort
->PXSQSize
= 0;
687 /* asynchronous transmit queue */
688 pGePort
->PXAQSize
= (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes
+
693 /* Rlmt Mode or single link adapter */
695 /* Set standby queue size defaults for all standby ports */
696 for (i
= 0; i
< pAC
->GIni
.GIMacsFound
; i
++) {
698 if (i
!= ActivePort
) {
699 pGePort
= &pAC
->GIni
.GP
[i
];
701 pGePort
->PRxQSize
= SK_MIN_RXQ_SIZE
;
702 pGePort
->PXAQSize
= SK_MIN_TXQ_SIZE
;
703 pGePort
->PXSQSize
= 0;
706 UsedKilobytes
+= pGePort
->PRxQSize
+ pGePort
->PXAQSize
;
710 ActivePortKilobytes
= pAC
->GIni
.GIRamSize
- UsedKilobytes
;
712 /* assign it to the active port */
713 /* first take away the minimum memory */
714 ActivePortKilobytes
-= (SK_MIN_RXQ_SIZE
+ SK_MIN_TXQ_SIZE
);
715 pGePort
= &pAC
->GIni
.GP
[ActivePort
];
717 /* receive queue get's the minimum + 80% of the rest */
718 pGePort
->PRxQSize
= (int) (ROUND_QUEUE_SIZE_KB((ActivePortKilobytes
*
719 (unsigned long) RAM_QUOTA_RX
) / 100)) + SK_MIN_RXQ_SIZE
;
721 ActivePortKilobytes
-= (pGePort
->PRxQSize
- SK_MIN_RXQ_SIZE
);
723 /* synchronous transmit queue */
724 pGePort
->PXSQSize
= 0;
726 /* asynchronous transmit queue */
727 pGePort
->PXAQSize
= (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes
) +
731 VCPUprintf(0, "PRxQSize=%u, PXSQSize=%u, PXAQSize=%u\n",
732 pGePort
->PRxQSize
, pGePort
->PXSQSize
, pGePort
->PXAQSize
);
736 } /* SkGeInitAssignRamToQueues */
738 /******************************************************************************
740 * SkGeCheckQSize() - Checks the Adapters Queue Size Configuration
743 * This function verifies the Queue Size Configuration specified
744 * in the variables PRxQSize, PXSQSize, and PXAQSize of all
746 * This requirements must be fullfilled to have a valid configuration:
747 * - The size of all queues must not exceed GIRamSize.
748 * - The queue sizes must be specified in units of 8 kB.
749 * - The size of Rx queues of available ports must not be
750 * smaller than 16 kB.
751 * - The size of at least one Tx queue (synch. or asynch.)
752 * of available ports must not be smaller than 16 kB
753 * when Jumbo Frames are used.
754 * - The RAM start and end addresses must not be changed
755 * for ports which are already initialized.
756 * Furthermore SkGeCheckQSize() defines the Start and End Addresses
757 * of all ports and stores them into the HWAC port structure.
760 * 0: Queue Size Configuration valid
761 * 1: Queue Size Configuration invalid
763 static int SkGeCheckQSize(
764 SK_AC
*pAC
, /* adapter context */
765 int Port
) /* port index */
768 int UsedMem
; /* total memory used (max. found ports) */
776 for (i
= 0; i
< pAC
->GIni
.GIMacsFound
; i
++) {
777 pPrt
= &pAC
->GIni
.GP
[i
];
779 if ((pPrt
->PRxQSize
& QZ_UNITS
) != 0 ||
780 (pPrt
->PXSQSize
& QZ_UNITS
) != 0 ||
781 (pPrt
->PXAQSize
& QZ_UNITS
) != 0) {
783 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E012
, SKERR_HWI_E012MSG
);
787 if (i
== Port
&& pPrt
->PRxQSize
< SK_MIN_RXQ_SIZE
) {
788 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E011
, SKERR_HWI_E011MSG
);
793 * the size of at least one Tx queue (synch. or asynch.) has to be > 0.
794 * if Jumbo Frames are used, this size has to be >= 16 kB.
796 if ((i
== Port
&& pPrt
->PXSQSize
== 0 && pPrt
->PXAQSize
== 0) ||
797 (pAC
->GIni
.GIPortUsage
== SK_JUMBO_LINK
&&
798 ((pPrt
->PXSQSize
> 0 && pPrt
->PXSQSize
< SK_MIN_TXQ_SIZE
) ||
799 (pPrt
->PXAQSize
> 0 && pPrt
->PXAQSize
< SK_MIN_TXQ_SIZE
)))) {
800 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E023
, SKERR_HWI_E023MSG
);
804 UsedMem
+= pPrt
->PRxQSize
+ pPrt
->PXSQSize
+ pPrt
->PXAQSize
;
807 if (UsedMem
> pAC
->GIni
.GIRamSize
) {
808 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E012
, SKERR_HWI_E012MSG
);
812 /* Now start address calculation */
813 StartAddr
= pAC
->GIni
.GIRamOffs
;
814 for (i
= 0; i
< pAC
->GIni
.GIMacsFound
; i
++) {
815 pPrt
= &pAC
->GIni
.GP
[i
];
817 /* Calculate/Check values for the receive queue */
818 Rtv2
= DoCalcAddr(pAC
, pPrt
, pPrt
->PRxQSize
, &StartAddr
,
819 &pPrt
->PRxQRamStart
, &pPrt
->PRxQRamEnd
);
822 /* Calculate/Check values for the synchronous Tx queue */
823 Rtv2
= DoCalcAddr(pAC
, pPrt
, pPrt
->PXSQSize
, &StartAddr
,
824 &pPrt
->PXsQRamStart
, &pPrt
->PXsQRamEnd
);
827 /* Calculate/Check values for the asynchronous Tx queue */
828 Rtv2
= DoCalcAddr(pAC
, pPrt
, pPrt
->PXAQSize
, &StartAddr
,
829 &pPrt
->PXaQRamStart
, &pPrt
->PXaQRamEnd
);
833 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E013
, SKERR_HWI_E013MSG
);
839 } /* SkGeCheckQSize */
842 /******************************************************************************
844 * SkGeInitMacArb() - Initialize the MAC Arbiter
847 * This function initializes the MAC Arbiter.
848 * It must not be called if there is still an
849 * initialized or active port.
854 static void SkGeInitMacArb(
855 SK_AC
*pAC
, /* adapter context */
856 SK_IOC IoC
) /* IO context */
858 /* release local reset */
859 SK_OUT16(IoC
, B3_MA_TO_CTRL
, MA_RST_CLR
);
861 /* configure timeout values */
862 SK_OUT8(IoC
, B3_MA_TOINI_RX1
, SK_MAC_TO_53
);
863 SK_OUT8(IoC
, B3_MA_TOINI_RX2
, SK_MAC_TO_53
);
864 SK_OUT8(IoC
, B3_MA_TOINI_TX1
, SK_MAC_TO_53
);
865 SK_OUT8(IoC
, B3_MA_TOINI_TX2
, SK_MAC_TO_53
);
867 SK_OUT8(IoC
, B3_MA_RCINI_RX1
, 0);
868 SK_OUT8(IoC
, B3_MA_RCINI_RX2
, 0);
869 SK_OUT8(IoC
, B3_MA_RCINI_TX1
, 0);
870 SK_OUT8(IoC
, B3_MA_RCINI_TX2
, 0);
872 /* recovery values are needed for XMAC II Rev. B2 only */
873 /* Fast Output Enable Mode was intended to use with Rev. B2, but now? */
876 * There is no start or enable button to push, therefore
877 * the MAC arbiter is configured and enabled now.
879 } /* SkGeInitMacArb */
882 /******************************************************************************
884 * SkGeInitPktArb() - Initialize the Packet Arbiter
887 * This function initializes the Packet Arbiter.
888 * It must not be called if there is still an
889 * initialized or active port.
894 static void SkGeInitPktArb(
895 SK_AC
*pAC
, /* adapter context */
896 SK_IOC IoC
) /* IO context */
898 /* release local reset */
899 SK_OUT16(IoC
, B3_PA_CTRL
, PA_RST_CLR
);
901 /* configure timeout values */
902 SK_OUT16(IoC
, B3_PA_TOINI_RX1
, SK_PKT_TO_MAX
);
903 SK_OUT16(IoC
, B3_PA_TOINI_RX2
, SK_PKT_TO_MAX
);
904 SK_OUT16(IoC
, B3_PA_TOINI_TX1
, SK_PKT_TO_MAX
);
905 SK_OUT16(IoC
, B3_PA_TOINI_TX2
, SK_PKT_TO_MAX
);
908 * enable timeout timers if jumbo frames not used
909 * NOTE: the packet arbiter timeout interrupt is needed for
910 * half duplex hangup workaround
912 if (pAC
->GIni
.GIPortUsage
!= SK_JUMBO_LINK
) {
913 if (pAC
->GIni
.GIMacsFound
== 1) {
914 SK_OUT16(IoC
, B3_PA_CTRL
, PA_ENA_TO_TX1
);
917 SK_OUT16(IoC
, B3_PA_CTRL
, PA_ENA_TO_TX1
| PA_ENA_TO_TX2
);
920 } /* SkGeInitPktArb */
923 /******************************************************************************
925 * SkGeInitMacFifo() - Initialize the MAC FIFOs
928 * Initialize all MAC FIFOs of the specified port
933 static void SkGeInitMacFifo(
934 SK_AC
*pAC
, /* adapter context */
935 SK_IOC IoC
, /* IO context */
936 int Port
) /* Port Index (MAC_1 + n) */
944 * - release local reset
945 * - use default value for MAC FIFO size
946 * - setup defaults for the control register
950 Word
= GMF_RX_CTRL_DEF
;
952 if (pAC
->GIni
.GIGenesis
) {
953 /* Configure Rx MAC FIFO */
954 SK_OUT8(IoC
, MR_ADDR(Port
, RX_MFF_CTRL2
), MFF_RST_CLR
);
955 SK_OUT16(IoC
, MR_ADDR(Port
, RX_MFF_CTRL1
), MFF_RX_CTRL_DEF
);
956 SK_OUT8(IoC
, MR_ADDR(Port
, RX_MFF_CTRL2
), MFF_ENA_OP_MD
);
958 /* Configure Tx MAC FIFO */
959 SK_OUT8(IoC
, MR_ADDR(Port
, TX_MFF_CTRL2
), MFF_RST_CLR
);
960 SK_OUT16(IoC
, MR_ADDR(Port
, TX_MFF_CTRL1
), MFF_TX_CTRL_DEF
);
961 SK_OUT8(IoC
, MR_ADDR(Port
, TX_MFF_CTRL2
), MFF_ENA_OP_MD
);
963 /* Enable frame flushing if jumbo frames used */
964 if (pAC
->GIni
.GIPortUsage
== SK_JUMBO_LINK
) {
965 SK_OUT16(IoC
, MR_ADDR(Port
, RX_MFF_CTRL1
), MFF_ENA_FLUSH
);
969 /* set Rx GMAC FIFO Flush Mask */
970 SK_OUT16(IoC
, MR_ADDR(Port
, RX_GMF_FL_MSK
), (SK_U16
)RX_FF_FL_DEF_MSK
);
972 if (pAC
->GIni
.GIYukonLite
&& pAC
->GIni
.GIChipId
== CHIP_ID_YUKON
) {
974 Word
&= ~GMF_RX_F_FL_ON
;
977 /* Configure Rx MAC FIFO */
978 SK_OUT8(IoC
, MR_ADDR(Port
, RX_GMF_CTRL_T
), (SK_U8
)GMF_RST_CLR
);
979 SK_OUT16(IoC
, MR_ADDR(Port
, RX_GMF_CTRL_T
), Word
);
981 /* set Rx GMAC FIFO Flush Threshold (default: 0x0a -> 56 bytes) */
982 SK_OUT16(IoC
, MR_ADDR(Port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
);
984 /* Configure Tx MAC FIFO */
985 SK_OUT8(IoC
, MR_ADDR(Port
, TX_GMF_CTRL_T
), (SK_U8
)GMF_RST_CLR
);
986 SK_OUT16(IoC
, MR_ADDR(Port
, TX_GMF_CTRL_T
), (SK_U16
)GMF_TX_CTRL_DEF
);
989 SK_IN32(IoC
, MR_ADDR(Port
, RX_GMF_AF_THR
), &DWord
);
990 SK_IN32(IoC
, MR_ADDR(Port
, TX_GMF_AE_THR
), &DWord
);
993 /* set Tx GMAC FIFO Almost Empty Threshold */
994 /* SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), 0); */
996 } /* SkGeInitMacFifo */
999 /******************************************************************************
1001 * SkGeLoadLnkSyncCnt() - Load the Link Sync Counter and starts counting
1004 * This function starts the Link Sync Counter of the specified
1005 * port and enables the generation of an Link Sync IRQ.
1006 * The Link Sync Counter may be used to detect an active link,
1007 * if autonegotiation is not used.
1010 * o To ensure receiving the Link Sync Event the LinkSyncCounter
1011 * should be initialized BEFORE clearing the XMAC's reset!
1012 * o Enable IS_LNK_SYNC_M1 and IS_LNK_SYNC_M2 after calling this
1018 void SkGeLoadLnkSyncCnt(
1019 SK_AC
*pAC
, /* adapter context */
1020 SK_IOC IoC
, /* IO context */
1021 int Port
, /* Port Index (MAC_1 + n) */
1022 SK_U32 CntVal
) /* Counter value */
1030 SK_OUT8(IoC
, MR_ADDR(Port
, LNK_SYNC_CTRL
), LED_STOP
);
1034 * Each time starting the Link Sync Counter an IRQ is generated
1035 * by the adapter. See problem report entry from 21.07.98
1037 * Workaround: Disable Link Sync IRQ and clear the unexpeced IRQ
1038 * if no IRQ is already pending.
1041 SK_IN32(IoC
, B0_ISRC
, &ISrc
);
1042 SK_IN32(IoC
, B0_IMSK
, &OrgIMsk
);
1043 if (Port
== MAC_1
) {
1044 NewIMsk
= OrgIMsk
& ~IS_LNK_SYNC_M1
;
1045 if ((ISrc
& IS_LNK_SYNC_M1
) != 0) {
1050 NewIMsk
= OrgIMsk
& ~IS_LNK_SYNC_M2
;
1051 if ((ISrc
& IS_LNK_SYNC_M2
) != 0) {
1056 SK_OUT32(IoC
, B0_IMSK
, NewIMsk
);
1060 SK_OUT32(IoC
, MR_ADDR(Port
, LNK_SYNC_INI
), CntVal
);
1063 SK_OUT8(IoC
, MR_ADDR(Port
, LNK_SYNC_CTRL
), LED_START
);
1066 /* clear the unexpected IRQ, and restore the interrupt mask */
1067 SK_OUT8(IoC
, MR_ADDR(Port
, LNK_SYNC_CTRL
), LED_CLR_IRQ
);
1068 SK_OUT32(IoC
, B0_IMSK
, OrgIMsk
);
1070 } /* SkGeLoadLnkSyncCnt*/
1073 /******************************************************************************
1075 * SkGeCfgSync() - Configure synchronous bandwidth for this port.
1078 * This function may be used to configure synchronous bandwidth
1079 * to the specified port. This may be done any time after
1080 * initializing the port. The configuration values are NOT saved
1081 * in the HWAC port structure and will be overwritten any
1082 * time when stopping and starting the port.
1083 * Any values for the synchronous configuration will be ignored
1084 * if the size of the synchronous queue is zero!
1086 * The default configuration for the synchronous service is
1087 * TXA_ENA_FSYNC. This means if the size of
1088 * the synchronous queue is unequal zero but no specific
1089 * synchronous bandwidth is configured, the synchronous queue
1090 * will always have the 'unlimited' transmit priority!
1092 * This mode will be restored if the synchronous bandwidth is
1093 * deallocated ('IntTime' = 0 and 'LimCount' = 0).
1097 * 1: parameter configuration error
1098 * 2: try to configure quality of service although no
1099 * synchronous queue is configured
1102 SK_AC
*pAC
, /* adapter context */
1103 SK_IOC IoC
, /* IO context */
1104 int Port
, /* Port Index (MAC_1 + n) */
1105 SK_U32 IntTime
, /* Interval Timer Value in units of 8ns */
1106 SK_U32 LimCount
, /* Number of bytes to transfer during IntTime */
1107 int SyncMode
) /* Sync Mode: TXA_ENA_ALLOC | TXA_DIS_ALLOC | 0 */
1113 /* check the parameters */
1114 if (LimCount
> IntTime
||
1115 (LimCount
== 0 && IntTime
!= 0) ||
1116 (LimCount
!= 0 && IntTime
== 0)) {
1118 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E010
, SKERR_HWI_E010MSG
);
1122 if (pAC
->GIni
.GP
[Port
].PXSQSize
== 0) {
1123 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E009
, SKERR_HWI_E009MSG
);
1127 /* calculate register values */
1128 IntTime
= (IntTime
/ 2) * pAC
->GIni
.GIHstClkFact
/ 100;
1129 LimCount
= LimCount
/ 8;
1131 if (IntTime
> TXA_MAX_VAL
|| LimCount
> TXA_MAX_VAL
) {
1132 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E010
, SKERR_HWI_E010MSG
);
1137 * - Enable 'Force Sync' to ensure the synchronous queue
1138 * has the priority while configuring the new values.
1139 * - Also 'disable alloc' to ensure the settings complies
1140 * to the SyncMode parameter.
1141 * - Disable 'Rate Control' to configure the new values.
1142 * - write IntTime and LimCount
1143 * - start 'Rate Control' and disable 'Force Sync'
1144 * if Interval Timer or Limit Counter not zero.
1146 SK_OUT8(IoC
, MR_ADDR(Port
, TXA_CTRL
),
1147 TXA_ENA_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1149 SK_OUT32(IoC
, MR_ADDR(Port
, TXA_ITI_INI
), IntTime
);
1150 SK_OUT32(IoC
, MR_ADDR(Port
, TXA_LIM_INI
), LimCount
);
1152 SK_OUT8(IoC
, MR_ADDR(Port
, TXA_CTRL
),
1153 (SK_U8
)(SyncMode
& (TXA_ENA_ALLOC
| TXA_DIS_ALLOC
)));
1155 if (IntTime
!= 0 || LimCount
!= 0) {
1156 SK_OUT8(IoC
, MR_ADDR(Port
, TXA_CTRL
), TXA_DIS_FSYNC
| TXA_START_RC
);
1163 /******************************************************************************
1165 * DoInitRamQueue() - Initialize the RAM Buffer Address of a single Queue
1168 * If the queue is used, enable and initialize it.
1169 * Make sure the queue is still reset, if it is not used.
1174 static void DoInitRamQueue(
1175 SK_AC
*pAC
, /* adapter context */
1176 SK_IOC IoC
, /* IO context */
1177 int QuIoOffs
, /* Queue IO Address Offset */
1178 SK_U32 QuStartAddr
, /* Queue Start Address */
1179 SK_U32 QuEndAddr
, /* Queue End Address */
1180 int QuType
) /* Queue Type (SK_RX_SRAM_Q|SK_RX_BRAM_Q|SK_TX_RAM_Q) */
1182 SK_U32 RxUpThresVal
;
1183 SK_U32 RxLoThresVal
;
1185 if (QuStartAddr
!= QuEndAddr
) {
1186 /* calculate thresholds, assume we have a big Rx queue */
1187 RxUpThresVal
= (QuEndAddr
+ 1 - QuStartAddr
- SK_RB_ULPP
) / 8;
1188 RxLoThresVal
= (QuEndAddr
+ 1 - QuStartAddr
- SK_RB_LLPP_B
)/8;
1190 /* build HW address format */
1191 QuStartAddr
= QuStartAddr
/ 8;
1192 QuEndAddr
= QuEndAddr
/ 8;
1194 /* release local reset */
1195 SK_OUT8(IoC
, RB_ADDR(QuIoOffs
, RB_CTRL
), RB_RST_CLR
);
1197 /* configure addresses */
1198 SK_OUT32(IoC
, RB_ADDR(QuIoOffs
, RB_START
), QuStartAddr
);
1199 SK_OUT32(IoC
, RB_ADDR(QuIoOffs
, RB_END
), QuEndAddr
);
1200 SK_OUT32(IoC
, RB_ADDR(QuIoOffs
, RB_WP
), QuStartAddr
);
1201 SK_OUT32(IoC
, RB_ADDR(QuIoOffs
, RB_RP
), QuStartAddr
);
1205 /* configure threshold for small Rx Queue */
1206 RxLoThresVal
+= (SK_RB_LLPP_B
- SK_RB_LLPP_S
) / 8;
1208 /* continue with SK_RX_BRAM_Q */
1210 /* write threshold for Rx Queue */
1212 SK_OUT32(IoC
, RB_ADDR(QuIoOffs
, RB_RX_UTPP
), RxUpThresVal
);
1213 SK_OUT32(IoC
, RB_ADDR(QuIoOffs
, RB_RX_LTPP
), RxLoThresVal
);
1215 /* the high priority threshold not used */
1219 * Do NOT use Store & Forward under normal operation due to
1220 * performance optimization (GENESIS only).
1221 * But if Jumbo Frames are configured (XMAC Tx FIFO is only 4 kB)
1222 * or YUKON is used ((GMAC Tx FIFO is only 1 kB)
1223 * we NEED Store & Forward of the RAM buffer.
1225 if (pAC
->GIni
.GIPortUsage
== SK_JUMBO_LINK
||
1226 !pAC
->GIni
.GIGenesis
) {
1227 /* enable Store & Forward Mode for the Tx Side */
1228 SK_OUT8(IoC
, RB_ADDR(QuIoOffs
, RB_CTRL
), RB_ENA_STFWD
);
1233 /* set queue operational */
1234 SK_OUT8(IoC
, RB_ADDR(QuIoOffs
, RB_CTRL
), RB_ENA_OP_MD
);
1237 /* ensure the queue is still disabled */
1238 SK_OUT8(IoC
, RB_ADDR(QuIoOffs
, RB_CTRL
), RB_RST_SET
);
1240 } /* DoInitRamQueue */
1243 /******************************************************************************
1245 * SkGeInitRamBufs() - Initialize the RAM Buffer Queues
1248 * Initialize all RAM Buffer Queues of the specified port
1253 static void SkGeInitRamBufs(
1254 SK_AC
*pAC
, /* adapter context */
1255 SK_IOC IoC
, /* IO context */
1256 int Port
) /* Port Index (MAC_1 + n) */
1261 pPrt
= &pAC
->GIni
.GP
[Port
];
1263 if (pPrt
->PRxQSize
== SK_MIN_RXQ_SIZE
) {
1264 RxQType
= SK_RX_SRAM_Q
; /* small Rx Queue */
1266 RxQType
= SK_RX_BRAM_Q
; /* big Rx Queue */
1269 DoInitRamQueue(pAC
, IoC
, pPrt
->PRxQOff
, pPrt
->PRxQRamStart
,
1270 pPrt
->PRxQRamEnd
, RxQType
);
1272 DoInitRamQueue(pAC
, IoC
, pPrt
->PXsQOff
, pPrt
->PXsQRamStart
,
1273 pPrt
->PXsQRamEnd
, SK_TX_RAM_Q
);
1275 DoInitRamQueue(pAC
, IoC
, pPrt
->PXaQOff
, pPrt
->PXaQRamStart
,
1276 pPrt
->PXaQRamEnd
, SK_TX_RAM_Q
);
1278 } /* SkGeInitRamBufs */
1281 /******************************************************************************
1283 * SkGeInitRamIface() - Initialize the RAM Interface
1286 * This function initializes the Adapters RAM Interface.
1289 * This function is used in the diagnostics.
1294 void SkGeInitRamIface(
1295 SK_AC
*pAC
, /* adapter context */
1296 SK_IOC IoC
) /* IO context */
1298 /* release local reset */
1299 SK_OUT16(IoC
, B3_RI_CTRL
, RI_RST_CLR
);
1301 /* configure timeout values */
1302 SK_OUT8(IoC
, B3_RI_WTO_R1
, SK_RI_TO_53
);
1303 SK_OUT8(IoC
, B3_RI_WTO_XA1
, SK_RI_TO_53
);
1304 SK_OUT8(IoC
, B3_RI_WTO_XS1
, SK_RI_TO_53
);
1305 SK_OUT8(IoC
, B3_RI_RTO_R1
, SK_RI_TO_53
);
1306 SK_OUT8(IoC
, B3_RI_RTO_XA1
, SK_RI_TO_53
);
1307 SK_OUT8(IoC
, B3_RI_RTO_XS1
, SK_RI_TO_53
);
1308 SK_OUT8(IoC
, B3_RI_WTO_R2
, SK_RI_TO_53
);
1309 SK_OUT8(IoC
, B3_RI_WTO_XA2
, SK_RI_TO_53
);
1310 SK_OUT8(IoC
, B3_RI_WTO_XS2
, SK_RI_TO_53
);
1311 SK_OUT8(IoC
, B3_RI_RTO_R2
, SK_RI_TO_53
);
1312 SK_OUT8(IoC
, B3_RI_RTO_XA2
, SK_RI_TO_53
);
1313 SK_OUT8(IoC
, B3_RI_RTO_XS2
, SK_RI_TO_53
);
1315 } /* SkGeInitRamIface */
1318 /******************************************************************************
1320 * SkGeInitBmu() - Initialize the BMU state machines
1323 * Initialize all BMU state machines of the specified port
1328 static void SkGeInitBmu(
1329 SK_AC
*pAC
, /* adapter context */
1330 SK_IOC IoC
, /* IO context */
1331 int Port
) /* Port Index (MAC_1 + n) */
1337 pPrt
= &pAC
->GIni
.GP
[Port
];
1339 RxWm
= SK_BMU_RX_WM
;
1340 TxWm
= SK_BMU_TX_WM
;
1342 if (!pAC
->GIni
.GIPciSlot64
&& !pAC
->GIni
.GIPciClock66
) {
1343 /* for better performance */
1348 /* Rx Queue: Release all local resets and set the watermark */
1349 SK_OUT32(IoC
, Q_ADDR(pPrt
->PRxQOff
, Q_CSR
), CSR_CLR_RESET
);
1350 SK_OUT32(IoC
, Q_ADDR(pPrt
->PRxQOff
, Q_F
), RxWm
);
1353 * Tx Queue: Release all local resets if the queue is used !
1356 if (pPrt
->PXSQSize
!= 0) {
1357 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXsQOff
, Q_CSR
), CSR_CLR_RESET
);
1358 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXsQOff
, Q_F
), TxWm
);
1361 if (pPrt
->PXAQSize
!= 0) {
1362 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXaQOff
, Q_CSR
), CSR_CLR_RESET
);
1363 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXaQOff
, Q_F
), TxWm
);
1366 * Do NOT enable the descriptor poll timers here, because
1367 * the descriptor addresses are not specified yet.
1372 /******************************************************************************
1374 * TestStopBit() - Test the stop bit of the queue
1377 * Stopping a queue is not as simple as it seems to be.
1378 * If descriptor polling is enabled, it may happen
1379 * that RX/TX stop is done and SV idle is NOT set.
1380 * In this case we have to issue another stop command.
1383 * The queues control status register
1385 static SK_U32
TestStopBit(
1386 SK_AC
*pAC
, /* Adapter Context */
1387 SK_IOC IoC
, /* IO Context */
1388 int QuIoOffs
) /* Queue IO Address Offset */
1390 SK_U32 QuCsr
; /* CSR contents */
1392 SK_IN32(IoC
, Q_ADDR(QuIoOffs
, Q_CSR
), &QuCsr
);
1394 if ((QuCsr
& (CSR_STOP
| CSR_SV_IDLE
)) == 0) {
1395 /* Stop Descriptor overridden by start command */
1396 SK_OUT32(IoC
, Q_ADDR(QuIoOffs
, Q_CSR
), CSR_STOP
);
1398 SK_IN32(IoC
, Q_ADDR(QuIoOffs
, Q_CSR
), &QuCsr
);
1405 /******************************************************************************
1407 * SkGeStopPort() - Stop the Rx/Tx activity of the port 'Port'.
1410 * After calling this function the descriptor rings and Rx and Tx
1411 * queues of this port may be reconfigured.
1413 * It is possible to stop the receive and transmit path separate or
1416 * Dir = SK_STOP_TX Stops the transmit path only and resets the MAC.
1417 * The receive queue is still active and
1418 * the pending Rx frames may be still transferred
1420 * SK_STOP_RX Stop the receive path. The tansmit path
1421 * has to be stopped once before.
1422 * SK_STOP_ALL SK_STOP_TX + SK_STOP_RX
1424 * RstMode = SK_SOFT_RST Resets the MAC. The PHY is still alive.
1425 * SK_HARD_RST Resets the MAC and the PHY.
1428 * 1) A Link Down event was signaled for a port. Therefore the activity
1429 * of this port should be stopped and a hardware reset should be issued
1430 * to enable the workaround of XMAC errata #2. But the received frames
1431 * should not be discarded.
1433 * SkGeStopPort(pAC, IoC, Port, SK_STOP_TX, SK_HARD_RST);
1434 * (transfer all pending Rx frames)
1435 * SkGeStopPort(pAC, IoC, Port, SK_STOP_RX, SK_HARD_RST);
1438 * 2) An event was issued which request the driver to switch
1439 * the 'virtual active' link to an other already active port
1440 * as soon as possible. The frames in the receive queue of this
1441 * port may be lost. But the PHY must not be reset during this
1444 * SkGeStopPort(pAC, IoC, Port, SK_STOP_ALL, SK_SOFT_RST);
1447 * Extended Description:
1448 * If SK_STOP_TX is set,
1449 * o disable the MAC's receive and transmitter to prevent
1450 * from sending incomplete frames
1451 * o stop the port's transmit queues before terminating the
1452 * BMUs to prevent from performing incomplete PCI cycles
1454 * - The network Rx and Tx activity and PCI Tx transfer is
1456 * o reset the MAC depending on the RstMode
1457 * o Stop Interval Timer and Limit Counter of Tx Arbiter,
1458 * also disable Force Sync bit and Enable Alloc bit.
1459 * o perform a local reset of the port's Tx path
1460 * - reset the PCI FIFO of the async Tx queue
1461 * - reset the PCI FIFO of the sync Tx queue
1462 * - reset the RAM Buffer async Tx queue
1463 * - reset the RAM Buffer sync Tx queue
1464 * - reset the MAC Tx FIFO
1465 * o switch Link and Tx LED off, stop the LED counters
1467 * If SK_STOP_RX is set,
1468 * o stop the port's receive queue
1469 * - The path data transfer activity is fully stopped now.
1470 * o perform a local reset of the port's Rx path
1471 * - reset the PCI FIFO of the Rx queue
1472 * - reset the RAM Buffer receive queue
1473 * - reset the MAC Rx FIFO
1474 * o switch Rx LED off, stop the LED counter
1476 * If all ports are stopped,
1477 * o reset the RAM Interface.
1480 * o This function may be called during the driver states RESET_PORT and
1484 SK_AC
*pAC
, /* adapter context */
1485 SK_IOC IoC
, /* I/O context */
1486 int Port
, /* port to stop (MAC_1 + n) */
1487 int Dir
, /* Direction to Stop (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */
1488 int RstMode
)/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */
1492 #endif /* !SK_DIAG */
1501 pPrt
= &pAC
->GIni
.GP
[Port
];
1503 if ((Dir
& SK_STOP_TX
) != 0) {
1504 /* disable receiver and transmitter */
1505 SkMacRxTxDisable(pAC
, IoC
, Port
);
1507 /* stop both transmit queues */
1509 * If the BMU is in the reset state CSR_STOP will terminate
1512 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXsQOff
, Q_CSR
), CSR_STOP
);
1513 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXaQOff
, Q_CSR
), CSR_STOP
);
1515 ToutStart
= SkOsGetTime(pAC
);
1519 * Clear packet arbiter timeout to make sure
1520 * this loop will terminate.
1522 SK_OUT16(IoC
, B3_PA_CTRL
, (Port
== MAC_1
) ? PA_CLR_TO_TX1
:
1526 * If the transfer stucks at the MAC the STOP command will not
1527 * terminate if we don't flush the XMAC's transmit FIFO !
1529 SkMacFlushTxFifo(pAC
, IoC
, Port
);
1531 XsCsr
= TestStopBit(pAC
, IoC
, pPrt
->PXsQOff
);
1532 XaCsr
= TestStopBit(pAC
, IoC
, pPrt
->PXaQOff
);
1534 if (SkOsGetTime(pAC
) - ToutStart
> (SK_TICKS_PER_SEC
/ 18)) {
1536 * Timeout of 1/18 second reached.
1537 * This needs to be checked at 1/18 sec only.
1541 /* Might be a problem when the driver event handler
1542 * calls StopPort again. XXX.
1545 /* Fatal Error, Loop aborted */
1546 SK_ERR_LOG(pAC
, SK_ERRCL_HW
, SKERR_HWI_E018
,
1550 SkEventQueue(pAC
, SKGE_DRV
, SK_DRV_PORT_FAIL
, Para
);
1551 #endif /* !SK_DIAG */
1555 * Cache incoherency workaround: Assume a start command
1556 * has been lost while sending the frame.
1558 ToutStart
= SkOsGetTime(pAC
);
1560 if ((XsCsr
& CSR_STOP
) != 0) {
1561 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXsQOff
, Q_CSR
), CSR_START
);
1563 if ((XaCsr
& CSR_STOP
) != 0) {
1564 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXaQOff
, Q_CSR
), CSR_START
);
1569 * Because of the ASIC problem report entry from 21.08.1998 it is
1570 * required to wait until CSR_STOP is reset and CSR_SV_IDLE is set.
1572 } while ((XsCsr
& (CSR_STOP
| CSR_SV_IDLE
)) != CSR_SV_IDLE
||
1573 (XaCsr
& (CSR_STOP
| CSR_SV_IDLE
)) != CSR_SV_IDLE
);
1575 /* Reset the MAC depending on the RstMode */
1576 if (RstMode
== SK_SOFT_RST
) {
1577 SkMacSoftRst(pAC
, IoC
, Port
);
1580 SkMacHardRst(pAC
, IoC
, Port
);
1583 /* Disable Force Sync bit and Enable Alloc bit */
1584 SK_OUT8(IoC
, MR_ADDR(Port
, TXA_CTRL
),
1585 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1587 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1588 SK_OUT32(IoC
, MR_ADDR(Port
, TXA_ITI_INI
), 0L);
1589 SK_OUT32(IoC
, MR_ADDR(Port
, TXA_LIM_INI
), 0L);
1591 /* Perform a local reset of the port's Tx path */
1593 /* Reset the PCI FIFO of the async Tx queue */
1594 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXaQOff
, Q_CSR
), CSR_SET_RESET
);
1595 /* Reset the PCI FIFO of the sync Tx queue */
1596 SK_OUT32(IoC
, Q_ADDR(pPrt
->PXsQOff
, Q_CSR
), CSR_SET_RESET
);
1597 /* Reset the RAM Buffer async Tx queue */
1598 SK_OUT8(IoC
, RB_ADDR(pPrt
->PXaQOff
, RB_CTRL
), RB_RST_SET
);
1599 /* Reset the RAM Buffer sync Tx queue */
1600 SK_OUT8(IoC
, RB_ADDR(pPrt
->PXsQOff
, RB_CTRL
), RB_RST_SET
);
1602 /* Reset Tx MAC FIFO */
1603 if (pAC
->GIni
.GIGenesis
) {
1604 /* Note: MFF_RST_SET does NOT reset the XMAC ! */
1605 SK_OUT8(IoC
, MR_ADDR(Port
, TX_MFF_CTRL2
), MFF_RST_SET
);
1607 /* switch Link and Tx LED off, stop the LED counters */
1608 /* Link LED is switched off by the RLMT and the Diag itself */
1609 SkGeXmitLED(pAC
, IoC
, MR_ADDR(Port
, TX_LED_INI
), SK_LED_DIS
);
1612 /* Reset TX MAC FIFO */
1613 SK_OUT8(IoC
, MR_ADDR(Port
, TX_GMF_CTRL_T
), (SK_U8
)GMF_RST_SET
);
1617 if ((Dir
& SK_STOP_RX
) != 0) {
1619 * The RX Stop Command will not terminate if no buffers
1620 * are queued in the RxD ring. But it will always reach
1621 * the Idle state. Therefore we can use this feature to
1622 * stop the transfer of received packets.
1624 /* stop the port's receive queue */
1625 SK_OUT32(IoC
, Q_ADDR(pPrt
->PRxQOff
, Q_CSR
), CSR_STOP
);
1630 * Clear packet arbiter timeout to make sure
1631 * this loop will terminate
1633 SK_OUT16(IoC
, B3_PA_CTRL
, (Port
== MAC_1
) ? PA_CLR_TO_RX1
:
1636 DWord
= TestStopBit(pAC
, IoC
, pPrt
->PRxQOff
);
1638 /* timeout if i==0 (bug fix for #10748) */
1640 SK_ERR_LOG(pAC
, SK_ERRCL_HW
, SKERR_HWI_E024
,
1645 * because of the ASIC problem report entry from 21.08.98
1646 * it is required to wait until CSR_STOP is reset and
1647 * CSR_SV_IDLE is set.
1649 } while ((DWord
& (CSR_STOP
| CSR_SV_IDLE
)) != CSR_SV_IDLE
);
1651 /* The path data transfer activity is fully stopped now */
1653 /* Perform a local reset of the port's Rx path */
1655 /* Reset the PCI FIFO of the Rx queue */
1656 SK_OUT32(IoC
, Q_ADDR(pPrt
->PRxQOff
, Q_CSR
), CSR_SET_RESET
);
1657 /* Reset the RAM Buffer receive queue */
1658 SK_OUT8(IoC
, RB_ADDR(pPrt
->PRxQOff
, RB_CTRL
), RB_RST_SET
);
1660 /* Reset Rx MAC FIFO */
1661 if (pAC
->GIni
.GIGenesis
) {
1663 SK_OUT8(IoC
, MR_ADDR(Port
, RX_MFF_CTRL2
), MFF_RST_SET
);
1665 /* switch Rx LED off, stop the LED counter */
1666 SkGeXmitLED(pAC
, IoC
, MR_ADDR(Port
, RX_LED_INI
), SK_LED_DIS
);
1669 /* Reset Rx MAC FIFO */
1670 SK_OUT8(IoC
, MR_ADDR(Port
, RX_GMF_CTRL_T
), (SK_U8
)GMF_RST_SET
);
1673 } /* SkGeStopPort */
1676 /******************************************************************************
1678 * SkGeInit0() - Level 0 Initialization
1681 * - Initialize the BMU address offsets
1686 static void SkGeInit0(
1687 SK_AC
*pAC
, /* adapter context */
1688 SK_IOC IoC
) /* IO context */
1693 for (i
= 0; i
< SK_MAX_MACS
; i
++) {
1694 pPrt
= &pAC
->GIni
.GP
[i
];
1696 pPrt
->PState
= SK_PRT_RESET
;
1697 pPrt
->PRxQOff
= QOffTab
[i
].RxQOff
;
1698 pPrt
->PXsQOff
= QOffTab
[i
].XsQOff
;
1699 pPrt
->PXaQOff
= QOffTab
[i
].XaQOff
;
1700 pPrt
->PCheckPar
= SK_FALSE
;
1702 pPrt
->PPrevShorts
= 0;
1703 pPrt
->PLinkResCt
= 0;
1704 pPrt
->PAutoNegTOCt
= 0;
1707 pPrt
->PRxLim
= SK_DEF_RX_WA_LIM
;
1708 pPrt
->PLinkMode
= SK_LMODE_AUTOFULL
;
1709 pPrt
->PLinkSpeedCap
= SK_LSPEED_CAP_1000MBPS
;
1710 pPrt
->PLinkSpeed
= SK_LSPEED_1000MBPS
;
1711 pPrt
->PLinkSpeedUsed
= SK_LSPEED_STAT_UNKNOWN
;
1712 pPrt
->PLinkModeConf
= SK_LMODE_AUTOSENSE
;
1713 pPrt
->PFlowCtrlMode
= SK_FLOW_MODE_SYM_OR_REM
;
1714 pPrt
->PLinkBroken
= SK_TRUE
; /* See WA code */
1715 pPrt
->PLinkCap
= (SK_LMODE_CAP_HALF
| SK_LMODE_CAP_FULL
|
1716 SK_LMODE_CAP_AUTOHALF
| SK_LMODE_CAP_AUTOFULL
);
1717 pPrt
->PLinkModeStatus
= SK_LMODE_STAT_UNKNOWN
;
1718 pPrt
->PFlowCtrlCap
= SK_FLOW_MODE_SYM_OR_REM
;
1719 pPrt
->PFlowCtrlStatus
= SK_FLOW_STAT_NONE
;
1721 pPrt
->PMSMode
= SK_MS_MODE_AUTO
;
1722 pPrt
->PMSStatus
= SK_MS_STAT_UNSET
;
1723 pPrt
->PAutoNegFail
= SK_FALSE
;
1724 pPrt
->PLipaAutoNeg
= SK_LIPA_UNKNOWN
;
1725 pPrt
->PHWLinkUp
= SK_FALSE
;
1728 pAC
->GIni
.GIPortUsage
= SK_RED_LINK
;
1734 /******************************************************************************
1736 * SkGePciReset() - Reset PCI interface
1739 * o Read PCI configuration.
1740 * o Change power state to 3.
1741 * o Change power state to 0.
1742 * o Restore PCI configuration.
1746 * 1: Power state could not be changed to 3.
1748 static int SkGePciReset(
1749 SK_AC
*pAC
, /* adapter context */
1750 SK_IOC IoC
) /* IO context */
1759 SK_U8 ConfigSpace
[PCI_CFG_SIZE
];
1762 * Note: Switching to D3 state is like a software reset.
1763 * Switching from D3 to D0 is a hardware reset.
1764 * We have to save and restore the configuration space.
1766 for (i
= 0; i
< PCI_CFG_SIZE
; i
++) {
1767 SkPciReadCfgDWord(pAC
, i
*4, &ConfigSpace
[i
]);
1770 /* We know the RAM Interface Arbiter is enabled. */
1771 SkPciWriteCfgWord(pAC
, PCI_PM_CTL_STS
, PCI_PM_STATE_D3
);
1772 SkPciReadCfgWord(pAC
, PCI_PM_CTL_STS
, &PmCtlSts
);
1774 if ((PmCtlSts
& PCI_PM_STATE_MSK
) != PCI_PM_STATE_D3
) {
1778 /* Return to D0 state. */
1779 SkPciWriteCfgWord(pAC
, PCI_PM_CTL_STS
, PCI_PM_STATE_D0
);
1781 /* Check for D0 state. */
1782 SkPciReadCfgWord(pAC
, PCI_PM_CTL_STS
, &PmCtlSts
);
1784 if ((PmCtlSts
& PCI_PM_STATE_MSK
) != PCI_PM_STATE_D0
) {
1788 /* Check PCI Config Registers. */
1789 SkPciReadCfgWord(pAC
, PCI_COMMAND
, &PciCmd
);
1790 SkPciReadCfgByte(pAC
, PCI_CACHE_LSZ
, &Cls
);
1791 SkPciReadCfgDWord(pAC
, PCI_BASE_1ST
, &Bp1
);
1792 SkPciReadCfgDWord(pAC
, PCI_BASE_2ND
, &Bp2
);
1793 SkPciReadCfgByte(pAC
, PCI_LAT_TIM
, &Lat
);
1795 if (PciCmd
!= 0 || Cls
!= 0 || (Bp1
& 0xfffffff0L
) != 0 || Bp2
!= 1 ||
1800 /* Restore PCI Config Space. */
1801 for (i
= 0; i
< PCI_CFG_SIZE
; i
++) {
1802 SkPciWriteCfgDWord(pAC
, i
*4, ConfigSpace
[i
]);
1806 } /* SkGePciReset */
1808 #endif /* SK_PCI_RESET */
1810 /******************************************************************************
1812 * SkGeInit1() - Level 1 Initialization
1815 * o Do a software reset.
1816 * o Clear all reset bits.
1817 * o Verify that the detected hardware is present.
1818 * Return an error if not.
1819 * o Get the hardware configuration
1820 * + Read the number of MACs/Ports.
1821 * + Read the RAM size.
1822 * + Read the PCI Revision Id.
1823 * + Find out the adapters host clock speed
1824 * + Read and check the PHY type
1828 * 5: Unexpected PHY type detected
1829 * 6: HW self test failed
1831 static int SkGeInit1(
1832 SK_AC
*pAC
, /* adapter context */
1833 SK_IOC IoC
) /* IO context */
1844 /* save CLK_RUN bits (YUKON-Lite) */
1845 SK_IN16(IoC
, B0_CTST
, &CtrlStat
);
1848 (void)SkGePciReset(pAC
, IoC
);
1849 #endif /* SK_PCI_RESET */
1851 /* do the SW-reset */
1852 SK_OUT8(IoC
, B0_CTST
, CS_RST_SET
);
1854 /* release the SW-reset */
1855 SK_OUT8(IoC
, B0_CTST
, CS_RST_CLR
);
1857 /* reset all error bits in the PCI STATUS register */
1859 * Note: PCI Cfg cycles cannot be used, because they are not
1860 * available on some platforms after 'boot time'.
1862 SK_IN16(IoC
, PCI_C(PCI_STATUS
), &Word
);
1864 SK_OUT8(IoC
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
1865 SK_OUT16(IoC
, PCI_C(PCI_STATUS
), Word
| PCI_ERRBITS
);
1866 SK_OUT8(IoC
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
1868 /* release Master Reset */
1869 SK_OUT8(IoC
, B0_CTST
, CS_MRST_CLR
);
1872 CtrlStat
|= CS_CLK_RUN_ENA
;
1873 #endif /* CLK_RUN */
1875 /* restore CLK_RUN bits */
1876 SK_OUT16(IoC
, B0_CTST
, CtrlStat
&
1877 (CS_CLK_RUN_HOT
| CS_CLK_RUN_RST
| CS_CLK_RUN_ENA
));
1879 /* read Chip Identification Number */
1880 SK_IN8(IoC
, B2_CHIP_ID
, &Byte
);
1881 pAC
->GIni
.GIChipId
= Byte
;
1883 /* read number of MACs */
1884 SK_IN8(IoC
, B2_MAC_CFG
, &Byte
);
1885 pAC
->GIni
.GIMacsFound
= (Byte
& CONFIG_SYS_SNG_MAC
) ? 1 : 2;
1887 /* get Chip Revision Number */
1888 pAC
->GIni
.GIChipRev
= (SK_U8
)((Byte
& CONFIG_SYS_CHIP_R_MSK
) >> 4);
1890 /* get diff. PCI parameters */
1891 SK_IN16(IoC
, B0_CTST
, &CtrlStat
);
1893 /* read the adapters RAM size */
1894 SK_IN8(IoC
, B2_E_0
, &Byte
);
1896 if (pAC
->GIni
.GIChipId
== CHIP_ID_GENESIS
) {
1898 pAC
->GIni
.GIGenesis
= SK_TRUE
;
1901 /* special case: 4 x 64k x 36, offset = 0x80000 */
1902 pAC
->GIni
.GIRamSize
= 1024;
1903 pAC
->GIni
.GIRamOffs
= (SK_U32
)512 * 1024;
1906 pAC
->GIni
.GIRamSize
= (int)Byte
* 512;
1907 pAC
->GIni
.GIRamOffs
= 0;
1909 /* all GE adapters work with 53.125 MHz host clock */
1910 pAC
->GIni
.GIHstClkFact
= SK_FACT_53
;
1912 /* set Descr. Poll Timer Init Value to 250 ms */
1913 pAC
->GIni
.GIPollTimerVal
=
1914 SK_DPOLL_DEF
* (SK_U32
)pAC
->GIni
.GIHstClkFact
/ 100;
1917 pAC
->GIni
.GIGenesis
= SK_FALSE
;
1920 pAC
->GIni
.GIRamSize
= (Byte
== 0) ? 128 : (int)Byte
* 4;
1922 pAC
->GIni
.GIRamSize
= 128;
1924 pAC
->GIni
.GIRamOffs
= 0;
1926 /* WA for chip Rev. A */
1927 pAC
->GIni
.GIWolOffs
= (pAC
->GIni
.GIChipRev
== 0) ? WOL_REG_OFFS
: 0;
1929 /* get PM Capabilities of PCI config space */
1930 SK_IN16(IoC
, PCI_C(PCI_PM_CAP_REG
), &Word
);
1932 /* check if VAUX is available */
1933 if (((CtrlStat
& CS_VAUX_AVAIL
) != 0) &&
1934 /* check also if PME from D3cold is set */
1935 ((Word
& PCI_PME_D3C_SUP
) != 0)) {
1936 /* set entry in GE init struct */
1937 pAC
->GIni
.GIVauxAvail
= SK_TRUE
;
1940 /* save Flash-Address Register */
1941 SK_IN32(IoC
, B2_FAR
, &FlashAddr
);
1943 /* test Flash-Address Register */
1944 SK_OUT8(IoC
, B2_FAR
+ 3, 0xff);
1945 SK_IN8(IoC
, B2_FAR
+ 3, &Byte
);
1947 pAC
->GIni
.GIYukonLite
= (SK_BOOL
)(Byte
!= 0);
1949 /* restore Flash-Address Register */
1950 SK_OUT32(IoC
, B2_FAR
, FlashAddr
);
1952 for (i
= 0; i
< pAC
->GIni
.GIMacsFound
; i
++) {
1953 /* set GMAC Link Control reset */
1954 SK_OUT16(IoC
, MR_ADDR(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
1956 /* clear GMAC Link Control reset */
1957 SK_OUT16(IoC
, MR_ADDR(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
1959 /* all YU chips work with 78.125 MHz host clock */
1960 pAC
->GIni
.GIHstClkFact
= SK_FACT_78
;
1962 pAC
->GIni
.GIPollTimerVal
= SK_DPOLL_MAX
; /* 215 ms */
1965 /* check if 64-bit PCI Slot is present */
1966 pAC
->GIni
.GIPciSlot64
= (SK_BOOL
)((CtrlStat
& CS_BUS_SLOT_SZ
) != 0);
1968 /* check if 66 MHz PCI Clock is active */
1969 pAC
->GIni
.GIPciClock66
= (SK_BOOL
)((CtrlStat
& CS_BUS_CLOCK
) != 0);
1971 /* read PCI HW Revision Id. */
1972 SK_IN8(IoC
, PCI_C(PCI_REV_ID
), &Byte
);
1973 pAC
->GIni
.GIPciHwRev
= Byte
;
1975 /* read the PMD type */
1976 SK_IN8(IoC
, B2_PMD_TYP
, &Byte
);
1977 pAC
->GIni
.GICopperType
= (SK_U8
)(Byte
== 'T');
1979 /* read the PHY type */
1980 SK_IN8(IoC
, B2_E_1
, &Byte
);
1982 Byte
&= 0x0f; /* the PHY type is stored in the lower nibble */
1983 for (i
= 0; i
< pAC
->GIni
.GIMacsFound
; i
++) {
1985 if (pAC
->GIni
.GIGenesis
) {
1988 pAC
->GIni
.GP
[i
].PhyAddr
= PHY_ADDR_XMAC
;
1991 pAC
->GIni
.GP
[i
].PhyAddr
= PHY_ADDR_BCOM
;
1992 pAC
->GIni
.GP
[i
].PMSCap
=
1993 SK_MS_CAP_AUTO
| SK_MS_CAP_MASTER
| SK_MS_CAP_SLAVE
;
1997 pAC
->GIni
.GP
[i
].PhyAddr
= PHY_ADDR_LONE
;
2000 pAC
->GIni
.GP
[i
].PhyAddr
= PHY_ADDR_NAT
;
2002 #endif /* OTHER_PHY */
2004 /* ERROR: unexpected PHY type detected */
2011 /* if this field is not initialized */
2012 Byte
= SK_PHY_MARV_COPPER
;
2013 pAC
->GIni
.GICopperType
= SK_TRUE
;
2015 pAC
->GIni
.GP
[i
].PhyAddr
= PHY_ADDR_MARV
;
2017 if (pAC
->GIni
.GICopperType
) {
2018 pAC
->GIni
.GP
[i
].PLinkSpeedCap
= SK_LSPEED_CAP_AUTO
|
2019 SK_LSPEED_CAP_10MBPS
| SK_LSPEED_CAP_100MBPS
|
2020 SK_LSPEED_CAP_1000MBPS
;
2021 pAC
->GIni
.GP
[i
].PLinkSpeed
= SK_LSPEED_AUTO
;
2022 pAC
->GIni
.GP
[i
].PMSCap
=
2023 SK_MS_CAP_AUTO
| SK_MS_CAP_MASTER
| SK_MS_CAP_SLAVE
;
2026 Byte
= SK_PHY_MARV_FIBER
;
2030 pAC
->GIni
.GP
[i
].PhyType
= Byte
;
2032 SK_DBG_MSG(pAC
, SK_DBGMOD_HWM
, SK_DBGCAT_INIT
,
2033 ("PHY type: %d PHY addr: %04x\n", Byte
,
2034 pAC
->GIni
.GP
[i
].PhyAddr
));
2037 /* get Mac Type & set function pointers dependent on */
2038 if (pAC
->GIni
.GIGenesis
) {
2039 pAC
->GIni
.GIMacType
= SK_MAC_XMAC
;
2041 pAC
->GIni
.GIFunc
.pFnMacUpdateStats
= SkXmUpdateStats
;
2042 pAC
->GIni
.GIFunc
.pFnMacStatistic
= SkXmMacStatistic
;
2043 pAC
->GIni
.GIFunc
.pFnMacResetCounter
= SkXmResetCounter
;
2044 pAC
->GIni
.GIFunc
.pFnMacOverflow
= SkXmOverflowStatus
;
2047 pAC
->GIni
.GIMacType
= SK_MAC_GMAC
;
2049 pAC
->GIni
.GIFunc
.pFnMacUpdateStats
= SkGmUpdateStats
;
2050 pAC
->GIni
.GIFunc
.pFnMacStatistic
= SkGmMacStatistic
;
2051 pAC
->GIni
.GIFunc
.pFnMacResetCounter
= SkGmResetCounter
;
2052 pAC
->GIni
.GIFunc
.pFnMacOverflow
= SkGmOverflowStatus
;
2054 #ifdef SPECIAL_HANDLING
2055 if (pAC
->GIni
.GIChipId
== CHIP_ID_YUKON
) {
2056 /* check HW self test result */
2057 SK_IN8(IoC
, B2_E_3
, &Byte
);
2058 if ((Byte
& B2_E3_RES_MASK
) != 0) {
2068 /******************************************************************************
2070 * SkGeInit2() - Level 2 Initialization
2073 * - start the Blink Source Counter
2074 * - start the Descriptor Poll Timer
2075 * - configure the MAC-Arbiter
2076 * - configure the Packet-Arbiter
2077 * - enable the Tx Arbiters
2078 * - enable the RAM Interface Arbiter
2083 static void SkGeInit2(
2084 SK_AC
*pAC
, /* adapter context */
2085 SK_IOC IoC
) /* IO context */
2090 /* start the Descriptor Poll Timer */
2091 if (pAC
->GIni
.GIPollTimerVal
!= 0) {
2092 if (pAC
->GIni
.GIPollTimerVal
> SK_DPOLL_MAX
) {
2093 pAC
->GIni
.GIPollTimerVal
= SK_DPOLL_MAX
;
2095 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E017
, SKERR_HWI_E017MSG
);
2097 SK_OUT32(IoC
, B28_DPT_INI
, pAC
->GIni
.GIPollTimerVal
);
2098 SK_OUT8(IoC
, B28_DPT_CTRL
, DPT_START
);
2101 if (pAC
->GIni
.GIGenesis
) {
2102 /* start the Blink Source Counter */
2103 DWord
= SK_BLK_DUR
* (SK_U32
)pAC
->GIni
.GIHstClkFact
/ 100;
2105 SK_OUT32(IoC
, B2_BSC_INI
, DWord
);
2106 SK_OUT8(IoC
, B2_BSC_CTRL
, BSC_START
);
2109 * Configure the MAC Arbiter and the Packet Arbiter.
2110 * They will be started once and never be stopped.
2112 SkGeInitMacArb(pAC
, IoC
);
2114 SkGeInitPktArb(pAC
, IoC
);
2117 /* start Time Stamp Timer */
2118 SK_OUT8(IoC
, GMAC_TI_ST_CTRL
, (SK_U8
)GMT_ST_START
);
2121 /* enable the Tx Arbiters */
2122 for (i
= 0; i
< pAC
->GIni
.GIMacsFound
; i
++) {
2123 SK_OUT8(IoC
, MR_ADDR(i
, TXA_CTRL
), TXA_ENA_ARB
);
2126 /* enable the RAM Interface Arbiter */
2127 SkGeInitRamIface(pAC
, IoC
);
2131 /******************************************************************************
2133 * SkGeInit() - Initialize the GE Adapter with the specified level.
2136 * Level 0: Initialize the Module structures.
2137 * Level 1: Generic Hardware Initialization. The IOP/MemBase pointer has
2138 * to be set before calling this level.
2140 * o Do a software reset.
2141 * o Clear all reset bits.
2142 * o Verify that the detected hardware is present.
2143 * Return an error if not.
2144 * o Get the hardware configuration
2145 * + Set GIMacsFound with the number of MACs.
2146 * + Store the RAM size in GIRamSize.
2147 * + Save the PCI Revision ID in GIPciHwRev.
2149 * if Number of MACs > SK_MAX_MACS
2151 * After returning from Level 0 the adapter
2152 * may be accessed with IO operations.
2154 * Level 2: start the Blink Source Counter
2158 * 1: Number of MACs exceeds SK_MAX_MACS (after level 1)
2159 * 2: Adapter not present or not accessible
2160 * 3: Illegal initialization level
2161 * 4: Initialization Level 1 Call missing
2162 * 5: Unexpected PHY type detected
2163 * 6: HW self test failed
2166 SK_AC
*pAC
, /* adapter context */
2167 SK_IOC IoC
, /* IO context */
2168 int Level
) /* initialization level */
2170 int RetVal
; /* return value */
2174 SK_DBG_MSG(pAC
, SK_DBGMOD_HWM
, SK_DBGCAT_INIT
,
2175 ("SkGeInit(Level %d)\n", Level
));
2179 /* Initialization Level 0 */
2180 SkGeInit0(pAC
, IoC
);
2181 pAC
->GIni
.GILevel
= SK_INIT_DATA
;
2185 /* Initialization Level 1 */
2186 RetVal
= SkGeInit1(pAC
, IoC
);
2191 /* check if the adapter seems to be accessible */
2192 SK_OUT32(IoC
, B2_IRQM_INI
, 0x11335577L
);
2193 SK_IN32(IoC
, B2_IRQM_INI
, &DWord
);
2194 SK_OUT32(IoC
, B2_IRQM_INI
, 0L);
2196 if (DWord
!= 0x11335577L
) {
2201 /* check if the number of GIMacsFound matches SK_MAX_MACS */
2202 if (pAC
->GIni
.GIMacsFound
> SK_MAX_MACS
) {
2207 /* Level 1 successfully passed */
2208 pAC
->GIni
.GILevel
= SK_INIT_IO
;
2212 /* Initialization Level 2 */
2213 if (pAC
->GIni
.GILevel
!= SK_INIT_IO
) {
2215 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E002
, SKERR_HWI_E002MSG
);
2216 #endif /* !SK_DIAG */
2220 SkGeInit2(pAC
, IoC
);
2222 /* Level 2 successfully passed */
2223 pAC
->GIni
.GILevel
= SK_INIT_RUN
;
2227 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E003
, SKERR_HWI_E003MSG
);
2236 /******************************************************************************
2238 * SkGeDeInit() - Deinitialize the adapter
2241 * All ports of the adapter will be stopped if not already done.
2242 * Do a software reset and switch off all LEDs.
2248 SK_AC
*pAC
, /* adapter context */
2249 SK_IOC IoC
) /* IO context */
2255 /* ensure I2C is ready */
2256 SkI2cWaitIrq(pAC
, IoC
);
2259 /* stop all current transfer activity */
2260 for (i
= 0; i
< pAC
->GIni
.GIMacsFound
; i
++) {
2261 if (pAC
->GIni
.GP
[i
].PState
!= SK_PRT_STOP
&&
2262 pAC
->GIni
.GP
[i
].PState
!= SK_PRT_RESET
) {
2264 SkGeStopPort(pAC
, IoC
, i
, SK_STOP_ALL
, SK_HARD_RST
);
2268 /* Reset all bits in the PCI STATUS register */
2270 * Note: PCI Cfg cycles cannot be used, because they are not
2271 * available on some platforms after 'boot time'.
2273 SK_IN16(IoC
, PCI_C(PCI_STATUS
), &Word
);
2275 SK_OUT8(IoC
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2276 SK_OUT16(IoC
, PCI_C(PCI_STATUS
), Word
| PCI_ERRBITS
);
2277 SK_OUT8(IoC
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2279 /* do the reset, all LEDs are switched off now */
2280 SK_OUT8(IoC
, B0_CTST
, CS_RST_SET
);
2284 /******************************************************************************
2286 * SkGeInitPort() Initialize the specified port.
2289 * PRxQSize, PXSQSize, and PXAQSize has to be
2290 * configured for the specified port before calling this function.
2291 * The descriptor rings has to be initialized too.
2293 * o (Re)configure queues of the specified port.
2294 * o configure the MAC of the specified port.
2295 * o put ASIC and MAC(s) in operational mode.
2296 * o initialize Rx/Tx and Sync LED
2297 * o initialize RAM Buffers and MAC FIFOs
2299 * The port is ready to connect when returning.
2302 * The MAC's Rx and Tx state machine is still disabled when returning.
2306 * 1: Queue size initialization error. The configured values
2307 * for PRxQSize, PXSQSize, or PXAQSize are invalid for one
2308 * or more queues. The specified port was NOT initialized.
2309 * An error log entry was generated.
2310 * 2: The port has to be stopped before it can be initialized again.
2313 SK_AC
*pAC
, /* adapter context */
2314 SK_IOC IoC
, /* IO context */
2315 int Port
) /* Port to configure */
2319 pPrt
= &pAC
->GIni
.GP
[Port
];
2321 if (SkGeCheckQSize(pAC
, Port
) != 0) {
2322 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E004
, SKERR_HWI_E004MSG
);
2326 if (pPrt
->PState
== SK_PRT_INIT
|| pPrt
->PState
== SK_PRT_RUN
) {
2327 SK_ERR_LOG(pAC
, SK_ERRCL_SW
, SKERR_HWI_E005
, SKERR_HWI_E005MSG
);
2331 /* configuration ok, initialize the Port now */
2333 if (pAC
->GIni
.GIGenesis
) {
2334 /* initialize Rx, Tx and Link LED */
2336 * If 1000BT Phy needs LED initialization than swap
2337 * LED and XMAC initialization order
2339 SkGeXmitLED(pAC
, IoC
, MR_ADDR(Port
, TX_LED_INI
), SK_LED_ENA
);
2340 SkGeXmitLED(pAC
, IoC
, MR_ADDR(Port
, RX_LED_INI
), SK_LED_ENA
);
2341 /* The Link LED is initialized by RLMT or Diagnostics itself */
2343 SkXmInitMac(pAC
, IoC
, Port
);
2347 SkGmInitMac(pAC
, IoC
, Port
);
2350 /* do NOT initialize the Link Sync Counter */
2352 SkGeInitMacFifo(pAC
, IoC
, Port
);
2354 SkGeInitRamBufs(pAC
, IoC
, Port
);
2356 if (pPrt
->PXSQSize
!= 0) {
2357 /* enable Force Sync bit if synchronous queue available */
2358 SK_OUT8(IoC
, MR_ADDR(Port
, TXA_CTRL
), TXA_ENA_FSYNC
);
2361 SkGeInitBmu(pAC
, IoC
, Port
);
2363 /* mark port as initialized */
2364 pPrt
->PState
= SK_PRT_INIT
;
2367 } /* SkGeInitPort */