drivers/net/tsec.c

   1 /*
   2  * Freescale Three Speed Ethernet Controller driver
   3  *
   4  * This software may be used and distributed according to the
   5  * terms of the GNU Public License, Version 2, incorporated
   6  * herein by reference.
   7  *
   8  * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
   9  * (C) Copyright 2003, Motorola, Inc.
  10  * author Andy Fleming
  11  *
  12  */
  13
  14 #include <config.h>
  15 #include <common.h>
  16 #include <malloc.h>
  17 #include <net.h>
  18 #include <command.h>
  19 #include <tsec.h>
  20 #include <fsl_mdio.h>
  21 #include <asm/errno.h>
  22 #include <asm/processor.h>
  23 #include <asm/io.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 #define TX_BUF_CNT              2
  28
  29 static uint rx_idx;             /* index of the current RX buffer */
  30 static uint tx_idx;             /* index of the current TX buffer */
  31
  32 #ifdef __GNUC__
  33 static struct txbd8 __iomem txbd[TX_BUF_CNT] __aligned(8);
  34 static struct rxbd8 __iomem rxbd[PKTBUFSRX] __aligned(8);
  35
  36 #else
  37 #error "rtx must be 64-bit aligned"
  38 #endif
  39
  40 static int tsec_send(struct eth_device *dev, void *packet, int length);
  41
  42 /* Default initializations for TSEC controllers. */
  43
  44 static struct tsec_info_struct tsec_info[] = {
  45 #ifdef CONFIG_TSEC1
  46         STD_TSEC_INFO(1),       /* TSEC1 */
  47 #endif
  48 #ifdef CONFIG_TSEC2
  49         STD_TSEC_INFO(2),       /* TSEC2 */
  50 #endif
  51 #ifdef CONFIG_MPC85XX_FEC
  52         {
  53                 .regs = TSEC_GET_REGS(2, 0x2000),
  54                 .devname = CONFIG_MPC85XX_FEC_NAME,
  55                 .phyaddr = FEC_PHY_ADDR,
  56                 .flags = FEC_FLAGS,
  57                 .mii_devname = DEFAULT_MII_NAME
  58         },                      /* FEC */
  59 #endif
  60 #ifdef CONFIG_TSEC3
  61         STD_TSEC_INFO(3),       /* TSEC3 */
  62 #endif
  63 #ifdef CONFIG_TSEC4
  64         STD_TSEC_INFO(4),       /* TSEC4 */
  65 #endif
  66 };
  67
  68 #define TBIANA_SETTINGS ( \
  69                 TBIANA_ASYMMETRIC_PAUSE \
  70                 | TBIANA_SYMMETRIC_PAUSE \
  71                 | TBIANA_FULL_DUPLEX \
  72                 )
  73
  74 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
  75 #ifndef CONFIG_TSEC_TBICR_SETTINGS
  76 #define CONFIG_TSEC_TBICR_SETTINGS ( \
  77                 TBICR_PHY_RESET \
  78                 | TBICR_ANEG_ENABLE \
  79                 | TBICR_FULL_DUPLEX \
  80                 | TBICR_SPEED1_SET \
  81                 )
  82 #endif /* CONFIG_TSEC_TBICR_SETTINGS */
  83
  84 /* Configure the TBI for SGMII operation */
  85 static void tsec_configure_serdes(struct tsec_private *priv)
  86 {
  87         /* Access TBI PHY registers at given TSEC register offset as opposed
  88          * to the register offset used for external PHY accesses */
  89         tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  90                         0, TBI_ANA, TBIANA_SETTINGS);
  91         tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  92                         0, TBI_TBICON, TBICON_CLK_SELECT);
  93         tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  94                         0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
  95 }
  96
  97 #ifdef CONFIG_MCAST_TFTP
  98
  99 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
 100
 101 /* Set the appropriate hash bit for the given addr */
 102
 103 /* The algorithm works like so:
 104  * 1) Take the Destination Address (ie the multicast address), and
 105  * do a CRC on it (little endian), and reverse the bits of the
 106  * result.
 107  * 2) Use the 8 most significant bits as a hash into a 256-entry
 108  * table.  The table is controlled through 8 32-bit registers:
 109  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is entry
 110  * 255.  This means that the 3 most significant bits in the
 111  * hash index which gaddr register to use, and the 5 other bits
 112  * indicate which bit (assuming an IBM numbering scheme, which
 113  * for PowerPC (tm) is usually the case) in the register holds
 114  * the entry. */
 115 static int
 116 tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
 117 {
 118         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 119         struct tsec __iomem *regs = priv->regs;
 120         u32 result, value;
 121         u8 whichbit, whichreg;
 122
 123         result = ether_crc(MAC_ADDR_LEN, mcast_mac);
 124         whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
 125         whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
 126
 127         value = 1 << (31-whichbit);
 128
 129         if (set)
 130                 setbits_be32(&regs->hash.gaddr0 + whichreg, value);
 131         else
 132                 clrbits_be32(&regs->hash.gaddr0 + whichreg, value);
 133
 134         return 0;
 135 }
 136 #endif /* Multicast TFTP ? */
 137
 138 /* Initialized required registers to appropriate values, zeroing
 139  * those we don't care about (unless zero is bad, in which case,
 140  * choose a more appropriate value)
 141  */
 142 static void init_registers(struct tsec __iomem *regs)
 143 {
 144         /* Clear IEVENT */
 145         out_be32(&regs->ievent, IEVENT_INIT_CLEAR);
 146
 147         out_be32(&regs->imask, IMASK_INIT_CLEAR);
 148
 149         out_be32(&regs->hash.iaddr0, 0);
 150         out_be32(&regs->hash.iaddr1, 0);
 151         out_be32(&regs->hash.iaddr2, 0);
 152         out_be32(&regs->hash.iaddr3, 0);
 153         out_be32(&regs->hash.iaddr4, 0);
 154         out_be32(&regs->hash.iaddr5, 0);
 155         out_be32(&regs->hash.iaddr6, 0);
 156         out_be32(&regs->hash.iaddr7, 0);
 157
 158         out_be32(&regs->hash.gaddr0, 0);
 159         out_be32(&regs->hash.gaddr1, 0);
 160         out_be32(&regs->hash.gaddr2, 0);
 161         out_be32(&regs->hash.gaddr3, 0);
 162         out_be32(&regs->hash.gaddr4, 0);
 163         out_be32(&regs->hash.gaddr5, 0);
 164         out_be32(&regs->hash.gaddr6, 0);
 165         out_be32(&regs->hash.gaddr7, 0);
 166
 167         out_be32(&regs->rctrl, 0x00000000);
 168
 169         /* Init RMON mib registers */
 170         memset((void *)&regs->rmon, 0, sizeof(regs->rmon));
 171
 172         out_be32(&regs->rmon.cam1, 0xffffffff);
 173         out_be32(&regs->rmon.cam2, 0xffffffff);
 174
 175         out_be32(&regs->mrblr, MRBLR_INIT_SETTINGS);
 176
 177         out_be32(&regs->minflr, MINFLR_INIT_SETTINGS);
 178
 179         out_be32(&regs->attr, ATTR_INIT_SETTINGS);
 180         out_be32(&regs->attreli, ATTRELI_INIT_SETTINGS);
 181
 182 }
 183
 184 /* Configure maccfg2 based on negotiated speed and duplex
 185  * reported by PHY handling code
 186  */
 187 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
 188 {
 189         struct tsec __iomem *regs = priv->regs;
 190         u32 ecntrl, maccfg2;
 191
 192         if (!phydev->link) {
 193                 printf("%s: No link.\n", phydev->dev->name);
 194                 return;
 195         }
 196
 197         /* clear all bits relative with interface mode */
 198         ecntrl = in_be32(&regs->ecntrl);
 199         ecntrl &= ~ECNTRL_R100;
 200
 201         maccfg2 = in_be32(&regs->maccfg2);
 202         maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
 203
 204         if (phydev->duplex)
 205                 maccfg2 |= MACCFG2_FULL_DUPLEX;
 206
 207         switch (phydev->speed) {
 208         case 1000:
 209                 maccfg2 |= MACCFG2_GMII;
 210                 break;
 211         case 100:
 212         case 10:
 213                 maccfg2 |= MACCFG2_MII;
 214
 215                 /* Set R100 bit in all modes although
 216                  * it is only used in RGMII mode
 217                  */
 218                 if (phydev->speed == 100)
 219                         ecntrl |= ECNTRL_R100;
 220                 break;
 221         default:
 222                 printf("%s: Speed was bad\n", phydev->dev->name);
 223                 break;
 224         }
 225
 226         out_be32(&regs->ecntrl, ecntrl);
 227         out_be32(&regs->maccfg2, maccfg2);
 228
 229         printf("Speed: %d, %s duplex%s\n", phydev->speed,
 230                         (phydev->duplex) ? "full" : "half",
 231                         (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
 232 }
 233
 234 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 235 /*
 236  * When MACCFG1[Rx_EN] is enabled during system boot as part
 237  * of the eTSEC port initialization sequence,
 238  * the eTSEC Rx logic may not be properly initialized.
 239  */
 240 void redundant_init(struct eth_device *dev)
 241 {
 242         struct tsec_private *priv = dev->priv;
 243         struct tsec __iomem *regs = priv->regs;
 244         uint t, count = 0;
 245         int fail = 1;
 246         static const u8 pkt[] = {
 247                 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
 248                 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
 249                 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
 250                 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
 251                 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
 252                 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
 253                 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
 254                 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
 255                 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
 256                 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
 257                 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
 258                 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
 259                 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
 260                 0x71, 0x72};
 261
 262         /* Enable promiscuous mode */
 263         setbits_be32(&regs->rctrl, 0x8);
 264         /* Enable loopback mode */
 265         setbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
 266         /* Enable transmit and receive */
 267         setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
 268
 269         /* Tell the DMA it is clear to go */
 270         setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
 271         out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
 272         out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 273         clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
 274
 275         do {
 276                 uint16_t status;
 277                 tsec_send(dev, (void *)pkt, sizeof(pkt));
 278
 279                 /* Wait for buffer to be received */
 280                 for (t = 0; in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY; t++) {
 281                         if (t >= 10 * TOUT_LOOP) {
 282                                 printf("%s: tsec: rx error\n", dev->name);
 283                                 break;
 284                         }
 285                 }
 286
 287                 if (!memcmp(pkt, (void *)net_rx_packets[rx_idx], sizeof(pkt)))
 288                         fail = 0;
 289
 290                 out_be16(&rxbd[rx_idx].length, 0);
 291                 status = RXBD_EMPTY;
 292                 if ((rx_idx + 1) == PKTBUFSRX)
 293                         status |= RXBD_WRAP;
 294                 out_be16(&rxbd[rx_idx].status, status);
 295                 rx_idx = (rx_idx + 1) % PKTBUFSRX;
 296
 297                 if (in_be32(&regs->ievent) & IEVENT_BSY) {
 298                         out_be32(&regs->ievent, IEVENT_BSY);
 299                         out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 300                 }
 301                 if (fail) {
 302                         printf("loopback recv packet error!\n");
 303                         clrbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
 304                         udelay(1000);
 305                         setbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
 306                 }
 307         } while ((count++ < 4) && (fail == 1));
 308
 309         if (fail)
 310                 panic("eTSEC init fail!\n");
 311         /* Disable promiscuous mode */
 312         clrbits_be32(&regs->rctrl, 0x8);
 313         /* Disable loopback mode */
 314         clrbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
 315 }
 316 #endif
 317
 318 /* Set up the buffers and their descriptors, and bring up the
 319  * interface
 320  */
 321 static void startup_tsec(struct eth_device *dev)
 322 {
 323         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 324         struct tsec __iomem *regs = priv->regs;
 325         uint16_t status;
 326         int i;
 327
 328         /* reset the indices to zero */
 329         rx_idx = 0;
 330         tx_idx = 0;
 331 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 332         uint svr;
 333 #endif
 334
 335         /* Point to the buffer descriptors */
 336         out_be32(&regs->tbase, (u32)&txbd[0]);
 337         out_be32(&regs->rbase, (u32)&rxbd[0]);
 338
 339         /* Initialize the Rx Buffer descriptors */
 340         for (i = 0; i < PKTBUFSRX; i++) {
 341                 out_be16(&rxbd[i].status, RXBD_EMPTY);
 342                 out_be16(&rxbd[i].length, 0);
 343                 out_be32(&rxbd[i].bufptr, (u32)net_rx_packets[i]);
 344         }
 345         status = in_be16(&rxbd[PKTBUFSRX - 1].status);
 346         out_be16(&rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
 347
 348         /* Initialize the TX Buffer Descriptors */
 349         for (i = 0; i < TX_BUF_CNT; i++) {
 350                 out_be16(&txbd[i].status, 0);
 351                 out_be16(&txbd[i].length, 0);
 352                 out_be32(&txbd[i].bufptr, 0);
 353         }
 354         status = in_be16(&txbd[TX_BUF_CNT - 1].status);
 355         out_be16(&txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
 356
 357 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 358         svr = get_svr();
 359         if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
 360                 redundant_init(dev);
 361 #endif
 362         /* Enable Transmit and Receive */
 363         setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
 364
 365         /* Tell the DMA it is clear to go */
 366         setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
 367         out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
 368         out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 369         clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
 370 }
 371
 372 /* This returns the status bits of the device.  The return value
 373  * is never checked, and this is what the 8260 driver did, so we
 374  * do the same.  Presumably, this would be zero if there were no
 375  * errors
 376  */
 377 static int tsec_send(struct eth_device *dev, void *packet, int length)
 378 {
 379         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 380         struct tsec __iomem *regs = priv->regs;
 381         uint16_t status;
 382         int result = 0;
 383         int i;
 384
 385         /* Find an empty buffer descriptor */
 386         for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) {
 387                 if (i >= TOUT_LOOP) {
 388                         debug("%s: tsec: tx buffers full\n", dev->name);
 389                         return result;
 390                 }
 391         }
 392
 393         out_be32(&txbd[tx_idx].bufptr, (u32)packet);
 394         out_be16(&txbd[tx_idx].length, length);
 395         status = in_be16(&txbd[tx_idx].status);
 396         out_be16(&txbd[tx_idx].status, status |
 397                 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
 398
 399         /* Tell the DMA to go */
 400         out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
 401
 402         /* Wait for buffer to be transmitted */
 403         for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) {
 404                 if (i >= TOUT_LOOP) {
 405                         debug("%s: tsec: tx error\n", dev->name);
 406                         return result;
 407                 }
 408         }
 409
 410         tx_idx = (tx_idx + 1) % TX_BUF_CNT;
 411         result = in_be16(&txbd[tx_idx].status) & TXBD_STATS;
 412
 413         return result;
 414 }
 415
 416 static int tsec_recv(struct eth_device *dev)
 417 {
 418         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 419         struct tsec __iomem *regs = priv->regs;
 420
 421         while (!(in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY)) {
 422                 int length = in_be16(&rxbd[rx_idx].length);
 423                 uint16_t status = in_be16(&rxbd[rx_idx].status);
 424
 425                 /* Send the packet up if there were no errors */
 426                 if (!(status & RXBD_STATS))
 427                         net_process_received_packet(net_rx_packets[rx_idx],
 428                                                     length - 4);
 429                 else
 430                         printf("Got error %x\n", (status & RXBD_STATS));
 431
 432                 out_be16(&rxbd[rx_idx].length, 0);
 433
 434                 status = RXBD_EMPTY;
 435                 /* Set the wrap bit if this is the last element in the list */
 436                 if ((rx_idx + 1) == PKTBUFSRX)
 437                         status |= RXBD_WRAP;
 438                 out_be16(&rxbd[rx_idx].status, status);
 439
 440                 rx_idx = (rx_idx + 1) % PKTBUFSRX;
 441         }
 442
 443         if (in_be32(&regs->ievent) & IEVENT_BSY) {
 444                 out_be32(&regs->ievent, IEVENT_BSY);
 445                 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 446         }
 447
 448         return -1;
 449
 450 }
 451
 452 /* Stop the interface */
 453 static void tsec_halt(struct eth_device *dev)
 454 {
 455         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 456         struct tsec __iomem *regs = priv->regs;
 457
 458         clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
 459         setbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
 460
 461         while ((in_be32(&regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
 462                         != (IEVENT_GRSC | IEVENT_GTSC))
 463                 ;
 464
 465         clrbits_be32(&regs->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
 466
 467         /* Shut down the PHY, as needed */
 468         phy_shutdown(priv->phydev);
 469 }
 470
 471 /* Initializes data structures and registers for the controller,
 472  * and brings the interface up.  Returns the link status, meaning
 473  * that it returns success if the link is up, failure otherwise.
 474  * This allows u-boot to find the first active controller.
 475  */
 476 static int tsec_init(struct eth_device *dev, bd_t * bd)
 477 {
 478         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 479         struct tsec __iomem *regs = priv->regs;
 480         u32 tempval;
 481         int ret;
 482
 483         /* Make sure the controller is stopped */
 484         tsec_halt(dev);
 485
 486         /* Init MACCFG2.  Defaults to GMII */
 487         out_be32(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
 488
 489         /* Init ECNTRL */
 490         out_be32(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
 491
 492         /* Copy the station address into the address registers.
 493          * For a station address of 0x12345678ABCD in transmission
 494          * order (BE), MACnADDR1 is set to 0xCDAB7856 and
 495          * MACnADDR2 is set to 0x34120000.
 496          */
 497         tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
 498                   (dev->enetaddr[3] << 8)  |  dev->enetaddr[2];
 499
 500         out_be32(&regs->macstnaddr1, tempval);
 501
 502         tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
 503
 504         out_be32(&regs->macstnaddr2, tempval);
 505
 506         /* Clear out (for the most part) the other registers */
 507         init_registers(regs);
 508
 509         /* Ready the device for tx/rx */
 510         startup_tsec(dev);
 511
 512         /* Start up the PHY */
 513         ret = phy_startup(priv->phydev);
 514         if (ret) {
 515                 printf("Could not initialize PHY %s\n",
 516                        priv->phydev->dev->name);
 517                 return ret;
 518         }
 519
 520         adjust_link(priv, priv->phydev);
 521
 522         /* If there's no link, fail */
 523         return priv->phydev->link ? 0 : -1;
 524 }
 525
 526 static phy_interface_t tsec_get_interface(struct tsec_private *priv)
 527 {
 528         struct tsec __iomem *regs = priv->regs;
 529         u32 ecntrl;
 530
 531         ecntrl = in_be32(&regs->ecntrl);
 532
 533         if (ecntrl & ECNTRL_SGMII_MODE)
 534                 return PHY_INTERFACE_MODE_SGMII;
 535
 536         if (ecntrl & ECNTRL_TBI_MODE) {
 537                 if (ecntrl & ECNTRL_REDUCED_MODE)
 538                         return PHY_INTERFACE_MODE_RTBI;
 539                 else
 540                         return PHY_INTERFACE_MODE_TBI;
 541         }
 542
 543         if (ecntrl & ECNTRL_REDUCED_MODE) {
 544                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
 545                         return PHY_INTERFACE_MODE_RMII;
 546                 else {
 547                         phy_interface_t interface = priv->interface;
 548
 549                         /*
 550                          * This isn't autodetected, so it must
 551                          * be set by the platform code.
 552                          */
 553                         if ((interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 554                                  (interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
 555                                  (interface == PHY_INTERFACE_MODE_RGMII_RXID))
 556                                 return interface;
 557
 558                         return PHY_INTERFACE_MODE_RGMII;
 559                 }
 560         }
 561
 562         if (priv->flags & TSEC_GIGABIT)
 563                 return PHY_INTERFACE_MODE_GMII;
 564
 565         return PHY_INTERFACE_MODE_MII;
 566 }
 567
 568
 569 /* Discover which PHY is attached to the device, and configure it
 570  * properly.  If the PHY is not recognized, then return 0
 571  * (failure).  Otherwise, return 1
 572  */
 573 static int init_phy(struct eth_device *dev)
 574 {
 575         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 576         struct phy_device *phydev;
 577         struct tsec __iomem *regs = priv->regs;
 578         u32 supported = (SUPPORTED_10baseT_Half |
 579                         SUPPORTED_10baseT_Full |
 580                         SUPPORTED_100baseT_Half |
 581                         SUPPORTED_100baseT_Full);
 582
 583         if (priv->flags & TSEC_GIGABIT)
 584                 supported |= SUPPORTED_1000baseT_Full;
 585
 586         /* Assign a Physical address to the TBI */
 587         out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);
 588
 589         priv->interface = tsec_get_interface(priv);
 590
 591         if (priv->interface == PHY_INTERFACE_MODE_SGMII)
 592                 tsec_configure_serdes(priv);
 593
 594         phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
 595         if (!phydev)
 596                 return 0;
 597
 598         phydev->supported &= supported;
 599         phydev->advertising = phydev->supported;
 600
 601         priv->phydev = phydev;
 602
 603         phy_config(phydev);
 604
 605         return 1;
 606 }
 607
 608 /* Initialize device structure. Returns success if PHY
 609  * initialization succeeded (i.e. if it recognizes the PHY)
 610  */
 611 static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
 612 {
 613         struct eth_device *dev;
 614         int i;
 615         struct tsec_private *priv;
 616
 617         dev = (struct eth_device *)malloc(sizeof *dev);
 618
 619         if (NULL == dev)
 620                 return 0;
 621
 622         memset(dev, 0, sizeof *dev);
 623
 624         priv = (struct tsec_private *)malloc(sizeof(*priv));
 625
 626         if (NULL == priv)
 627                 return 0;
 628
 629         priv->regs = tsec_info->regs;
 630         priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
 631
 632         priv->phyaddr = tsec_info->phyaddr;
 633         priv->flags = tsec_info->flags;
 634
 635         sprintf(dev->name, tsec_info->devname);
 636         priv->interface = tsec_info->interface;
 637         priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
 638         dev->iobase = 0;
 639         dev->priv = priv;
 640         dev->init = tsec_init;
 641         dev->halt = tsec_halt;
 642         dev->send = tsec_send;
 643         dev->recv = tsec_recv;
 644 #ifdef CONFIG_MCAST_TFTP
 645         dev->mcast = tsec_mcast_addr;
 646 #endif
 647
 648         /* Tell u-boot to get the addr from the env */
 649         for (i = 0; i < 6; i++)
 650                 dev->enetaddr[i] = 0;
 651
 652         eth_register(dev);
 653
 654         /* Reset the MAC */
 655         setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
 656         udelay(2);  /* Soft Reset must be asserted for 3 TX clocks */
 657         clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
 658
 659         /* Try to initialize PHY here, and return */
 660         return init_phy(dev);
 661 }
 662
 663 /*
 664  * Initialize all the TSEC devices
 665  *
 666  * Returns the number of TSEC devices that were initialized
 667  */
 668 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
 669 {
 670         int i;
 671         int ret, count = 0;
 672
 673         for (i = 0; i < num; i++) {
 674                 ret = tsec_initialize(bis, &tsecs[i]);
 675                 if (ret > 0)
 676                         count += ret;
 677         }
 678
 679         return count;
 680 }
 681
 682 int tsec_standard_init(bd_t *bis)
 683 {
 684         struct fsl_pq_mdio_info info;
 685
 686         info.regs = TSEC_GET_MDIO_REGS_BASE(1);
 687         info.name = DEFAULT_MII_NAME;
 688
 689         fsl_pq_mdio_init(bis, &info);
 690
 691         return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
 692 }