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[people/ms/u-boot.git] / drivers / net / tsec.c
1 /*
2 * Freescale Three Speed Ethernet Controller driver
3 *
4 * This software may be used and distributed according to the
5 * terms of the GNU Public License, Version 2, incorporated
6 * herein by reference.
7 *
8 * Copyright 2004, 2007 Freescale Semiconductor, Inc.
9 * (C) Copyright 2003, Motorola, Inc.
10 * author Andy Fleming
11 *
12 */
13
14 #include <config.h>
15 #include <common.h>
16 #include <malloc.h>
17 #include <net.h>
18 #include <command.h>
19
20 #include "tsec.h"
21 #include "miiphy.h"
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 #define TX_BUF_CNT 2
26
27 static uint rxIdx; /* index of the current RX buffer */
28 static uint txIdx; /* index of the current TX buffer */
29
30 typedef volatile struct rtxbd {
31 txbd8_t txbd[TX_BUF_CNT];
32 rxbd8_t rxbd[PKTBUFSRX];
33 } RTXBD;
34
35 struct tsec_info_struct {
36 unsigned int phyaddr;
37 u32 flags;
38 unsigned int phyregidx;
39 };
40
41 /* The tsec_info structure contains 3 values which the
42 * driver uses to determine how to operate a given ethernet
43 * device. The information needed is:
44 * phyaddr - The address of the PHY which is attached to
45 * the given device.
46 *
47 * flags - This variable indicates whether the device
48 * supports gigabit speed ethernet, and whether it should be
49 * in reduced mode.
50 *
51 * phyregidx - This variable specifies which ethernet device
52 * controls the MII Management registers which are connected
53 * to the PHY. For now, only TSEC1 (index 0) has
54 * access to the PHYs, so all of the entries have "0".
55 *
56 * The values specified in the table are taken from the board's
57 * config file in include/configs/. When implementing a new
58 * board with ethernet capability, it is necessary to define:
59 * TSECn_PHY_ADDR
60 * TSECn_PHYIDX
61 *
62 * for n = 1,2,3, etc. And for FEC:
63 * FEC_PHY_ADDR
64 * FEC_PHYIDX
65 */
66 static struct tsec_info_struct tsec_info[] = {
67 #ifdef CONFIG_TSEC1
68 {TSEC1_PHY_ADDR, TSEC1_FLAGS, TSEC1_PHYIDX},
69 #else
70 {0, 0, 0},
71 #endif
72 #ifdef CONFIG_TSEC2
73 {TSEC2_PHY_ADDR, TSEC2_FLAGS, TSEC2_PHYIDX},
74 #else
75 {0, 0, 0},
76 #endif
77 #ifdef CONFIG_MPC85XX_FEC
78 {FEC_PHY_ADDR, FEC_FLAGS, FEC_PHYIDX},
79 #else
80 #ifdef CONFIG_TSEC3
81 {TSEC3_PHY_ADDR, TSEC3_FLAGS, TSEC3_PHYIDX},
82 #else
83 {0, 0, 0},
84 #endif
85 #ifdef CONFIG_TSEC4
86 {TSEC4_PHY_ADDR, TSEC4_FLAGS, TSEC4_PHYIDX},
87 #else
88 {0, 0, 0},
89 #endif /* CONFIG_TSEC4 */
90 #endif /* CONFIG_MPC85XX_FEC */
91 };
92
93 #define MAXCONTROLLERS (4)
94
95 static int relocated = 0;
96
97 static struct tsec_private *privlist[MAXCONTROLLERS];
98
99 #ifdef __GNUC__
100 static RTXBD rtx __attribute__ ((aligned(8)));
101 #else
102 #error "rtx must be 64-bit aligned"
103 #endif
104
105 static int tsec_send(struct eth_device *dev,
106 volatile void *packet, int length);
107 static int tsec_recv(struct eth_device *dev);
108 static int tsec_init(struct eth_device *dev, bd_t * bd);
109 static void tsec_halt(struct eth_device *dev);
110 static void init_registers(volatile tsec_t * regs);
111 static void startup_tsec(struct eth_device *dev);
112 static int init_phy(struct eth_device *dev);
113 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
114 uint read_phy_reg(struct tsec_private *priv, uint regnum);
115 struct phy_info *get_phy_info(struct eth_device *dev);
116 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
117 static void adjust_link(struct eth_device *dev);
118 static void relocate_cmds(void);
119 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
120 && !defined(BITBANGMII)
121 static int tsec_miiphy_write(char *devname, unsigned char addr,
122 unsigned char reg, unsigned short value);
123 static int tsec_miiphy_read(char *devname, unsigned char addr,
124 unsigned char reg, unsigned short *value);
125 #endif
126 #ifdef CONFIG_MCAST_TFTP
127 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set);
128 #endif
129
130 /* Initialize device structure. Returns success if PHY
131 * initialization succeeded (i.e. if it recognizes the PHY)
132 */
133 int tsec_initialize(bd_t * bis, int index, char *devname)
134 {
135 struct eth_device *dev;
136 int i;
137 struct tsec_private *priv;
138
139 dev = (struct eth_device *)malloc(sizeof *dev);
140
141 if (NULL == dev)
142 return 0;
143
144 memset(dev, 0, sizeof *dev);
145
146 priv = (struct tsec_private *)malloc(sizeof(*priv));
147
148 if (NULL == priv)
149 return 0;
150
151 privlist[index] = priv;
152 priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE);
153 priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
154 tsec_info[index].phyregidx *
155 TSEC_SIZE);
156
157 priv->phyaddr = tsec_info[index].phyaddr;
158 priv->flags = tsec_info[index].flags;
159
160 sprintf(dev->name, devname);
161 dev->iobase = 0;
162 dev->priv = priv;
163 dev->init = tsec_init;
164 dev->halt = tsec_halt;
165 dev->send = tsec_send;
166 dev->recv = tsec_recv;
167 #ifdef CONFIG_MCAST_TFTP
168 dev->mcast = tsec_mcast_addr;
169 #endif
170
171 /* Tell u-boot to get the addr from the env */
172 for (i = 0; i < 6; i++)
173 dev->enetaddr[i] = 0;
174
175 eth_register(dev);
176
177 /* Reset the MAC */
178 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
179 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
180
181 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
182 && !defined(BITBANGMII)
183 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
184 #endif
185
186 /* Try to initialize PHY here, and return */
187 return init_phy(dev);
188 }
189
190 /* Initializes data structures and registers for the controller,
191 * and brings the interface up. Returns the link status, meaning
192 * that it returns success if the link is up, failure otherwise.
193 * This allows u-boot to find the first active controller.
194 */
195 int tsec_init(struct eth_device *dev, bd_t * bd)
196 {
197 uint tempval;
198 char tmpbuf[MAC_ADDR_LEN];
199 int i;
200 struct tsec_private *priv = (struct tsec_private *)dev->priv;
201 volatile tsec_t *regs = priv->regs;
202
203 /* Make sure the controller is stopped */
204 tsec_halt(dev);
205
206 /* Init MACCFG2. Defaults to GMII */
207 regs->maccfg2 = MACCFG2_INIT_SETTINGS;
208
209 /* Init ECNTRL */
210 regs->ecntrl = ECNTRL_INIT_SETTINGS;
211
212 /* Copy the station address into the address registers.
213 * Backwards, because little endian MACS are dumb */
214 for (i = 0; i < MAC_ADDR_LEN; i++) {
215 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
216 }
217 regs->macstnaddr1 = *((uint *) (tmpbuf));
218
219 tempval = *((uint *) (tmpbuf + 4));
220
221 regs->macstnaddr2 = tempval;
222
223 /* reset the indices to zero */
224 rxIdx = 0;
225 txIdx = 0;
226
227 /* Clear out (for the most part) the other registers */
228 init_registers(regs);
229
230 /* Ready the device for tx/rx */
231 startup_tsec(dev);
232
233 /* If there's no link, fail */
234 return (priv->link ? 0 : -1);
235
236 }
237
238 /* Write value to the device's PHY through the registers
239 * specified in priv, modifying the register specified in regnum.
240 * It will wait for the write to be done (or for a timeout to
241 * expire) before exiting
242 */
243 void write_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum, uint value)
244 {
245 volatile tsec_t *regbase = priv->phyregs;
246 int timeout = 1000000;
247
248 regbase->miimadd = (phyid << 8) | regnum;
249 regbase->miimcon = value;
250 asm("sync");
251
252 timeout = 1000000;
253 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
254 }
255
256 /* #define to provide old write_phy_reg functionality without duplicating code */
257 #define write_phy_reg(priv, regnum, value) write_any_phy_reg(priv,priv->phyaddr,regnum,value)
258
259 /* Reads register regnum on the device's PHY through the
260 * registers specified in priv. It lowers and raises the read
261 * command, and waits for the data to become valid (miimind
262 * notvalid bit cleared), and the bus to cease activity (miimind
263 * busy bit cleared), and then returns the value
264 */
265 uint read_any_phy_reg(struct tsec_private *priv, uint phyid, uint regnum)
266 {
267 uint value;
268 volatile tsec_t *regbase = priv->phyregs;
269
270 /* Put the address of the phy, and the register
271 * number into MIIMADD */
272 regbase->miimadd = (phyid << 8) | regnum;
273
274 /* Clear the command register, and wait */
275 regbase->miimcom = 0;
276 asm("sync");
277
278 /* Initiate a read command, and wait */
279 regbase->miimcom = MIIM_READ_COMMAND;
280 asm("sync");
281
282 /* Wait for the the indication that the read is done */
283 while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
284
285 /* Grab the value read from the PHY */
286 value = regbase->miimstat;
287
288 return value;
289 }
290
291 /* #define to provide old read_phy_reg functionality without duplicating code */
292 #define read_phy_reg(priv,regnum) read_any_phy_reg(priv,priv->phyaddr,regnum)
293
294 /* Discover which PHY is attached to the device, and configure it
295 * properly. If the PHY is not recognized, then return 0
296 * (failure). Otherwise, return 1
297 */
298 static int init_phy(struct eth_device *dev)
299 {
300 struct tsec_private *priv = (struct tsec_private *)dev->priv;
301 struct phy_info *curphy;
302 volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
303
304 /* Assign a Physical address to the TBI */
305 regs->tbipa = CFG_TBIPA_VALUE;
306 regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
307 regs->tbipa = CFG_TBIPA_VALUE;
308 asm("sync");
309
310 /* Reset MII (due to new addresses) */
311 priv->phyregs->miimcfg = MIIMCFG_RESET;
312 asm("sync");
313 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
314 asm("sync");
315 while (priv->phyregs->miimind & MIIMIND_BUSY) ;
316
317 if (0 == relocated)
318 relocate_cmds();
319
320 /* Get the cmd structure corresponding to the attached
321 * PHY */
322 curphy = get_phy_info(dev);
323
324 if (curphy == NULL) {
325 priv->phyinfo = NULL;
326 printf("%s: No PHY found\n", dev->name);
327
328 return 0;
329 }
330
331 priv->phyinfo = curphy;
332
333 phy_run_commands(priv, priv->phyinfo->config);
334
335 return 1;
336 }
337
338 /*
339 * Returns which value to write to the control register.
340 * For 10/100, the value is slightly different
341 */
342 uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
343 {
344 if (priv->flags & TSEC_GIGABIT)
345 return MIIM_CONTROL_INIT;
346 else
347 return MIIM_CR_INIT;
348 }
349
350 /* Parse the status register for link, and then do
351 * auto-negotiation
352 */
353 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
354 {
355 /*
356 * Wait if the link is up, and autonegotiation is in progress
357 * (ie - we're capable and it's not done)
358 */
359 mii_reg = read_phy_reg(priv, MIIM_STATUS);
360 if ((mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE)
361 && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
362 int i = 0;
363
364 puts("Waiting for PHY auto negotiation to complete");
365 while (!(mii_reg & PHY_BMSR_AUTN_COMP)) {
366 /*
367 * Timeout reached ?
368 */
369 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
370 puts(" TIMEOUT !\n");
371 priv->link = 0;
372 return 0;
373 }
374
375 if ((i++ % 1000) == 0) {
376 putc('.');
377 }
378 udelay(1000); /* 1 ms */
379 mii_reg = read_phy_reg(priv, MIIM_STATUS);
380 }
381 puts(" done\n");
382 priv->link = 1;
383 udelay(500000); /* another 500 ms (results in faster booting) */
384 } else {
385 if (mii_reg & MIIM_STATUS_LINK)
386 priv->link = 1;
387 else
388 priv->link = 0;
389 }
390
391 return 0;
392 }
393
394 /* Generic function which updates the speed and duplex. If
395 * autonegotiation is enabled, it uses the AND of the link
396 * partner's advertised capabilities and our advertised
397 * capabilities. If autonegotiation is disabled, we use the
398 * appropriate bits in the control register.
399 *
400 * Stolen from Linux's mii.c and phy_device.c
401 */
402 uint mii_parse_link(uint mii_reg, struct tsec_private *priv)
403 {
404 /* We're using autonegotiation */
405 if (mii_reg & PHY_BMSR_AUTN_ABLE) {
406 uint lpa = 0;
407 uint gblpa = 0;
408
409 /* Check for gigabit capability */
410 if (mii_reg & PHY_BMSR_EXT) {
411 /* We want a list of states supported by
412 * both PHYs in the link
413 */
414 gblpa = read_phy_reg(priv, PHY_1000BTSR);
415 gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2;
416 }
417
418 /* Set the baseline so we only have to set them
419 * if they're different
420 */
421 priv->speed = 10;
422 priv->duplexity = 0;
423
424 /* Check the gigabit fields */
425 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
426 priv->speed = 1000;
427
428 if (gblpa & PHY_1000BTSR_1000FD)
429 priv->duplexity = 1;
430
431 /* We're done! */
432 return 0;
433 }
434
435 lpa = read_phy_reg(priv, PHY_ANAR);
436 lpa &= read_phy_reg(priv, PHY_ANLPAR);
437
438 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) {
439 priv->speed = 100;
440
441 if (lpa & PHY_ANLPAR_TXFD)
442 priv->duplexity = 1;
443
444 } else if (lpa & PHY_ANLPAR_10FD)
445 priv->duplexity = 1;
446 } else {
447 uint bmcr = read_phy_reg(priv, PHY_BMCR);
448
449 priv->speed = 10;
450 priv->duplexity = 0;
451
452 if (bmcr & PHY_BMCR_DPLX)
453 priv->duplexity = 1;
454
455 if (bmcr & PHY_BMCR_1000_MBPS)
456 priv->speed = 1000;
457 else if (bmcr & PHY_BMCR_100_MBPS)
458 priv->speed = 100;
459 }
460
461 return 0;
462 }
463
464 /*
465 * Parse the BCM54xx status register for speed and duplex information.
466 * The linux sungem_phy has this information, but in a table format.
467 */
468 uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv)
469 {
470
471 switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){
472
473 case 1:
474 printf("Enet starting in 10BT/HD\n");
475 priv->duplexity = 0;
476 priv->speed = 10;
477 break;
478
479 case 2:
480 printf("Enet starting in 10BT/FD\n");
481 priv->duplexity = 1;
482 priv->speed = 10;
483 break;
484
485 case 3:
486 printf("Enet starting in 100BT/HD\n");
487 priv->duplexity = 0;
488 priv->speed = 100;
489 break;
490
491 case 5:
492 printf("Enet starting in 100BT/FD\n");
493 priv->duplexity = 1;
494 priv->speed = 100;
495 break;
496
497 case 6:
498 printf("Enet starting in 1000BT/HD\n");
499 priv->duplexity = 0;
500 priv->speed = 1000;
501 break;
502
503 case 7:
504 printf("Enet starting in 1000BT/FD\n");
505 priv->duplexity = 1;
506 priv->speed = 1000;
507 break;
508
509 default:
510 printf("Auto-neg error, defaulting to 10BT/HD\n");
511 priv->duplexity = 0;
512 priv->speed = 10;
513 break;
514 }
515
516 return 0;
517
518 }
519 /* Parse the 88E1011's status register for speed and duplex
520 * information
521 */
522 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
523 {
524 uint speed;
525
526 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
527
528 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) &&
529 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
530 int i = 0;
531
532 puts("Waiting for PHY realtime link");
533 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
534 /* Timeout reached ? */
535 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
536 puts(" TIMEOUT !\n");
537 priv->link = 0;
538 break;
539 }
540
541 if ((i++ % 1000) == 0) {
542 putc('.');
543 }
544 udelay(1000); /* 1 ms */
545 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
546 }
547 puts(" done\n");
548 udelay(500000); /* another 500 ms (results in faster booting) */
549 } else {
550 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK)
551 priv->link = 1;
552 else
553 priv->link = 0;
554 }
555
556 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
557 priv->duplexity = 1;
558 else
559 priv->duplexity = 0;
560
561 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
562
563 switch (speed) {
564 case MIIM_88E1011_PHYSTAT_GBIT:
565 priv->speed = 1000;
566 break;
567 case MIIM_88E1011_PHYSTAT_100:
568 priv->speed = 100;
569 break;
570 default:
571 priv->speed = 10;
572 }
573
574 return 0;
575 }
576
577 /* Parse the RTL8211B's status register for speed and duplex
578 * information
579 */
580 uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv)
581 {
582 uint speed;
583
584 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS);
585 if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
586 int i = 0;
587
588 /* in case of timeout ->link is cleared */
589 priv->link = 1;
590 puts("Waiting for PHY realtime link");
591 while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
592 /* Timeout reached ? */
593 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
594 puts(" TIMEOUT !\n");
595 priv->link = 0;
596 break;
597 }
598
599 if ((i++ % 1000) == 0) {
600 putc('.');
601 }
602 udelay(1000); /* 1 ms */
603 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS);
604 }
605 puts(" done\n");
606 udelay(500000); /* another 500 ms (results in faster booting) */
607 } else {
608 if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK)
609 priv->link = 1;
610 else
611 priv->link = 0;
612 }
613
614 if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX)
615 priv->duplexity = 1;
616 else
617 priv->duplexity = 0;
618
619 speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED);
620
621 switch (speed) {
622 case MIIM_RTL8211B_PHYSTAT_GBIT:
623 priv->speed = 1000;
624 break;
625 case MIIM_RTL8211B_PHYSTAT_100:
626 priv->speed = 100;
627 break;
628 default:
629 priv->speed = 10;
630 }
631
632 return 0;
633 }
634
635 /* Parse the cis8201's status register for speed and duplex
636 * information
637 */
638 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
639 {
640 uint speed;
641
642 if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
643 priv->duplexity = 1;
644 else
645 priv->duplexity = 0;
646
647 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
648 switch (speed) {
649 case MIIM_CIS8201_AUXCONSTAT_GBIT:
650 priv->speed = 1000;
651 break;
652 case MIIM_CIS8201_AUXCONSTAT_100:
653 priv->speed = 100;
654 break;
655 default:
656 priv->speed = 10;
657 break;
658 }
659
660 return 0;
661 }
662
663 /* Parse the vsc8244's status register for speed and duplex
664 * information
665 */
666 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
667 {
668 uint speed;
669
670 if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
671 priv->duplexity = 1;
672 else
673 priv->duplexity = 0;
674
675 speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
676 switch (speed) {
677 case MIIM_VSC8244_AUXCONSTAT_GBIT:
678 priv->speed = 1000;
679 break;
680 case MIIM_VSC8244_AUXCONSTAT_100:
681 priv->speed = 100;
682 break;
683 default:
684 priv->speed = 10;
685 break;
686 }
687
688 return 0;
689 }
690
691 /* Parse the DM9161's status register for speed and duplex
692 * information
693 */
694 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
695 {
696 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
697 priv->speed = 100;
698 else
699 priv->speed = 10;
700
701 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
702 priv->duplexity = 1;
703 else
704 priv->duplexity = 0;
705
706 return 0;
707 }
708
709 /*
710 * Hack to write all 4 PHYs with the LED values
711 */
712 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
713 {
714 uint phyid;
715 volatile tsec_t *regbase = priv->phyregs;
716 int timeout = 1000000;
717
718 for (phyid = 0; phyid < 4; phyid++) {
719 regbase->miimadd = (phyid << 8) | mii_reg;
720 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
721 asm("sync");
722
723 timeout = 1000000;
724 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
725 }
726
727 return MIIM_CIS8204_SLEDCON_INIT;
728 }
729
730 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
731 {
732 if (priv->flags & TSEC_REDUCED)
733 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
734 else
735 return MIIM_CIS8204_EPHYCON_INIT;
736 }
737
738 uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv)
739 {
740 uint mii_data = read_phy_reg(priv, mii_reg);
741
742 if (priv->flags & TSEC_REDUCED)
743 mii_data = (mii_data & 0xfff0) | 0x000b;
744 return mii_data;
745 }
746
747 /* Initialized required registers to appropriate values, zeroing
748 * those we don't care about (unless zero is bad, in which case,
749 * choose a more appropriate value)
750 */
751 static void init_registers(volatile tsec_t * regs)
752 {
753 /* Clear IEVENT */
754 regs->ievent = IEVENT_INIT_CLEAR;
755
756 regs->imask = IMASK_INIT_CLEAR;
757
758 regs->hash.iaddr0 = 0;
759 regs->hash.iaddr1 = 0;
760 regs->hash.iaddr2 = 0;
761 regs->hash.iaddr3 = 0;
762 regs->hash.iaddr4 = 0;
763 regs->hash.iaddr5 = 0;
764 regs->hash.iaddr6 = 0;
765 regs->hash.iaddr7 = 0;
766
767 regs->hash.gaddr0 = 0;
768 regs->hash.gaddr1 = 0;
769 regs->hash.gaddr2 = 0;
770 regs->hash.gaddr3 = 0;
771 regs->hash.gaddr4 = 0;
772 regs->hash.gaddr5 = 0;
773 regs->hash.gaddr6 = 0;
774 regs->hash.gaddr7 = 0;
775
776 regs->rctrl = 0x00000000;
777
778 /* Init RMON mib registers */
779 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
780
781 regs->rmon.cam1 = 0xffffffff;
782 regs->rmon.cam2 = 0xffffffff;
783
784 regs->mrblr = MRBLR_INIT_SETTINGS;
785
786 regs->minflr = MINFLR_INIT_SETTINGS;
787
788 regs->attr = ATTR_INIT_SETTINGS;
789 regs->attreli = ATTRELI_INIT_SETTINGS;
790
791 }
792
793 /* Configure maccfg2 based on negotiated speed and duplex
794 * reported by PHY handling code
795 */
796 static void adjust_link(struct eth_device *dev)
797 {
798 struct tsec_private *priv = (struct tsec_private *)dev->priv;
799 volatile tsec_t *regs = priv->regs;
800
801 if (priv->link) {
802 if (priv->duplexity != 0)
803 regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
804 else
805 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
806
807 switch (priv->speed) {
808 case 1000:
809 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
810 | MACCFG2_GMII);
811 break;
812 case 100:
813 case 10:
814 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
815 | MACCFG2_MII);
816
817 /* Set R100 bit in all modes although
818 * it is only used in RGMII mode
819 */
820 if (priv->speed == 100)
821 regs->ecntrl |= ECNTRL_R100;
822 else
823 regs->ecntrl &= ~(ECNTRL_R100);
824 break;
825 default:
826 printf("%s: Speed was bad\n", dev->name);
827 break;
828 }
829
830 printf("Speed: %d, %s duplex\n", priv->speed,
831 (priv->duplexity) ? "full" : "half");
832
833 } else {
834 printf("%s: No link.\n", dev->name);
835 }
836 }
837
838 /* Set up the buffers and their descriptors, and bring up the
839 * interface
840 */
841 static void startup_tsec(struct eth_device *dev)
842 {
843 int i;
844 struct tsec_private *priv = (struct tsec_private *)dev->priv;
845 volatile tsec_t *regs = priv->regs;
846
847 /* Point to the buffer descriptors */
848 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
849 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
850
851 /* Initialize the Rx Buffer descriptors */
852 for (i = 0; i < PKTBUFSRX; i++) {
853 rtx.rxbd[i].status = RXBD_EMPTY;
854 rtx.rxbd[i].length = 0;
855 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
856 }
857 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
858
859 /* Initialize the TX Buffer Descriptors */
860 for (i = 0; i < TX_BUF_CNT; i++) {
861 rtx.txbd[i].status = 0;
862 rtx.txbd[i].length = 0;
863 rtx.txbd[i].bufPtr = 0;
864 }
865 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
866
867 /* Start up the PHY */
868 if(priv->phyinfo)
869 phy_run_commands(priv, priv->phyinfo->startup);
870
871 adjust_link(dev);
872
873 /* Enable Transmit and Receive */
874 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
875
876 /* Tell the DMA it is clear to go */
877 regs->dmactrl |= DMACTRL_INIT_SETTINGS;
878 regs->tstat = TSTAT_CLEAR_THALT;
879 regs->rstat = RSTAT_CLEAR_RHALT;
880 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
881 }
882
883 /* This returns the status bits of the device. The return value
884 * is never checked, and this is what the 8260 driver did, so we
885 * do the same. Presumably, this would be zero if there were no
886 * errors
887 */
888 static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
889 {
890 int i;
891 int result = 0;
892 struct tsec_private *priv = (struct tsec_private *)dev->priv;
893 volatile tsec_t *regs = priv->regs;
894
895 /* Find an empty buffer descriptor */
896 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
897 if (i >= TOUT_LOOP) {
898 debug("%s: tsec: tx buffers full\n", dev->name);
899 return result;
900 }
901 }
902
903 rtx.txbd[txIdx].bufPtr = (uint) packet;
904 rtx.txbd[txIdx].length = length;
905 rtx.txbd[txIdx].status |=
906 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
907
908 /* Tell the DMA to go */
909 regs->tstat = TSTAT_CLEAR_THALT;
910
911 /* Wait for buffer to be transmitted */
912 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
913 if (i >= TOUT_LOOP) {
914 debug("%s: tsec: tx error\n", dev->name);
915 return result;
916 }
917 }
918
919 txIdx = (txIdx + 1) % TX_BUF_CNT;
920 result = rtx.txbd[txIdx].status & TXBD_STATS;
921
922 return result;
923 }
924
925 static int tsec_recv(struct eth_device *dev)
926 {
927 int length;
928 struct tsec_private *priv = (struct tsec_private *)dev->priv;
929 volatile tsec_t *regs = priv->regs;
930
931 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
932
933 length = rtx.rxbd[rxIdx].length;
934
935 /* Send the packet up if there were no errors */
936 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
937 NetReceive(NetRxPackets[rxIdx], length - 4);
938 } else {
939 printf("Got error %x\n",
940 (rtx.rxbd[rxIdx].status & RXBD_STATS));
941 }
942
943 rtx.rxbd[rxIdx].length = 0;
944
945 /* Set the wrap bit if this is the last element in the list */
946 rtx.rxbd[rxIdx].status =
947 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
948
949 rxIdx = (rxIdx + 1) % PKTBUFSRX;
950 }
951
952 if (regs->ievent & IEVENT_BSY) {
953 regs->ievent = IEVENT_BSY;
954 regs->rstat = RSTAT_CLEAR_RHALT;
955 }
956
957 return -1;
958
959 }
960
961 /* Stop the interface */
962 static void tsec_halt(struct eth_device *dev)
963 {
964 struct tsec_private *priv = (struct tsec_private *)dev->priv;
965 volatile tsec_t *regs = priv->regs;
966
967 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
968 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
969
970 while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ;
971
972 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
973
974 /* Shut down the PHY, as needed */
975 if(priv->phyinfo)
976 phy_run_commands(priv, priv->phyinfo->shutdown);
977 }
978
979 struct phy_info phy_info_M88E1149S = {
980 0x1410ca,
981 "Marvell 88E1149S",
982 4,
983 (struct phy_cmd[]){ /* config */
984 /* Reset and configure the PHY */
985 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
986 {0x1d, 0x1f, NULL},
987 {0x1e, 0x200c, NULL},
988 {0x1d, 0x5, NULL},
989 {0x1e, 0x0, NULL},
990 {0x1e, 0x100, NULL},
991 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
992 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
993 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
994 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
995 {miim_end,}
996 },
997 (struct phy_cmd[]){ /* startup */
998 /* Status is read once to clear old link state */
999 {MIIM_STATUS, miim_read, NULL},
1000 /* Auto-negotiate */
1001 {MIIM_STATUS, miim_read, &mii_parse_sr},
1002 /* Read the status */
1003 {MIIM_88E1011_PHY_STATUS, miim_read,
1004 &mii_parse_88E1011_psr},
1005 {miim_end,}
1006 },
1007 (struct phy_cmd[]){ /* shutdown */
1008 {miim_end,}
1009 },
1010 };
1011
1012 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
1013 struct phy_info phy_info_BCM5461S = {
1014 0x02060c1, /* 5461 ID */
1015 "Broadcom BCM5461S",
1016 0, /* not clear to me what minor revisions we can shift away */
1017 (struct phy_cmd[]) { /* config */
1018 /* Reset and configure the PHY */
1019 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1020 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1021 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1022 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1023 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1024 {miim_end,}
1025 },
1026 (struct phy_cmd[]) { /* startup */
1027 /* Status is read once to clear old link state */
1028 {MIIM_STATUS, miim_read, NULL},
1029 /* Auto-negotiate */
1030 {MIIM_STATUS, miim_read, &mii_parse_sr},
1031 /* Read the status */
1032 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1033 {miim_end,}
1034 },
1035 (struct phy_cmd[]) { /* shutdown */
1036 {miim_end,}
1037 },
1038 };
1039
1040 struct phy_info phy_info_BCM5464S = {
1041 0x02060b1, /* 5464 ID */
1042 "Broadcom BCM5464S",
1043 0, /* not clear to me what minor revisions we can shift away */
1044 (struct phy_cmd[]) { /* config */
1045 /* Reset and configure the PHY */
1046 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1047 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1048 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1049 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1050 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1051 {miim_end,}
1052 },
1053 (struct phy_cmd[]) { /* startup */
1054 /* Status is read once to clear old link state */
1055 {MIIM_STATUS, miim_read, NULL},
1056 /* Auto-negotiate */
1057 {MIIM_STATUS, miim_read, &mii_parse_sr},
1058 /* Read the status */
1059 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1060 {miim_end,}
1061 },
1062 (struct phy_cmd[]) { /* shutdown */
1063 {miim_end,}
1064 },
1065 };
1066
1067 struct phy_info phy_info_M88E1011S = {
1068 0x01410c6,
1069 "Marvell 88E1011S",
1070 4,
1071 (struct phy_cmd[]){ /* config */
1072 /* Reset and configure the PHY */
1073 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1074 {0x1d, 0x1f, NULL},
1075 {0x1e, 0x200c, NULL},
1076 {0x1d, 0x5, NULL},
1077 {0x1e, 0x0, NULL},
1078 {0x1e, 0x100, NULL},
1079 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1080 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1081 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1082 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1083 {miim_end,}
1084 },
1085 (struct phy_cmd[]){ /* startup */
1086 /* Status is read once to clear old link state */
1087 {MIIM_STATUS, miim_read, NULL},
1088 /* Auto-negotiate */
1089 {MIIM_STATUS, miim_read, &mii_parse_sr},
1090 /* Read the status */
1091 {MIIM_88E1011_PHY_STATUS, miim_read,
1092 &mii_parse_88E1011_psr},
1093 {miim_end,}
1094 },
1095 (struct phy_cmd[]){ /* shutdown */
1096 {miim_end,}
1097 },
1098 };
1099
1100 struct phy_info phy_info_M88E1111S = {
1101 0x01410cc,
1102 "Marvell 88E1111S",
1103 4,
1104 (struct phy_cmd[]){ /* config */
1105 /* Reset and configure the PHY */
1106 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1107 {0x1b, 0x848f, &mii_m88e1111s_setmode},
1108 {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
1109 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1110 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1111 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1112 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1113 {miim_end,}
1114 },
1115 (struct phy_cmd[]){ /* startup */
1116 /* Status is read once to clear old link state */
1117 {MIIM_STATUS, miim_read, NULL},
1118 /* Auto-negotiate */
1119 {MIIM_STATUS, miim_read, &mii_parse_sr},
1120 /* Read the status */
1121 {MIIM_88E1011_PHY_STATUS, miim_read,
1122 &mii_parse_88E1011_psr},
1123 {miim_end,}
1124 },
1125 (struct phy_cmd[]){ /* shutdown */
1126 {miim_end,}
1127 },
1128 };
1129
1130 struct phy_info phy_info_M88E1118 = {
1131 0x01410e1,
1132 "Marvell 88E1118",
1133 4,
1134 (struct phy_cmd[]){ /* config */
1135 /* Reset and configure the PHY */
1136 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1137 {0x16, 0x0002, NULL}, /* Change Page Number */
1138 {0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */
1139 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1140 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1141 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1142 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1143 {miim_end,}
1144 },
1145 (struct phy_cmd[]){ /* startup */
1146 {0x16, 0x0000, NULL}, /* Change Page Number */
1147 /* Status is read once to clear old link state */
1148 {MIIM_STATUS, miim_read, NULL},
1149 /* Auto-negotiate */
1150 /* Read the status */
1151 {MIIM_88E1011_PHY_STATUS, miim_read,
1152 &mii_parse_88E1011_psr},
1153 {miim_end,}
1154 },
1155 (struct phy_cmd[]){ /* shutdown */
1156 {miim_end,}
1157 },
1158 };
1159
1160 /*
1161 * Since to access LED register we need do switch the page, we
1162 * do LED configuring in the miim_read-like function as follows
1163 */
1164 uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv)
1165 {
1166 uint pg;
1167
1168 /* Switch the page to access the led register */
1169 pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE);
1170 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE);
1171
1172 /* Configure leds */
1173 write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL,
1174 MIIM_88E1121_PHY_LED_DEF);
1175
1176 /* Restore the page pointer */
1177 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg);
1178 return 0;
1179 }
1180
1181 struct phy_info phy_info_M88E1121R = {
1182 0x01410cb,
1183 "Marvell 88E1121R",
1184 4,
1185 (struct phy_cmd[]){ /* config */
1186 /* Reset and configure the PHY */
1187 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1188 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1189 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1190 /* Configure leds */
1191 {MIIM_88E1121_PHY_LED_CTRL, miim_read,
1192 &mii_88E1121_set_led},
1193 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1194 {miim_end,}
1195 },
1196 (struct phy_cmd[]){ /* startup */
1197 /* Status is read once to clear old link state */
1198 {MIIM_STATUS, miim_read, NULL},
1199 {MIIM_STATUS, miim_read, &mii_parse_sr},
1200 {MIIM_STATUS, miim_read, &mii_parse_link},
1201 {miim_end,}
1202 },
1203 (struct phy_cmd[]){ /* shutdown */
1204 {miim_end,}
1205 },
1206 };
1207
1208 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
1209 {
1210 uint mii_data = read_phy_reg(priv, mii_reg);
1211
1212 /* Setting MIIM_88E1145_PHY_EXT_CR */
1213 if (priv->flags & TSEC_REDUCED)
1214 return mii_data |
1215 MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
1216 else
1217 return mii_data;
1218 }
1219
1220 static struct phy_info phy_info_M88E1145 = {
1221 0x01410cd,
1222 "Marvell 88E1145",
1223 4,
1224 (struct phy_cmd[]){ /* config */
1225 /* Reset the PHY */
1226 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1227
1228 /* Errata E0, E1 */
1229 {29, 0x001b, NULL},
1230 {30, 0x418f, NULL},
1231 {29, 0x0016, NULL},
1232 {30, 0xa2da, NULL},
1233
1234 /* Configure the PHY */
1235 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1236 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1237 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO,
1238 NULL},
1239 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
1240 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1241 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
1242 {miim_end,}
1243 },
1244 (struct phy_cmd[]){ /* startup */
1245 /* Status is read once to clear old link state */
1246 {MIIM_STATUS, miim_read, NULL},
1247 /* Auto-negotiate */
1248 {MIIM_STATUS, miim_read, &mii_parse_sr},
1249 {MIIM_88E1111_PHY_LED_CONTROL,
1250 MIIM_88E1111_PHY_LED_DIRECT, NULL},
1251 /* Read the Status */
1252 {MIIM_88E1011_PHY_STATUS, miim_read,
1253 &mii_parse_88E1011_psr},
1254 {miim_end,}
1255 },
1256 (struct phy_cmd[]){ /* shutdown */
1257 {miim_end,}
1258 },
1259 };
1260
1261 struct phy_info phy_info_cis8204 = {
1262 0x3f11,
1263 "Cicada Cis8204",
1264 6,
1265 (struct phy_cmd[]){ /* config */
1266 /* Override PHY config settings */
1267 {MIIM_CIS8201_AUX_CONSTAT,
1268 MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1269 /* Configure some basic stuff */
1270 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1271 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
1272 &mii_cis8204_fixled},
1273 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
1274 &mii_cis8204_setmode},
1275 {miim_end,}
1276 },
1277 (struct phy_cmd[]){ /* startup */
1278 /* Read the Status (2x to make sure link is right) */
1279 {MIIM_STATUS, miim_read, NULL},
1280 /* Auto-negotiate */
1281 {MIIM_STATUS, miim_read, &mii_parse_sr},
1282 /* Read the status */
1283 {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1284 &mii_parse_cis8201},
1285 {miim_end,}
1286 },
1287 (struct phy_cmd[]){ /* shutdown */
1288 {miim_end,}
1289 },
1290 };
1291
1292 /* Cicada 8201 */
1293 struct phy_info phy_info_cis8201 = {
1294 0xfc41,
1295 "CIS8201",
1296 4,
1297 (struct phy_cmd[]){ /* config */
1298 /* Override PHY config settings */
1299 {MIIM_CIS8201_AUX_CONSTAT,
1300 MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1301 /* Set up the interface mode */
1302 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT,
1303 NULL},
1304 /* Configure some basic stuff */
1305 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1306 {miim_end,}
1307 },
1308 (struct phy_cmd[]){ /* startup */
1309 /* Read the Status (2x to make sure link is right) */
1310 {MIIM_STATUS, miim_read, NULL},
1311 /* Auto-negotiate */
1312 {MIIM_STATUS, miim_read, &mii_parse_sr},
1313 /* Read the status */
1314 {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1315 &mii_parse_cis8201},
1316 {miim_end,}
1317 },
1318 (struct phy_cmd[]){ /* shutdown */
1319 {miim_end,}
1320 },
1321 };
1322 struct phy_info phy_info_VSC8244 = {
1323 0x3f1b,
1324 "Vitesse VSC8244",
1325 6,
1326 (struct phy_cmd[]){ /* config */
1327 /* Override PHY config settings */
1328 /* Configure some basic stuff */
1329 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1330 {miim_end,}
1331 },
1332 (struct phy_cmd[]){ /* startup */
1333 /* Read the Status (2x to make sure link is right) */
1334 {MIIM_STATUS, miim_read, NULL},
1335 /* Auto-negotiate */
1336 {MIIM_STATUS, miim_read, &mii_parse_sr},
1337 /* Read the status */
1338 {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1339 &mii_parse_vsc8244},
1340 {miim_end,}
1341 },
1342 (struct phy_cmd[]){ /* shutdown */
1343 {miim_end,}
1344 },
1345 };
1346
1347 struct phy_info phy_info_VSC8601 = {
1348 0x00007042,
1349 "Vitesse VSC8601",
1350 4,
1351 (struct phy_cmd[]){ /* config */
1352 /* Override PHY config settings */
1353 /* Configure some basic stuff */
1354 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1355 #ifdef CFG_VSC8601_SKEWFIX
1356 {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
1357 #if defined(CFG_VSC8601_SKEW_TX) && defined(CFG_VSC8601_SKEW_RX)
1358 {MIIM_EXT_PAGE_ACCESS,1,NULL},
1359 #define VSC8101_SKEW (CFG_VSC8601_SKEW_TX<<14)|(CFG_VSC8601_SKEW_RX<<12)
1360 {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL},
1361 {MIIM_EXT_PAGE_ACCESS,0,NULL},
1362 #endif
1363 #endif
1364 {miim_end,}
1365 },
1366 (struct phy_cmd[]){ /* startup */
1367 /* Read the Status (2x to make sure link is right) */
1368 {MIIM_STATUS, miim_read, NULL},
1369 /* Auto-negotiate */
1370 {MIIM_STATUS, miim_read, &mii_parse_sr},
1371 /* Read the status */
1372 {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1373 &mii_parse_vsc8244},
1374 {miim_end,}
1375 },
1376 (struct phy_cmd[]){ /* shutdown */
1377 {miim_end,}
1378 },
1379 };
1380
1381
1382 struct phy_info phy_info_dm9161 = {
1383 0x0181b88,
1384 "Davicom DM9161E",
1385 4,
1386 (struct phy_cmd[]){ /* config */
1387 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
1388 /* Do not bypass the scrambler/descrambler */
1389 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
1390 /* Clear 10BTCSR to default */
1391 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT,
1392 NULL},
1393 /* Configure some basic stuff */
1394 {MIIM_CONTROL, MIIM_CR_INIT, NULL},
1395 /* Restart Auto Negotiation */
1396 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
1397 {miim_end,}
1398 },
1399 (struct phy_cmd[]){ /* startup */
1400 /* Status is read once to clear old link state */
1401 {MIIM_STATUS, miim_read, NULL},
1402 /* Auto-negotiate */
1403 {MIIM_STATUS, miim_read, &mii_parse_sr},
1404 /* Read the status */
1405 {MIIM_DM9161_SCSR, miim_read,
1406 &mii_parse_dm9161_scsr},
1407 {miim_end,}
1408 },
1409 (struct phy_cmd[]){ /* shutdown */
1410 {miim_end,}
1411 },
1412 };
1413 /* a generic flavor. */
1414 struct phy_info phy_info_generic = {
1415 0,
1416 "Unknown/Generic PHY",
1417 32,
1418 (struct phy_cmd[]) { /* config */
1419 {PHY_BMCR, PHY_BMCR_RESET, NULL},
1420 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL},
1421 {miim_end,}
1422 },
1423 (struct phy_cmd[]) { /* startup */
1424 {PHY_BMSR, miim_read, NULL},
1425 {PHY_BMSR, miim_read, &mii_parse_sr},
1426 {PHY_BMSR, miim_read, &mii_parse_link},
1427 {miim_end,}
1428 },
1429 (struct phy_cmd[]) { /* shutdown */
1430 {miim_end,}
1431 }
1432 };
1433
1434
1435 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
1436 {
1437 unsigned int speed;
1438 if (priv->link) {
1439 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
1440
1441 switch (speed) {
1442 case MIIM_LXT971_SR2_10HDX:
1443 priv->speed = 10;
1444 priv->duplexity = 0;
1445 break;
1446 case MIIM_LXT971_SR2_10FDX:
1447 priv->speed = 10;
1448 priv->duplexity = 1;
1449 break;
1450 case MIIM_LXT971_SR2_100HDX:
1451 priv->speed = 100;
1452 priv->duplexity = 0;
1453 break;
1454 default:
1455 priv->speed = 100;
1456 priv->duplexity = 1;
1457 }
1458 } else {
1459 priv->speed = 0;
1460 priv->duplexity = 0;
1461 }
1462
1463 return 0;
1464 }
1465
1466 static struct phy_info phy_info_lxt971 = {
1467 0x0001378e,
1468 "LXT971",
1469 4,
1470 (struct phy_cmd[]){ /* config */
1471 {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */
1472 {miim_end,}
1473 },
1474 (struct phy_cmd[]){ /* startup - enable interrupts */
1475 /* { 0x12, 0x00f2, NULL }, */
1476 {MIIM_STATUS, miim_read, NULL},
1477 {MIIM_STATUS, miim_read, &mii_parse_sr},
1478 {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
1479 {miim_end,}
1480 },
1481 (struct phy_cmd[]){ /* shutdown - disable interrupts */
1482 {miim_end,}
1483 },
1484 };
1485
1486 /* Parse the DP83865's link and auto-neg status register for speed and duplex
1487 * information
1488 */
1489 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
1490 {
1491 switch (mii_reg & MIIM_DP83865_SPD_MASK) {
1492
1493 case MIIM_DP83865_SPD_1000:
1494 priv->speed = 1000;
1495 break;
1496
1497 case MIIM_DP83865_SPD_100:
1498 priv->speed = 100;
1499 break;
1500
1501 default:
1502 priv->speed = 10;
1503 break;
1504
1505 }
1506
1507 if (mii_reg & MIIM_DP83865_DPX_FULL)
1508 priv->duplexity = 1;
1509 else
1510 priv->duplexity = 0;
1511
1512 return 0;
1513 }
1514
1515 struct phy_info phy_info_dp83865 = {
1516 0x20005c7,
1517 "NatSemi DP83865",
1518 4,
1519 (struct phy_cmd[]){ /* config */
1520 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
1521 {miim_end,}
1522 },
1523 (struct phy_cmd[]){ /* startup */
1524 /* Status is read once to clear old link state */
1525 {MIIM_STATUS, miim_read, NULL},
1526 /* Auto-negotiate */
1527 {MIIM_STATUS, miim_read, &mii_parse_sr},
1528 /* Read the link and auto-neg status */
1529 {MIIM_DP83865_LANR, miim_read,
1530 &mii_parse_dp83865_lanr},
1531 {miim_end,}
1532 },
1533 (struct phy_cmd[]){ /* shutdown */
1534 {miim_end,}
1535 },
1536 };
1537
1538 struct phy_info phy_info_rtl8211b = {
1539 0x001cc91,
1540 "RealTek RTL8211B",
1541 4,
1542 (struct phy_cmd[]){ /* config */
1543 /* Reset and configure the PHY */
1544 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1545 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1546 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1547 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1548 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1549 {miim_end,}
1550 },
1551 (struct phy_cmd[]){ /* startup */
1552 /* Status is read once to clear old link state */
1553 {MIIM_STATUS, miim_read, NULL},
1554 /* Auto-negotiate */
1555 {MIIM_STATUS, miim_read, &mii_parse_sr},
1556 /* Read the status */
1557 {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr},
1558 {miim_end,}
1559 },
1560 (struct phy_cmd[]){ /* shutdown */
1561 {miim_end,}
1562 },
1563 };
1564
1565 struct phy_info *phy_info[] = {
1566 &phy_info_cis8204,
1567 &phy_info_cis8201,
1568 &phy_info_BCM5461S,
1569 &phy_info_BCM5464S,
1570 &phy_info_M88E1011S,
1571 &phy_info_M88E1111S,
1572 &phy_info_M88E1118,
1573 &phy_info_M88E1121R,
1574 &phy_info_M88E1145,
1575 &phy_info_M88E1149S,
1576 &phy_info_dm9161,
1577 &phy_info_lxt971,
1578 &phy_info_VSC8244,
1579 &phy_info_VSC8601,
1580 &phy_info_dp83865,
1581 &phy_info_rtl8211b,
1582 &phy_info_generic,
1583 NULL
1584 };
1585
1586 /* Grab the identifier of the device's PHY, and search through
1587 * all of the known PHYs to see if one matches. If so, return
1588 * it, if not, return NULL
1589 */
1590 struct phy_info *get_phy_info(struct eth_device *dev)
1591 {
1592 struct tsec_private *priv = (struct tsec_private *)dev->priv;
1593 uint phy_reg, phy_ID;
1594 int i;
1595 struct phy_info *theInfo = NULL;
1596
1597 /* Grab the bits from PHYIR1, and put them in the upper half */
1598 phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
1599 phy_ID = (phy_reg & 0xffff) << 16;
1600
1601 /* Grab the bits from PHYIR2, and put them in the lower half */
1602 phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
1603 phy_ID |= (phy_reg & 0xffff);
1604
1605 /* loop through all the known PHY types, and find one that */
1606 /* matches the ID we read from the PHY. */
1607 for (i = 0; phy_info[i]; i++) {
1608 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) {
1609 theInfo = phy_info[i];
1610 break;
1611 }
1612 }
1613
1614 if (theInfo == NULL) {
1615 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
1616 return NULL;
1617 } else {
1618 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
1619 }
1620
1621 return theInfo;
1622 }
1623
1624 /* Execute the given series of commands on the given device's
1625 * PHY, running functions as necessary
1626 */
1627 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
1628 {
1629 int i;
1630 uint result;
1631 volatile tsec_t *phyregs = priv->phyregs;
1632
1633 phyregs->miimcfg = MIIMCFG_RESET;
1634
1635 phyregs->miimcfg = MIIMCFG_INIT_VALUE;
1636
1637 while (phyregs->miimind & MIIMIND_BUSY) ;
1638
1639 for (i = 0; cmd->mii_reg != miim_end; i++) {
1640 if (cmd->mii_data == miim_read) {
1641 result = read_phy_reg(priv, cmd->mii_reg);
1642
1643 if (cmd->funct != NULL)
1644 (*(cmd->funct)) (result, priv);
1645
1646 } else {
1647 if (cmd->funct != NULL)
1648 result = (*(cmd->funct)) (cmd->mii_reg, priv);
1649 else
1650 result = cmd->mii_data;
1651
1652 write_phy_reg(priv, cmd->mii_reg, result);
1653
1654 }
1655 cmd++;
1656 }
1657 }
1658
1659 /* Relocate the function pointers in the phy cmd lists */
1660 static void relocate_cmds(void)
1661 {
1662 struct phy_cmd **cmdlistptr;
1663 struct phy_cmd *cmd;
1664 int i, j, k;
1665
1666 for (i = 0; phy_info[i]; i++) {
1667 /* First thing's first: relocate the pointers to the
1668 * PHY command structures (the structs were done) */
1669 phy_info[i] = (struct phy_info *)((uint) phy_info[i]
1670 + gd->reloc_off);
1671 phy_info[i]->name += gd->reloc_off;
1672 phy_info[i]->config =
1673 (struct phy_cmd *)((uint) phy_info[i]->config
1674 + gd->reloc_off);
1675 phy_info[i]->startup =
1676 (struct phy_cmd *)((uint) phy_info[i]->startup
1677 + gd->reloc_off);
1678 phy_info[i]->shutdown =
1679 (struct phy_cmd *)((uint) phy_info[i]->shutdown
1680 + gd->reloc_off);
1681
1682 cmdlistptr = &phy_info[i]->config;
1683 j = 0;
1684 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) {
1685 k = 0;
1686 for (cmd = *cmdlistptr;
1687 cmd->mii_reg != miim_end;
1688 cmd++) {
1689 /* Only relocate non-NULL pointers */
1690 if (cmd->funct)
1691 cmd->funct += gd->reloc_off;
1692
1693 k++;
1694 }
1695 j++;
1696 }
1697 }
1698
1699 relocated = 1;
1700 }
1701
1702 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
1703 && !defined(BITBANGMII)
1704
1705 /*
1706 * Read a MII PHY register.
1707 *
1708 * Returns:
1709 * 0 on success
1710 */
1711 static int tsec_miiphy_read(char *devname, unsigned char addr,
1712 unsigned char reg, unsigned short *value)
1713 {
1714 unsigned short ret;
1715 struct tsec_private *priv = privlist[0];
1716
1717 if (NULL == priv) {
1718 printf("Can't read PHY at address %d\n", addr);
1719 return -1;
1720 }
1721
1722 ret = (unsigned short)read_any_phy_reg(priv, addr, reg);
1723 *value = ret;
1724
1725 return 0;
1726 }
1727
1728 /*
1729 * Write a MII PHY register.
1730 *
1731 * Returns:
1732 * 0 on success
1733 */
1734 static int tsec_miiphy_write(char *devname, unsigned char addr,
1735 unsigned char reg, unsigned short value)
1736 {
1737 struct tsec_private *priv = privlist[0];
1738
1739 if (NULL == priv) {
1740 printf("Can't write PHY at address %d\n", addr);
1741 return -1;
1742 }
1743
1744 write_any_phy_reg(priv, addr, reg, value);
1745
1746 return 0;
1747 }
1748
1749 #endif
1750
1751 #ifdef CONFIG_MCAST_TFTP
1752
1753 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
1754
1755 /* Set the appropriate hash bit for the given addr */
1756
1757 /* The algorithm works like so:
1758 * 1) Take the Destination Address (ie the multicast address), and
1759 * do a CRC on it (little endian), and reverse the bits of the
1760 * result.
1761 * 2) Use the 8 most significant bits as a hash into a 256-entry
1762 * table. The table is controlled through 8 32-bit registers:
1763 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
1764 * gaddr7. This means that the 3 most significant bits in the
1765 * hash index which gaddr register to use, and the 5 other bits
1766 * indicate which bit (assuming an IBM numbering scheme, which
1767 * for PowerPC (tm) is usually the case) in the tregister holds
1768 * the entry. */
1769 static int
1770 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set)
1771 {
1772 struct tsec_private *priv = privlist[1];
1773 volatile tsec_t *regs = priv->regs;
1774 volatile u32 *reg_array, value;
1775 u8 result, whichbit, whichreg;
1776
1777 result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff);
1778 whichbit = result & 0x1f; /* the 5 LSB = which bit to set */
1779 whichreg = result >> 5; /* the 3 MSB = which reg to set it in */
1780 value = (1 << (31-whichbit));
1781
1782 reg_array = &(regs->hash.gaddr0);
1783
1784 if (set) {
1785 reg_array[whichreg] |= value;
1786 } else {
1787 reg_array[whichreg] &= ~value;
1788 }
1789 return 0;
1790 }
1791 #endif /* Multicast TFTP ? */
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