drivers/net/tsec.c

   1 /*
   2  * Freescale Three Speed Ethernet Controller driver
   3  *
   4  * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
   5  * (C) Copyright 2003, Motorola, Inc.
   6  * author Andy Fleming
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <config.h>
  12 #include <common.h>
  13 #include <malloc.h>
  14 #include <net.h>
  15 #include <command.h>
  16 #include <tsec.h>
  17 #include <fsl_mdio.h>
  18 #include <asm/errno.h>
  19 #include <asm/processor.h>
  20 #include <asm/io.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 /* Default initializations for TSEC controllers. */
  25
  26 static struct tsec_info_struct tsec_info[] = {
  27 #ifdef CONFIG_TSEC1
  28         STD_TSEC_INFO(1),       /* TSEC1 */
  29 #endif
  30 #ifdef CONFIG_TSEC2
  31         STD_TSEC_INFO(2),       /* TSEC2 */
  32 #endif
  33 #ifdef CONFIG_MPC85XX_FEC
  34         {
  35                 .regs = TSEC_GET_REGS(2, 0x2000),
  36                 .devname = CONFIG_MPC85XX_FEC_NAME,
  37                 .phyaddr = FEC_PHY_ADDR,
  38                 .flags = FEC_FLAGS,
  39                 .mii_devname = DEFAULT_MII_NAME
  40         },                      /* FEC */
  41 #endif
  42 #ifdef CONFIG_TSEC3
  43         STD_TSEC_INFO(3),       /* TSEC3 */
  44 #endif
  45 #ifdef CONFIG_TSEC4
  46         STD_TSEC_INFO(4),       /* TSEC4 */
  47 #endif
  48 };
  49
  50 #define TBIANA_SETTINGS ( \
  51                 TBIANA_ASYMMETRIC_PAUSE \
  52                 | TBIANA_SYMMETRIC_PAUSE \
  53                 | TBIANA_FULL_DUPLEX \
  54                 )
  55
  56 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
  57 #ifndef CONFIG_TSEC_TBICR_SETTINGS
  58 #define CONFIG_TSEC_TBICR_SETTINGS ( \
  59                 TBICR_PHY_RESET \
  60                 | TBICR_ANEG_ENABLE \
  61                 | TBICR_FULL_DUPLEX \
  62                 | TBICR_SPEED1_SET \
  63                 )
  64 #endif /* CONFIG_TSEC_TBICR_SETTINGS */
  65
  66 /* Configure the TBI for SGMII operation */
  67 static void tsec_configure_serdes(struct tsec_private *priv)
  68 {
  69         /*
  70          * Access TBI PHY registers at given TSEC register offset as opposed
  71          * to the register offset used for external PHY accesses
  72          */
  73         tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  74                         0, TBI_ANA, TBIANA_SETTINGS);
  75         tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  76                         0, TBI_TBICON, TBICON_CLK_SELECT);
  77         tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  78                         0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
  79 }
  80
  81 #ifdef CONFIG_MCAST_TFTP
  82
  83 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
  84
  85 /* Set the appropriate hash bit for the given addr */
  86
  87 /*
  88  * The algorithm works like so:
  89  * 1) Take the Destination Address (ie the multicast address), and
  90  * do a CRC on it (little endian), and reverse the bits of the
  91  * result.
  92  * 2) Use the 8 most significant bits as a hash into a 256-entry
  93  * table.  The table is controlled through 8 32-bit registers:
  94  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is entry
  95  * 255.  This means that the 3 most significant bits in the
  96  * hash index which gaddr register to use, and the 5 other bits
  97  * indicate which bit (assuming an IBM numbering scheme, which
  98  * for PowerPC (tm) is usually the case) in the register holds
  99  * the entry.
 100  */
 101 static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
 102 {
 103         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 104         struct tsec __iomem *regs = priv->regs;
 105         u32 result, value;
 106         u8 whichbit, whichreg;
 107
 108         result = ether_crc(MAC_ADDR_LEN, mcast_mac);
 109         whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
 110         whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
 111
 112         value = 1 << (31-whichbit);
 113
 114         if (set)
 115                 setbits_be32(&regs->hash.gaddr0 + whichreg, value);
 116         else
 117                 clrbits_be32(&regs->hash.gaddr0 + whichreg, value);
 118
 119         return 0;
 120 }
 121 #endif /* Multicast TFTP ? */
 122
 123 /*
 124  * Initialized required registers to appropriate values, zeroing
 125  * those we don't care about (unless zero is bad, in which case,
 126  * choose a more appropriate value)
 127  */
 128 static void init_registers(struct tsec __iomem *regs)
 129 {
 130         /* Clear IEVENT */
 131         out_be32(&regs->ievent, IEVENT_INIT_CLEAR);
 132
 133         out_be32(&regs->imask, IMASK_INIT_CLEAR);
 134
 135         out_be32(&regs->hash.iaddr0, 0);
 136         out_be32(&regs->hash.iaddr1, 0);
 137         out_be32(&regs->hash.iaddr2, 0);
 138         out_be32(&regs->hash.iaddr3, 0);
 139         out_be32(&regs->hash.iaddr4, 0);
 140         out_be32(&regs->hash.iaddr5, 0);
 141         out_be32(&regs->hash.iaddr6, 0);
 142         out_be32(&regs->hash.iaddr7, 0);
 143
 144         out_be32(&regs->hash.gaddr0, 0);
 145         out_be32(&regs->hash.gaddr1, 0);
 146         out_be32(&regs->hash.gaddr2, 0);
 147         out_be32(&regs->hash.gaddr3, 0);
 148         out_be32(&regs->hash.gaddr4, 0);
 149         out_be32(&regs->hash.gaddr5, 0);
 150         out_be32(&regs->hash.gaddr6, 0);
 151         out_be32(&regs->hash.gaddr7, 0);
 152
 153         out_be32(&regs->rctrl, 0x00000000);
 154
 155         /* Init RMON mib registers */
 156         memset((void *)&regs->rmon, 0, sizeof(regs->rmon));
 157
 158         out_be32(&regs->rmon.cam1, 0xffffffff);
 159         out_be32(&regs->rmon.cam2, 0xffffffff);
 160
 161         out_be32(&regs->mrblr, MRBLR_INIT_SETTINGS);
 162
 163         out_be32(&regs->minflr, MINFLR_INIT_SETTINGS);
 164
 165         out_be32(&regs->attr, ATTR_INIT_SETTINGS);
 166         out_be32(&regs->attreli, ATTRELI_INIT_SETTINGS);
 167
 168 }
 169
 170 /*
 171  * Configure maccfg2 based on negotiated speed and duplex
 172  * reported by PHY handling code
 173  */
 174 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
 175 {
 176         struct tsec __iomem *regs = priv->regs;
 177         u32 ecntrl, maccfg2;
 178
 179         if (!phydev->link) {
 180                 printf("%s: No link.\n", phydev->dev->name);
 181                 return;
 182         }
 183
 184         /* clear all bits relative with interface mode */
 185         ecntrl = in_be32(&regs->ecntrl);
 186         ecntrl &= ~ECNTRL_R100;
 187
 188         maccfg2 = in_be32(&regs->maccfg2);
 189         maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
 190
 191         if (phydev->duplex)
 192                 maccfg2 |= MACCFG2_FULL_DUPLEX;
 193
 194         switch (phydev->speed) {
 195         case 1000:
 196                 maccfg2 |= MACCFG2_GMII;
 197                 break;
 198         case 100:
 199         case 10:
 200                 maccfg2 |= MACCFG2_MII;
 201
 202                 /*
 203                  * Set R100 bit in all modes although
 204                  * it is only used in RGMII mode
 205                  */
 206                 if (phydev->speed == 100)
 207                         ecntrl |= ECNTRL_R100;
 208                 break;
 209         default:
 210                 printf("%s: Speed was bad\n", phydev->dev->name);
 211                 break;
 212         }
 213
 214         out_be32(&regs->ecntrl, ecntrl);
 215         out_be32(&regs->maccfg2, maccfg2);
 216
 217         printf("Speed: %d, %s duplex%s\n", phydev->speed,
 218                         (phydev->duplex) ? "full" : "half",
 219                         (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
 220 }
 221
 222 /*
 223  * This returns the status bits of the device. The return value
 224  * is never checked, and this is what the 8260 driver did, so we
 225  * do the same. Presumably, this would be zero if there were no
 226  * errors
 227  */
 228 static int tsec_send(struct eth_device *dev, void *packet, int length)
 229 {
 230         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 231         struct tsec __iomem *regs = priv->regs;
 232         uint16_t status;
 233         int result = 0;
 234         int i;
 235
 236         /* Find an empty buffer descriptor */
 237         for (i = 0;
 238              in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
 239              i++) {
 240                 if (i >= TOUT_LOOP) {
 241                         debug("%s: tsec: tx buffers full\n", dev->name);
 242                         return result;
 243                 }
 244         }
 245
 246         out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
 247         out_be16(&priv->txbd[priv->tx_idx].length, length);
 248         status = in_be16(&priv->txbd[priv->tx_idx].status);
 249         out_be16(&priv->txbd[priv->tx_idx].status, status |
 250                 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
 251
 252         /* Tell the DMA to go */
 253         out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
 254
 255         /* Wait for buffer to be transmitted */
 256         for (i = 0;
 257              in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
 258              i++) {
 259                 if (i >= TOUT_LOOP) {
 260                         debug("%s: tsec: tx error\n", dev->name);
 261                         return result;
 262                 }
 263         }
 264
 265         priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
 266         result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
 267
 268         return result;
 269 }
 270
 271 static int tsec_recv(struct eth_device *dev)
 272 {
 273         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 274         struct tsec __iomem *regs = priv->regs;
 275
 276         while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
 277                 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
 278                 uint16_t status = in_be16(&priv->rxbd[priv->rx_idx].status);
 279                 uchar *packet = net_rx_packets[priv->rx_idx];
 280
 281                 /* Send the packet up if there were no errors */
 282                 if (!(status & RXBD_STATS))
 283                         net_process_received_packet(packet, length - 4);
 284                 else
 285                         printf("Got error %x\n", (status & RXBD_STATS));
 286
 287                 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
 288
 289                 status = RXBD_EMPTY;
 290                 /* Set the wrap bit if this is the last element in the list */
 291                 if ((priv->rx_idx + 1) == PKTBUFSRX)
 292                         status |= RXBD_WRAP;
 293                 out_be16(&priv->rxbd[priv->rx_idx].status, status);
 294
 295                 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
 296         }
 297
 298         if (in_be32(&regs->ievent) & IEVENT_BSY) {
 299                 out_be32(&regs->ievent, IEVENT_BSY);
 300                 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 301         }
 302
 303         return -1;
 304 }
 305
 306 /* Stop the interface */
 307 static void tsec_halt(struct eth_device *dev)
 308 {
 309         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 310         struct tsec __iomem *regs = priv->regs;
 311
 312         clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
 313         setbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
 314
 315         while ((in_be32(&regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
 316                         != (IEVENT_GRSC | IEVENT_GTSC))
 317                 ;
 318
 319         clrbits_be32(&regs->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
 320
 321         /* Shut down the PHY, as needed */
 322         phy_shutdown(priv->phydev);
 323 }
 324
 325 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 326 /*
 327  * When MACCFG1[Rx_EN] is enabled during system boot as part
 328  * of the eTSEC port initialization sequence,
 329  * the eTSEC Rx logic may not be properly initialized.
 330  */
 331 void redundant_init(struct eth_device *dev)
 332 {
 333         struct tsec_private *priv = dev->priv;
 334         struct tsec __iomem *regs = priv->regs;
 335         uint t, count = 0;
 336         int fail = 1;
 337         static const u8 pkt[] = {
 338                 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
 339                 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
 340                 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
 341                 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
 342                 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
 343                 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
 344                 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
 345                 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
 346                 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
 347                 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
 348                 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
 349                 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
 350                 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
 351                 0x71, 0x72};
 352
 353         /* Enable promiscuous mode */
 354         setbits_be32(&regs->rctrl, 0x8);
 355         /* Enable loopback mode */
 356         setbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
 357         /* Enable transmit and receive */
 358         setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
 359
 360         /* Tell the DMA it is clear to go */
 361         setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
 362         out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
 363         out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 364         clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
 365
 366         do {
 367                 uint16_t status;
 368                 tsec_send(dev, (void *)pkt, sizeof(pkt));
 369
 370                 /* Wait for buffer to be received */
 371                 for (t = 0;
 372                      in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
 373                      t++) {
 374                         if (t >= 10 * TOUT_LOOP) {
 375                                 printf("%s: tsec: rx error\n", dev->name);
 376                                 break;
 377                         }
 378                 }
 379
 380                 if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
 381                         fail = 0;
 382
 383                 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
 384                 status = RXBD_EMPTY;
 385                 if ((priv->rx_idx + 1) == PKTBUFSRX)
 386                         status |= RXBD_WRAP;
 387                 out_be16(&priv->rxbd[priv->rx_idx].status, status);
 388                 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
 389
 390                 if (in_be32(&regs->ievent) & IEVENT_BSY) {
 391                         out_be32(&regs->ievent, IEVENT_BSY);
 392                         out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 393                 }
 394                 if (fail) {
 395                         printf("loopback recv packet error!\n");
 396                         clrbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
 397                         udelay(1000);
 398                         setbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
 399                 }
 400         } while ((count++ < 4) && (fail == 1));
 401
 402         if (fail)
 403                 panic("eTSEC init fail!\n");
 404         /* Disable promiscuous mode */
 405         clrbits_be32(&regs->rctrl, 0x8);
 406         /* Disable loopback mode */
 407         clrbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
 408 }
 409 #endif
 410
 411 /*
 412  * Set up the buffers and their descriptors, and bring up the
 413  * interface
 414  */
 415 static void startup_tsec(struct eth_device *dev)
 416 {
 417         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 418         struct tsec __iomem *regs = priv->regs;
 419         uint16_t status;
 420         int i;
 421
 422         /* reset the indices to zero */
 423         priv->rx_idx = 0;
 424         priv->tx_idx = 0;
 425 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 426         uint svr;
 427 #endif
 428
 429         /* Point to the buffer descriptors */
 430         out_be32(&regs->tbase, (u32)&priv->txbd[0]);
 431         out_be32(&regs->rbase, (u32)&priv->rxbd[0]);
 432
 433         /* Initialize the Rx Buffer descriptors */
 434         for (i = 0; i < PKTBUFSRX; i++) {
 435                 out_be16(&priv->rxbd[i].status, RXBD_EMPTY);
 436                 out_be16(&priv->rxbd[i].length, 0);
 437                 out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]);
 438         }
 439         status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status);
 440         out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
 441
 442         /* Initialize the TX Buffer Descriptors */
 443         for (i = 0; i < TX_BUF_CNT; i++) {
 444                 out_be16(&priv->txbd[i].status, 0);
 445                 out_be16(&priv->txbd[i].length, 0);
 446                 out_be32(&priv->txbd[i].bufptr, 0);
 447         }
 448         status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status);
 449         out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
 450
 451 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 452         svr = get_svr();
 453         if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
 454                 redundant_init(dev);
 455 #endif
 456         /* Enable Transmit and Receive */
 457         setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
 458
 459         /* Tell the DMA it is clear to go */
 460         setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
 461         out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
 462         out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
 463         clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
 464 }
 465
 466 /*
 467  * Initializes data structures and registers for the controller,
 468  * and brings the interface up. Returns the link status, meaning
 469  * that it returns success if the link is up, failure otherwise.
 470  * This allows U-Boot to find the first active controller.
 471  */
 472 static int tsec_init(struct eth_device *dev, bd_t * bd)
 473 {
 474         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 475         struct tsec __iomem *regs = priv->regs;
 476         u32 tempval;
 477         int ret;
 478
 479         /* Make sure the controller is stopped */
 480         tsec_halt(dev);
 481
 482         /* Init MACCFG2.  Defaults to GMII */
 483         out_be32(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
 484
 485         /* Init ECNTRL */
 486         out_be32(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
 487
 488         /*
 489          * Copy the station address into the address registers.
 490          * For a station address of 0x12345678ABCD in transmission
 491          * order (BE), MACnADDR1 is set to 0xCDAB7856 and
 492          * MACnADDR2 is set to 0x34120000.
 493          */
 494         tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
 495                   (dev->enetaddr[3] << 8)  |  dev->enetaddr[2];
 496
 497         out_be32(&regs->macstnaddr1, tempval);
 498
 499         tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
 500
 501         out_be32(&regs->macstnaddr2, tempval);
 502
 503         /* Clear out (for the most part) the other registers */
 504         init_registers(regs);
 505
 506         /* Ready the device for tx/rx */
 507         startup_tsec(dev);
 508
 509         /* Start up the PHY */
 510         ret = phy_startup(priv->phydev);
 511         if (ret) {
 512                 printf("Could not initialize PHY %s\n",
 513                        priv->phydev->dev->name);
 514                 return ret;
 515         }
 516
 517         adjust_link(priv, priv->phydev);
 518
 519         /* If there's no link, fail */
 520         return priv->phydev->link ? 0 : -1;
 521 }
 522
 523 static phy_interface_t tsec_get_interface(struct tsec_private *priv)
 524 {
 525         struct tsec __iomem *regs = priv->regs;
 526         u32 ecntrl;
 527
 528         ecntrl = in_be32(&regs->ecntrl);
 529
 530         if (ecntrl & ECNTRL_SGMII_MODE)
 531                 return PHY_INTERFACE_MODE_SGMII;
 532
 533         if (ecntrl & ECNTRL_TBI_MODE) {
 534                 if (ecntrl & ECNTRL_REDUCED_MODE)
 535                         return PHY_INTERFACE_MODE_RTBI;
 536                 else
 537                         return PHY_INTERFACE_MODE_TBI;
 538         }
 539
 540         if (ecntrl & ECNTRL_REDUCED_MODE) {
 541                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
 542                         return PHY_INTERFACE_MODE_RMII;
 543                 else {
 544                         phy_interface_t interface = priv->interface;
 545
 546                         /*
 547                          * This isn't autodetected, so it must
 548                          * be set by the platform code.
 549                          */
 550                         if ((interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 551                             (interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
 552                             (interface == PHY_INTERFACE_MODE_RGMII_RXID))
 553                                 return interface;
 554
 555                         return PHY_INTERFACE_MODE_RGMII;
 556                 }
 557         }
 558
 559         if (priv->flags & TSEC_GIGABIT)
 560                 return PHY_INTERFACE_MODE_GMII;
 561
 562         return PHY_INTERFACE_MODE_MII;
 563 }
 564
 565 /*
 566  * Discover which PHY is attached to the device, and configure it
 567  * properly.  If the PHY is not recognized, then return 0
 568  * (failure).  Otherwise, return 1
 569  */
 570 static int init_phy(struct eth_device *dev)
 571 {
 572         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 573         struct phy_device *phydev;
 574         struct tsec __iomem *regs = priv->regs;
 575         u32 supported = (SUPPORTED_10baseT_Half |
 576                         SUPPORTED_10baseT_Full |
 577                         SUPPORTED_100baseT_Half |
 578                         SUPPORTED_100baseT_Full);
 579
 580         if (priv->flags & TSEC_GIGABIT)
 581                 supported |= SUPPORTED_1000baseT_Full;
 582
 583         /* Assign a Physical address to the TBI */
 584         out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);
 585
 586         priv->interface = tsec_get_interface(priv);
 587
 588         if (priv->interface == PHY_INTERFACE_MODE_SGMII)
 589                 tsec_configure_serdes(priv);
 590
 591         phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
 592         if (!phydev)
 593                 return 0;
 594
 595         phydev->supported &= supported;
 596         phydev->advertising = phydev->supported;
 597
 598         priv->phydev = phydev;
 599
 600         phy_config(phydev);
 601
 602         return 1;
 603 }
 604
 605 /*
 606  * Initialize device structure. Returns success if PHY
 607  * initialization succeeded (i.e. if it recognizes the PHY)
 608  */
 609 static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
 610 {
 611         struct eth_device *dev;
 612         int i;
 613         struct tsec_private *priv;
 614
 615         dev = (struct eth_device *)malloc(sizeof *dev);
 616
 617         if (NULL == dev)
 618                 return 0;
 619
 620         memset(dev, 0, sizeof *dev);
 621
 622         priv = (struct tsec_private *)malloc(sizeof(*priv));
 623
 624         if (NULL == priv)
 625                 return 0;
 626
 627         priv->regs = tsec_info->regs;
 628         priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
 629
 630         priv->phyaddr = tsec_info->phyaddr;
 631         priv->flags = tsec_info->flags;
 632
 633         sprintf(dev->name, tsec_info->devname);
 634         priv->interface = tsec_info->interface;
 635         priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
 636         dev->iobase = 0;
 637         dev->priv = priv;
 638         dev->init = tsec_init;
 639         dev->halt = tsec_halt;
 640         dev->send = tsec_send;
 641         dev->recv = tsec_recv;
 642 #ifdef CONFIG_MCAST_TFTP
 643         dev->mcast = tsec_mcast_addr;
 644 #endif
 645
 646         /* Tell U-Boot to get the addr from the env */
 647         for (i = 0; i < 6; i++)
 648                 dev->enetaddr[i] = 0;
 649
 650         eth_register(dev);
 651
 652         /* Reset the MAC */
 653         setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
 654         udelay(2);  /* Soft Reset must be asserted for 3 TX clocks */
 655         clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
 656
 657         /* Try to initialize PHY here, and return */
 658         return init_phy(dev);
 659 }
 660
 661 /*
 662  * Initialize all the TSEC devices
 663  *
 664  * Returns the number of TSEC devices that were initialized
 665  */
 666 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
 667 {
 668         int i;
 669         int ret, count = 0;
 670
 671         for (i = 0; i < num; i++) {
 672                 ret = tsec_initialize(bis, &tsecs[i]);
 673                 if (ret > 0)
 674                         count += ret;
 675         }
 676
 677         return count;
 678 }
 679
 680 int tsec_standard_init(bd_t *bis)
 681 {
 682         struct fsl_pq_mdio_info info;
 683
 684         info.regs = TSEC_GET_MDIO_REGS_BASE(1);
 685         info.name = DEFAULT_MII_NAME;
 686
 687         fsl_pq_mdio_init(bis, &info);
 688
 689         return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
 690 }