2 * Copyright 2007, 2010 Freescale Semiconductor, Inc.
4 * Author: Roy Zang <tie-fei.zang@freescale.com>, Sep, 2007
7 * ULI 526x Ethernet port driver.
8 * Based on the Linux driver: drivers/net/tulip/uli526x.c
10 * This is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
24 /* some kernel function compatible define */
28 /* Board/System/Debug information/definition */
29 #define ULI_VENDOR_ID 0x10B9
30 #define ULI5261_DEVICE_ID 0x5261
31 #define ULI5263_DEVICE_ID 0x5263
33 #define PCI_ULI5261_ID (ULI5261_DEVICE_ID << 16 | ULI_VENDOR_ID)
35 #define PCI_ULI5263_ID (ULI5263_DEVICE_ID << 16 | ULI_VENDOR_ID)
37 #define ULI526X_IO_SIZE 0x100
38 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
39 #define RX_DESC_CNT PKTBUFSRX /* Allocated Rx descriptors */
40 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
41 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
42 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
43 #define TX_BUF_ALLOC 0x300
44 #define RX_ALLOC_SIZE PKTSIZE
45 #define ULI526X_RESET 1
47 #define CR6_DEFAULT 0x22200000
48 #define CR7_DEFAULT 0x180c1
49 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
50 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
51 #define MAX_PACKET_SIZE 1514
52 #define ULI5261_MAX_MULTICAST 14
53 #define RX_COPY_SIZE 100
54 #define MAX_CHECK_PACKET 0x8000
56 #define ULI526X_10MHF 0
57 #define ULI526X_100MHF 1
58 #define ULI526X_10MFD 4
59 #define ULI526X_100MFD 5
60 #define ULI526X_AUTO 8
62 #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
63 #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
64 #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
65 #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
66 #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
67 #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
69 /* CR9 definition: SROM/MII */
70 #define CR9_SROM_READ 0x4800
73 #define CR9_CRDOUT 0x8
74 #define SROM_DATA_0 0x0
75 #define SROM_DATA_1 0x4
76 #define PHY_DATA_1 0x20000
77 #define PHY_DATA_0 0x00000
78 #define MDCLKH 0x10000
80 #define PHY_POWER_DOWN 0x800
82 #define SROM_V41_CODE 0x14
84 #define SROM_CLK_WRITE(data, ioaddr) do { \
85 outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
87 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK, ioaddr); \
89 outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
93 /* Structure/enum declaration */
96 u32 tdes0
, tdes1
, tdes2
, tdes3
; /* Data for the card */
97 char *tx_buf_ptr
; /* Data for us */
98 struct tx_desc
*next_tx_desc
;
102 u32 rdes0
, rdes1
, rdes2
, rdes3
; /* Data for the card */
103 char *rx_buf_ptr
; /* Data for us */
104 struct rx_desc
*next_rx_desc
;
107 struct uli526x_board_info
{
108 u32 chip_id
; /* Chip vendor/Device ID */
111 long ioaddr
; /* I/O base address */
118 /* pointer for memory physical address */
119 dma_addr_t buf_pool_dma_ptr
; /* Tx buffer pool memory */
120 dma_addr_t buf_pool_dma_start
; /* Tx buffer pool align dword */
121 dma_addr_t desc_pool_dma_ptr
; /* descriptor pool memory */
122 dma_addr_t first_tx_desc_dma
;
123 dma_addr_t first_rx_desc_dma
;
125 /* descriptor pointer */
126 unsigned char *buf_pool_ptr
; /* Tx buffer pool memory */
127 unsigned char *buf_pool_start
; /* Tx buffer pool align dword */
128 unsigned char *desc_pool_ptr
; /* descriptor pool memory */
129 struct tx_desc
*first_tx_desc
;
130 struct tx_desc
*tx_insert_ptr
;
131 struct tx_desc
*tx_remove_ptr
;
132 struct rx_desc
*first_rx_desc
;
133 struct rx_desc
*rx_ready_ptr
; /* packet come pointer */
134 unsigned long tx_packet_cnt
; /* transmitted packet count */
136 u16 PHY_reg4
; /* Saved Phyxcer register 4 value */
138 u8 media_mode
; /* user specify media mode */
139 u8 op_mode
; /* real work dedia mode */
143 unsigned char srom
[128];
146 enum uli526x_offsets
{
147 DCR0
= 0x00, DCR1
= 0x08, DCR2
= 0x10, DCR3
= 0x18, DCR4
= 0x20,
148 DCR5
= 0x28, DCR6
= 0x30, DCR7
= 0x38, DCR8
= 0x40, DCR9
= 0x48,
149 DCR10
= 0x50, DCR11
= 0x58, DCR12
= 0x60, DCR13
= 0x68, DCR14
= 0x70,
153 enum uli526x_CR6_bits
{
154 CR6_RXSC
= 0x2, CR6_PBF
= 0x8, CR6_PM
= 0x40, CR6_PAM
= 0x80,
155 CR6_FDM
= 0x200, CR6_TXSC
= 0x2000, CR6_STI
= 0x100000,
156 CR6_SFT
= 0x200000, CR6_RXA
= 0x40000000, CR6_NO_PURGE
= 0x20000000
159 /* Global variable declaration -- */
161 static unsigned char uli526x_media_mode
= ULI526X_AUTO
;
163 static struct tx_desc desc_pool_array
[DESC_ALL_CNT
+ 0x20]
164 __attribute__ ((aligned(32)));
165 static char buf_pool
[TX_BUF_ALLOC
* TX_DESC_CNT
+ 4];
167 /* For module input parameter */
170 /* function declaration -- */
171 static int uli526x_start_xmit(struct eth_device
*dev
,
172 volatile void *packet
, int length
);
173 static const struct ethtool_ops netdev_ethtool_ops
;
174 static u16
read_srom_word(long, int);
175 static void uli526x_descriptor_init(struct uli526x_board_info
*, unsigned long);
176 static void allocate_rx_buffer(struct uli526x_board_info
*);
177 static void update_cr6(u32
, unsigned long);
178 static u16
phy_read(unsigned long, u8
, u8
, u32
);
179 static u16
phy_readby_cr10(unsigned long, u8
, u8
);
180 static void phy_write(unsigned long, u8
, u8
, u16
, u32
);
181 static void phy_writeby_cr10(unsigned long, u8
, u8
, u16
);
182 static void phy_write_1bit(unsigned long, u32
, u32
);
183 static u16
phy_read_1bit(unsigned long, u32
);
184 static int uli526x_rx_packet(struct eth_device
*);
185 static void uli526x_free_tx_pkt(struct eth_device
*,
186 struct uli526x_board_info
*);
187 static void uli526x_reuse_buf(struct rx_desc
*);
188 static void uli526x_init(struct eth_device
*);
189 static void uli526x_set_phyxcer(struct uli526x_board_info
*);
192 static int uli526x_init_one(struct eth_device
*, bd_t
*);
193 static void uli526x_disable(struct eth_device
*);
194 static void set_mac_addr(struct eth_device
*);
196 static struct pci_device_id uli526x_pci_tbl
[] = {
197 { ULI_VENDOR_ID
, ULI5261_DEVICE_ID
}, /* 5261 device */
198 { ULI_VENDOR_ID
, ULI5263_DEVICE_ID
}, /* 5263 device */
202 /* ULI526X network board routine */
205 * Search ULI526X board, register it
208 int uli526x_initialize(bd_t
*bis
)
212 struct eth_device
*dev
;
213 struct uli526x_board_info
*db
; /* board information structure */
219 /* Find PCI device */
220 devno
= pci_find_devices(uli526x_pci_tbl
, idx
++);
224 pci_read_config_dword(devno
, PCI_BASE_ADDRESS_1
, &iobase
);
227 dev
= (struct eth_device
*)malloc(sizeof *dev
);
229 printf("uli526x: Can not allocate memory\n");
232 memset(dev
, 0, sizeof(*dev
));
233 sprintf(dev
->name
, "uli526x#%d", card_number
);
234 db
= (struct uli526x_board_info
*)
235 malloc(sizeof(struct uli526x_board_info
));
239 dev
->iobase
= iobase
;
241 dev
->init
= uli526x_init_one
;
242 dev
->halt
= uli526x_disable
;
243 dev
->send
= uli526x_start_xmit
;
244 dev
->recv
= uli526x_rx_packet
;
247 db
->ioaddr
= dev
->iobase
;
250 pci_read_config_dword(devno
, PCI_VENDOR_ID
, &db
->chip_id
);
252 printf("uli526x: uli526x @0x%x\n", iobase
);
253 printf("uli526x: chip_id%x\n", db
->chip_id
);
257 pci_write_config_byte(devno
, PCI_LATENCY_TIMER
, 0x20);
263 static int uli526x_init_one(struct eth_device
*dev
, bd_t
*bis
)
266 struct uli526x_board_info
*db
= dev
->priv
;
274 uli526x_media_mode
= mode
;
277 uli526x_media_mode
= ULI526X_AUTO
;
281 /* Allocate Tx/Rx descriptor memory */
282 db
->desc_pool_ptr
= (uchar
*)&desc_pool_array
[0];
283 db
->desc_pool_dma_ptr
= (dma_addr_t
)&desc_pool_array
[0];
284 if (db
->desc_pool_ptr
== NULL
)
287 db
->buf_pool_ptr
= (uchar
*)&buf_pool
[0];
288 db
->buf_pool_dma_ptr
= (dma_addr_t
)&buf_pool
[0];
289 if (db
->buf_pool_ptr
== NULL
)
292 db
->first_tx_desc
= (struct tx_desc
*) db
->desc_pool_ptr
;
293 db
->first_tx_desc_dma
= db
->desc_pool_dma_ptr
;
295 db
->buf_pool_start
= db
->buf_pool_ptr
;
296 db
->buf_pool_dma_start
= db
->buf_pool_dma_ptr
;
299 printf("%s(): db->ioaddr= 0x%x\n",
300 __FUNCTION__
, db
->ioaddr
);
301 printf("%s(): media_mode= 0x%x\n",
302 __FUNCTION__
, uli526x_media_mode
);
303 printf("%s(): db->desc_pool_ptr= 0x%x\n",
304 __FUNCTION__
, db
->desc_pool_ptr
);
305 printf("%s(): db->desc_pool_dma_ptr= 0x%x\n",
306 __FUNCTION__
, db
->desc_pool_dma_ptr
);
307 printf("%s(): db->buf_pool_ptr= 0x%x\n",
308 __FUNCTION__
, db
->buf_pool_ptr
);
309 printf("%s(): db->buf_pool_dma_ptr= 0x%x\n",
310 __FUNCTION__
, db
->buf_pool_dma_ptr
);
313 /* read 64 word srom data */
314 for (i
= 0; i
< 64; i
++)
315 ((u16
*) db
->srom
)[i
] = cpu_to_le16(read_srom_word(db
->ioaddr
,
318 /* Set Node address */
319 if (((db
->srom
[0] == 0xff) && (db
->srom
[1] == 0xff)) ||
320 ((db
->srom
[0] == 0x00) && (db
->srom
[1] == 0x00)))
321 /* SROM absent, so write MAC address to ID Table */
323 else { /*Exist SROM*/
324 for (i
= 0; i
< 6; i
++)
325 dev
->enetaddr
[i
] = db
->srom
[20 + i
];
328 for (i
= 0; i
< 6; i
++)
329 printf("%c%02x", i
? ':' : ' ', dev
->enetaddr
[i
]);
331 db
->PHY_reg4
= 0x1e0;
333 /* system variable init */
334 db
->cr6_data
= CR6_DEFAULT
;
335 db
->cr6_data
|= ULI526X_TXTH_256
;
336 db
->cr0_data
= CR0_DEFAULT
;
341 static void uli526x_disable(struct eth_device
*dev
)
344 printf("uli526x_disable\n");
346 struct uli526x_board_info
*db
= dev
->priv
;
348 if (!((inl(db
->ioaddr
+ DCR12
)) & 0x8)) {
349 /* Reset & stop ULI526X board */
350 outl(ULI526X_RESET
, db
->ioaddr
+ DCR0
);
352 phy_write(db
->ioaddr
, db
->phy_addr
, 0, 0x8000, db
->chip_id
);
354 /* reset the board */
355 db
->cr6_data
&= ~(CR6_RXSC
| CR6_TXSC
); /* Disable Tx/Rx */
356 update_cr6(db
->cr6_data
, dev
->iobase
);
357 outl(0, dev
->iobase
+ DCR7
); /* Disable Interrupt */
358 outl(inl(dev
->iobase
+ DCR5
), dev
->iobase
+ DCR5
);
362 /* Initialize ULI526X board
363 * Reset ULI526X board
364 * Initialize TX/Rx descriptor chain structure
365 * Send the set-up frame
366 * Enable Tx/Rx machine
369 static void uli526x_init(struct eth_device
*dev
)
372 struct uli526x_board_info
*db
= dev
->priv
;
377 /* Reset M526x MAC controller */
378 outl(ULI526X_RESET
, db
->ioaddr
+ DCR0
); /* RESET MAC */
380 outl(db
->cr0_data
, db
->ioaddr
+ DCR0
);
383 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
385 db
->tx_packet_cnt
= 0;
386 for (phy_tmp
= 0; phy_tmp
< 32; phy_tmp
++) {
388 phy_value
= phy_read(db
->ioaddr
, phy_tmp
, 3, db
->chip_id
);
389 if (phy_value
!= 0xffff && phy_value
!= 0) {
390 db
->phy_addr
= phy_tmp
;
396 printf("%s(): db->ioaddr= 0x%x\n", __FUNCTION__
, db
->ioaddr
);
397 printf("%s(): db->phy_addr= 0x%x\n", __FUNCTION__
, db
->phy_addr
);
400 printf("Can not find the phy address!!!");
402 /* Parser SROM and media mode */
403 db
->media_mode
= uli526x_media_mode
;
405 if (!(inl(db
->ioaddr
+ DCR12
) & 0x8)) {
406 /* Phyxcer capability setting */
407 phy_reg_reset
= phy_read(db
->ioaddr
,
408 db
->phy_addr
, 0, db
->chip_id
);
409 phy_reg_reset
= (phy_reg_reset
| 0x8000);
410 phy_write(db
->ioaddr
, db
->phy_addr
, 0,
411 phy_reg_reset
, db
->chip_id
);
414 /* Process Phyxcer Media Mode */
415 uli526x_set_phyxcer(db
);
417 /* Media Mode Process */
418 if (!(db
->media_mode
& ULI526X_AUTO
))
419 db
->op_mode
= db
->media_mode
; /* Force Mode */
421 /* Initialize Transmit/Receive decriptor and CR3/4 */
422 uli526x_descriptor_init(db
, db
->ioaddr
);
424 /* Init CR6 to program M526X operation */
425 update_cr6(db
->cr6_data
, db
->ioaddr
);
427 /* Init CR7, interrupt active bit */
428 db
->cr7_data
= CR7_DEFAULT
;
429 outl(db
->cr7_data
, db
->ioaddr
+ DCR7
);
431 /* Init CR15, Tx jabber and Rx watchdog timer */
432 outl(db
->cr15_data
, db
->ioaddr
+ DCR15
);
434 /* Enable ULI526X Tx/Rx function */
435 db
->cr6_data
|= CR6_RXSC
| CR6_TXSC
;
436 update_cr6(db
->cr6_data
, db
->ioaddr
);
437 while (!(inl(db
->ioaddr
+ DCR12
) & 0x8))
442 * Hardware start transmission.
443 * Send a packet to media from the upper layer.
446 static int uli526x_start_xmit(struct eth_device
*dev
,
447 volatile void *packet
, int length
)
449 struct uli526x_board_info
*db
= dev
->priv
;
450 struct tx_desc
*txptr
;
451 unsigned int len
= length
;
452 /* Too large packet check */
453 if (len
> MAX_PACKET_SIZE
) {
454 printf(": big packet = %d\n", len
);
458 /* No Tx resource check, it never happen nromally */
459 if (db
->tx_packet_cnt
>= TX_FREE_DESC_CNT
) {
460 printf("No Tx resource %ld\n", db
->tx_packet_cnt
);
464 /* Disable NIC interrupt */
465 outl(0, dev
->iobase
+ DCR7
);
467 /* transmit this packet */
468 txptr
= db
->tx_insert_ptr
;
469 memcpy((char *)txptr
->tx_buf_ptr
, (char *)packet
, (int)length
);
470 txptr
->tdes1
= cpu_to_le32(0xe1000000 | length
);
472 /* Point to next transmit free descriptor */
473 db
->tx_insert_ptr
= txptr
->next_tx_desc
;
475 /* Transmit Packet Process */
476 if ((db
->tx_packet_cnt
< TX_DESC_CNT
)) {
477 txptr
->tdes0
= cpu_to_le32(0x80000000); /* Set owner bit */
478 db
->tx_packet_cnt
++; /* Ready to send */
479 outl(0x1, dev
->iobase
+ DCR1
); /* Issue Tx polling */
482 /* Got ULI526X status */
483 db
->cr5_data
= inl(db
->ioaddr
+ DCR5
);
484 outl(db
->cr5_data
, db
->ioaddr
+ DCR5
);
487 printf("%s(): length = 0x%x\n", __FUNCTION__
, length
);
488 printf("%s(): cr5_data=%x\n", __FUNCTION__
, db
->cr5_data
);
491 outl(db
->cr7_data
, dev
->iobase
+ DCR7
);
492 uli526x_free_tx_pkt(dev
, db
);
498 * Free TX resource after TX complete
501 static void uli526x_free_tx_pkt(struct eth_device
*dev
,
502 struct uli526x_board_info
*db
)
504 struct tx_desc
*txptr
;
507 txptr
= db
->tx_remove_ptr
;
508 while (db
->tx_packet_cnt
) {
509 tdes0
= le32_to_cpu(txptr
->tdes0
);
510 /* printf(DRV_NAME ": tdes0=%x\n", tdes0); */
511 if (tdes0
& 0x80000000)
514 /* A packet sent completed */
517 if (tdes0
!= 0x7fffffff) {
519 printf("%s()tdes0=%x\n", __FUNCTION__
, tdes0
);
521 if (tdes0
& TDES0_ERR_MASK
) {
522 if (tdes0
& 0x0002) { /* UnderRun */
523 if (!(db
->cr6_data
& CR6_SFT
)) {
524 db
->cr6_data
= db
->cr6_data
|
526 update_cr6(db
->cr6_data
,
533 txptr
= txptr
->next_tx_desc
;
536 /* Update TX remove pointer to next */
537 db
->tx_remove_ptr
= txptr
;
542 * Receive the come packet and pass to upper layer
545 static int uli526x_rx_packet(struct eth_device
*dev
)
547 struct uli526x_board_info
*db
= dev
->priv
;
548 struct rx_desc
*rxptr
;
552 rxptr
= db
->rx_ready_ptr
;
554 rdes0
= le32_to_cpu(rxptr
->rdes0
);
556 printf("%s(): rxptr->rdes0=%x:%x\n", __FUNCTION__
, rxptr
->rdes0
);
558 if (!(rdes0
& 0x80000000)) { /* packet owner check */
559 if ((rdes0
& 0x300) != 0x300) {
560 /* A packet without First/Last flag */
562 printf("A packet without First/Last flag");
563 uli526x_reuse_buf(rxptr
);
565 /* A packet with First/Last flag */
566 rxlen
= ((rdes0
>> 16) & 0x3fff) - 4;
568 printf("%s(): rxlen =%x\n", __FUNCTION__
, rxlen
);
570 /* error summary bit check */
571 if (rdes0
& 0x8000) {
572 /* This is a error packet */
573 printf("Error: rdes0: %x\n", rdes0
);
576 if (!(rdes0
& 0x8000) ||
577 ((db
->cr6_data
& CR6_PM
) && (rxlen
> 6))) {
580 printf("%s(): rx_skb_ptr =%x\n",
581 __FUNCTION__
, rxptr
->rx_buf_ptr
);
582 printf("%s(): rxlen =%x\n",
583 __FUNCTION__
, rxlen
);
585 printf("%s(): buf addr =%x\n",
586 __FUNCTION__
, rxptr
->rx_buf_ptr
);
587 printf("%s(): rxlen =%x\n",
588 __FUNCTION__
, rxlen
);
590 for (i
= 0; i
< 0x20; i
++)
591 printf("%s(): data[%x] =%x\n",
592 __FUNCTION__
, i
, rxptr
->rx_buf_ptr
[i
]);
595 NetReceive((uchar
*)rxptr
->rx_buf_ptr
, rxlen
);
596 uli526x_reuse_buf(rxptr
);
599 /* Reuse SKB buffer when the packet is error */
600 printf("Reuse buffer, rdes0");
601 uli526x_reuse_buf(rxptr
);
605 rxptr
= rxptr
->next_rx_desc
;
608 db
->rx_ready_ptr
= rxptr
;
613 * Reuse the RX buffer
616 static void uli526x_reuse_buf(struct rx_desc
*rxptr
)
619 if (!(rxptr
->rdes0
& cpu_to_le32(0x80000000)))
620 rxptr
->rdes0
= cpu_to_le32(0x80000000);
622 printf("Buffer reuse method error");
625 * Initialize transmit/Receive descriptor
626 * Using Chain structure, and allocate Tx/Rx buffer
629 static void uli526x_descriptor_init(struct uli526x_board_info
*db
,
630 unsigned long ioaddr
)
632 struct tx_desc
*tmp_tx
;
633 struct rx_desc
*tmp_rx
;
634 unsigned char *tmp_buf
;
635 dma_addr_t tmp_tx_dma
, tmp_rx_dma
;
636 dma_addr_t tmp_buf_dma
;
638 /* tx descriptor start pointer */
639 db
->tx_insert_ptr
= db
->first_tx_desc
;
640 db
->tx_remove_ptr
= db
->first_tx_desc
;
642 outl(db
->first_tx_desc_dma
, ioaddr
+ DCR4
); /* TX DESC address */
644 /* rx descriptor start pointer */
645 db
->first_rx_desc
= (void *)db
->first_tx_desc
+
646 sizeof(struct tx_desc
) * TX_DESC_CNT
;
647 db
->first_rx_desc_dma
= db
->first_tx_desc_dma
+
648 sizeof(struct tx_desc
) * TX_DESC_CNT
;
649 db
->rx_ready_ptr
= db
->first_rx_desc
;
650 outl(db
->first_rx_desc_dma
, ioaddr
+ DCR3
); /* RX DESC address */
652 printf("%s(): db->first_tx_desc= 0x%x\n",
653 __FUNCTION__
, db
->first_tx_desc
);
654 printf("%s(): db->first_rx_desc_dma= 0x%x\n",
655 __FUNCTION__
, db
->first_rx_desc_dma
);
657 /* Init Transmit chain */
658 tmp_buf
= db
->buf_pool_start
;
659 tmp_buf_dma
= db
->buf_pool_dma_start
;
660 tmp_tx_dma
= db
->first_tx_desc_dma
;
661 for (tmp_tx
= db
->first_tx_desc
, i
= 0;
662 i
< TX_DESC_CNT
; i
++, tmp_tx
++) {
663 tmp_tx
->tx_buf_ptr
= (char *)tmp_buf
;
664 tmp_tx
->tdes0
= cpu_to_le32(0);
665 tmp_tx
->tdes1
= cpu_to_le32(0x81000000); /* IC, chain */
666 tmp_tx
->tdes2
= cpu_to_le32(tmp_buf_dma
);
667 tmp_tx_dma
+= sizeof(struct tx_desc
);
668 tmp_tx
->tdes3
= cpu_to_le32(tmp_tx_dma
);
669 tmp_tx
->next_tx_desc
= tmp_tx
+ 1;
670 tmp_buf
= tmp_buf
+ TX_BUF_ALLOC
;
671 tmp_buf_dma
= tmp_buf_dma
+ TX_BUF_ALLOC
;
673 (--tmp_tx
)->tdes3
= cpu_to_le32(db
->first_tx_desc_dma
);
674 tmp_tx
->next_tx_desc
= db
->first_tx_desc
;
676 /* Init Receive descriptor chain */
677 tmp_rx_dma
= db
->first_rx_desc_dma
;
678 for (tmp_rx
= db
->first_rx_desc
, i
= 0; i
< RX_DESC_CNT
;
680 tmp_rx
->rdes0
= cpu_to_le32(0);
681 tmp_rx
->rdes1
= cpu_to_le32(0x01000600);
682 tmp_rx_dma
+= sizeof(struct rx_desc
);
683 tmp_rx
->rdes3
= cpu_to_le32(tmp_rx_dma
);
684 tmp_rx
->next_rx_desc
= tmp_rx
+ 1;
686 (--tmp_rx
)->rdes3
= cpu_to_le32(db
->first_rx_desc_dma
);
687 tmp_rx
->next_rx_desc
= db
->first_rx_desc
;
689 /* pre-allocate Rx buffer */
690 allocate_rx_buffer(db
);
695 * Firstly stop ULI526X, then written value and start
698 static void update_cr6(u32 cr6_data
, unsigned long ioaddr
)
701 outl(cr6_data
, ioaddr
+ DCR6
);
706 * Allocate rx buffer,
709 static void allocate_rx_buffer(struct uli526x_board_info
*db
)
712 struct rx_desc
*rxptr
;
713 rxptr
= db
->first_rx_desc
;
716 for (index
= 0; index
< RX_DESC_CNT
; index
++) {
717 addr
= (u32
)NetRxPackets
[index
];
718 addr
+= (16 - (addr
& 15));
719 rxptr
->rx_buf_ptr
= (char *) addr
;
720 rxptr
->rdes2
= cpu_to_le32(addr
);
721 rxptr
->rdes0
= cpu_to_le32(0x80000000);
723 printf("%s(): Number 0x%x:\n", __FUNCTION__
, index
);
724 printf("%s(): addr 0x%x:\n", __FUNCTION__
, addr
);
725 printf("%s(): rxptr address = 0x%x\n", __FUNCTION__
, rxptr
);
726 printf("%s(): rxptr buf address = 0x%x\n", \
727 __FUNCTION__
, rxptr
->rx_buf_ptr
);
728 printf("%s(): rdes2 = 0x%x\n", __FUNCTION__
, rxptr
->rdes2
);
730 rxptr
= rxptr
->next_rx_desc
;
735 * Read one word data from the serial ROM
738 static u16
read_srom_word(long ioaddr
, int offset
)
742 long cr9_ioaddr
= ioaddr
+ DCR9
;
744 outl(CR9_SROM_READ
, cr9_ioaddr
);
745 outl(CR9_SROM_READ
| CR9_SRCS
, cr9_ioaddr
);
747 /* Send the Read Command 110b */
748 SROM_CLK_WRITE(SROM_DATA_1
, cr9_ioaddr
);
749 SROM_CLK_WRITE(SROM_DATA_1
, cr9_ioaddr
);
750 SROM_CLK_WRITE(SROM_DATA_0
, cr9_ioaddr
);
752 /* Send the offset */
753 for (i
= 5; i
>= 0; i
--) {
754 srom_data
= (offset
& (1 << i
)) ? SROM_DATA_1
: SROM_DATA_0
;
755 SROM_CLK_WRITE(srom_data
, cr9_ioaddr
);
758 outl(CR9_SROM_READ
| CR9_SRCS
, cr9_ioaddr
);
760 for (i
= 16; i
> 0; i
--) {
761 outl(CR9_SROM_READ
| CR9_SRCS
| CR9_SRCLK
, cr9_ioaddr
);
763 srom_data
= (srom_data
<< 1) | ((inl(cr9_ioaddr
) & CR9_CRDOUT
)
765 outl(CR9_SROM_READ
| CR9_SRCS
, cr9_ioaddr
);
769 outl(CR9_SROM_READ
, cr9_ioaddr
);
774 * Set 10/100 phyxcer capability
775 * AUTO mode : phyxcer register4 is NIC capability
776 * Force mode: phyxcer register4 is the force media
779 static void uli526x_set_phyxcer(struct uli526x_board_info
*db
)
783 /* Phyxcer capability setting */
784 phy_reg
= phy_read(db
->ioaddr
, db
->phy_addr
, 4, db
->chip_id
) & ~0x01e0;
786 if (db
->media_mode
& ULI526X_AUTO
) {
788 phy_reg
|= db
->PHY_reg4
;
791 switch (db
->media_mode
) {
792 case ULI526X_10MHF
: phy_reg
|= 0x20; break;
793 case ULI526X_10MFD
: phy_reg
|= 0x40; break;
794 case ULI526X_100MHF
: phy_reg
|= 0x80; break;
795 case ULI526X_100MFD
: phy_reg
|= 0x100; break;
800 /* Write new capability to Phyxcer Reg4 */
801 if (!(phy_reg
& 0x01e0)) {
802 phy_reg
|= db
->PHY_reg4
;
803 db
->media_mode
|= ULI526X_AUTO
;
805 phy_write(db
->ioaddr
, db
->phy_addr
, 4, phy_reg
, db
->chip_id
);
807 /* Restart Auto-Negotiation */
808 phy_write(db
->ioaddr
, db
->phy_addr
, 0, 0x1200, db
->chip_id
);
813 * Write a word to Phy register
816 static void phy_write(unsigned long iobase
, u8 phy_addr
, u8 offset
,
817 u16 phy_data
, u32 chip_id
)
820 unsigned long ioaddr
;
822 if (chip_id
== PCI_ULI5263_ID
) {
823 phy_writeby_cr10(iobase
, phy_addr
, offset
, phy_data
);
826 /* M5261/M5263 Chip */
827 ioaddr
= iobase
+ DCR9
;
829 /* Send 33 synchronization clock to Phy controller */
830 for (i
= 0; i
< 35; i
++)
831 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
833 /* Send start command(01) to Phy */
834 phy_write_1bit(ioaddr
, PHY_DATA_0
, chip_id
);
835 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
837 /* Send write command(01) to Phy */
838 phy_write_1bit(ioaddr
, PHY_DATA_0
, chip_id
);
839 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
841 /* Send Phy address */
842 for (i
= 0x10; i
> 0; i
= i
>> 1)
843 phy_write_1bit(ioaddr
, phy_addr
& i
?
844 PHY_DATA_1
: PHY_DATA_0
, chip_id
);
846 /* Send register address */
847 for (i
= 0x10; i
> 0; i
= i
>> 1)
848 phy_write_1bit(ioaddr
, offset
& i
?
849 PHY_DATA_1
: PHY_DATA_0
, chip_id
);
851 /* written trasnition */
852 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
853 phy_write_1bit(ioaddr
, PHY_DATA_0
, chip_id
);
855 /* Write a word data to PHY controller */
856 for (i
= 0x8000; i
> 0; i
>>= 1)
857 phy_write_1bit(ioaddr
, phy_data
& i
?
858 PHY_DATA_1
: PHY_DATA_0
, chip_id
);
862 * Read a word data from phy register
865 static u16
phy_read(unsigned long iobase
, u8 phy_addr
, u8 offset
, u32 chip_id
)
869 unsigned long ioaddr
;
871 if (chip_id
== PCI_ULI5263_ID
)
872 return phy_readby_cr10(iobase
, phy_addr
, offset
);
873 /* M5261/M5263 Chip */
874 ioaddr
= iobase
+ DCR9
;
876 /* Send 33 synchronization clock to Phy controller */
877 for (i
= 0; i
< 35; i
++)
878 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
880 /* Send start command(01) to Phy */
881 phy_write_1bit(ioaddr
, PHY_DATA_0
, chip_id
);
882 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
884 /* Send read command(10) to Phy */
885 phy_write_1bit(ioaddr
, PHY_DATA_1
, chip_id
);
886 phy_write_1bit(ioaddr
, PHY_DATA_0
, chip_id
);
888 /* Send Phy address */
889 for (i
= 0x10; i
> 0; i
= i
>> 1)
890 phy_write_1bit(ioaddr
, phy_addr
& i
?
891 PHY_DATA_1
: PHY_DATA_0
, chip_id
);
893 /* Send register address */
894 for (i
= 0x10; i
> 0; i
= i
>> 1)
895 phy_write_1bit(ioaddr
, offset
& i
?
896 PHY_DATA_1
: PHY_DATA_0
, chip_id
);
898 /* Skip transition state */
899 phy_read_1bit(ioaddr
, chip_id
);
901 /* read 16bit data */
902 for (phy_data
= 0, i
= 0; i
< 16; i
++) {
904 phy_data
|= phy_read_1bit(ioaddr
, chip_id
);
910 static u16
phy_readby_cr10(unsigned long iobase
, u8 phy_addr
, u8 offset
)
912 unsigned long ioaddr
, cr10_value
;
914 ioaddr
= iobase
+ DCR10
;
915 cr10_value
= phy_addr
;
916 cr10_value
= (cr10_value
<<5) + offset
;
917 cr10_value
= (cr10_value
<<16) + 0x08000000;
918 outl(cr10_value
, ioaddr
);
921 cr10_value
= inl(ioaddr
);
922 if (cr10_value
& 0x10000000)
925 return (cr10_value
&0x0ffff);
928 static void phy_writeby_cr10(unsigned long iobase
, u8 phy_addr
,
929 u8 offset
, u16 phy_data
)
931 unsigned long ioaddr
, cr10_value
;
933 ioaddr
= iobase
+ DCR10
;
934 cr10_value
= phy_addr
;
935 cr10_value
= (cr10_value
<<5) + offset
;
936 cr10_value
= (cr10_value
<<16) + 0x04000000 + phy_data
;
937 outl(cr10_value
, ioaddr
);
941 * Write one bit data to Phy Controller
944 static void phy_write_1bit(unsigned long ioaddr
, u32 phy_data
, u32 chip_id
)
946 outl(phy_data
, ioaddr
); /* MII Clock Low */
948 outl(phy_data
| MDCLKH
, ioaddr
); /* MII Clock High */
950 outl(phy_data
, ioaddr
); /* MII Clock Low */
955 * Read one bit phy data from PHY controller
958 static u16
phy_read_1bit(unsigned long ioaddr
, u32 chip_id
)
962 outl(0x50000 , ioaddr
);
964 phy_data
= (inl(ioaddr
) >> 19) & 0x1;
965 outl(0x40000 , ioaddr
);
972 * Set MAC address to ID Table
975 static void set_mac_addr(struct eth_device
*dev
)
979 struct uli526x_board_info
*db
= dev
->priv
;
980 outl(0x10000, db
->ioaddr
+ DCR0
); /* Diagnosis mode */
981 /* Reset dianostic pointer port */
982 outl(0x1c0, db
->ioaddr
+ DCR13
);
983 outl(0, db
->ioaddr
+ DCR14
); /* Clear reset port */
984 outl(0x10, db
->ioaddr
+ DCR14
); /* Reset ID Table pointer */
985 outl(0, db
->ioaddr
+ DCR14
); /* Clear reset port */
986 outl(0, db
->ioaddr
+ DCR13
); /* Clear CR13 */
987 /* Select ID Table access port */
988 outl(0x1b0, db
->ioaddr
+ DCR13
);
989 /* Read MAC address from CR14 */
990 for (i
= 0; i
< 3; i
++) {
991 addr
= dev
->enetaddr
[2 * i
] | (dev
->enetaddr
[2 * i
+ 1] << 8);
992 outl(addr
, db
->ioaddr
+ DCR14
);
995 outl(0, db
->ioaddr
+ DCR13
); /* Clear CR13 */
996 outl(0, db
->ioaddr
+ DCR0
); /* Clear CR0 */