drivers/net/xilinx_axi_emac.c

   1 /*
   2  * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
   3  * Copyright (C) 2011 PetaLogix
   4  * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <config.h>
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <net.h>
  13 #include <malloc.h>
  14 #include <asm/io.h>
  15 #include <phy.h>
  16 #include <miiphy.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 /* Link setup */
  21 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
  22 #define XAE_EMMC_LINKSPD_10     0x00000000 /* Link Speed mask for 10 Mbit */
  23 #define XAE_EMMC_LINKSPD_100    0x40000000 /* Link Speed mask for 100 Mbit */
  24 #define XAE_EMMC_LINKSPD_1000   0x80000000 /* Link Speed mask for 1000 Mbit */
  25
  26 /* Interrupt Status/Enable/Mask Registers bit definitions */
  27 #define XAE_INT_RXRJECT_MASK    0x00000008 /* Rx frame rejected */
  28 #define XAE_INT_MGTRDY_MASK     0x00000080 /* MGT clock Lock */
  29
  30 /* Receive Configuration Word 1 (RCW1) Register bit definitions */
  31 #define XAE_RCW1_RX_MASK        0x10000000 /* Receiver enable */
  32
  33 /* Transmitter Configuration (TC) Register bit definitions */
  34 #define XAE_TC_TX_MASK          0x10000000 /* Transmitter enable */
  35
  36 #define XAE_UAW1_UNICASTADDR_MASK       0x0000FFFF
  37
  38 /* MDIO Management Configuration (MC) Register bit definitions */
  39 #define XAE_MDIO_MC_MDIOEN_MASK         0x00000040 /* MII management enable*/
  40
  41 /* MDIO Management Control Register (MCR) Register bit definitions */
  42 #define XAE_MDIO_MCR_PHYAD_MASK         0x1F000000 /* Phy Address Mask */
  43 #define XAE_MDIO_MCR_PHYAD_SHIFT        24         /* Phy Address Shift */
  44 #define XAE_MDIO_MCR_REGAD_MASK         0x001F0000 /* Reg Address Mask */
  45 #define XAE_MDIO_MCR_REGAD_SHIFT        16         /* Reg Address Shift */
  46 #define XAE_MDIO_MCR_OP_READ_MASK       0x00008000 /* Op Code Read Mask */
  47 #define XAE_MDIO_MCR_OP_WRITE_MASK      0x00004000 /* Op Code Write Mask */
  48 #define XAE_MDIO_MCR_INITIATE_MASK      0x00000800 /* Ready Mask */
  49 #define XAE_MDIO_MCR_READY_MASK         0x00000080 /* Ready Mask */
  50
  51 #define XAE_MDIO_DIV_DFT        29      /* Default MDIO clock divisor */
  52
  53 /* DMA macros */
  54 /* Bitmasks of XAXIDMA_CR_OFFSET register */
  55 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
  56 #define XAXIDMA_CR_RESET_MASK   0x00000004 /* Reset DMA engine */
  57
  58 /* Bitmasks of XAXIDMA_SR_OFFSET register */
  59 #define XAXIDMA_HALTED_MASK     0x00000001  /* DMA channel halted */
  60
  61 /* Bitmask for interrupts */
  62 #define XAXIDMA_IRQ_IOC_MASK    0x00001000 /* Completion intr */
  63 #define XAXIDMA_IRQ_DELAY_MASK  0x00002000 /* Delay interrupt */
  64 #define XAXIDMA_IRQ_ALL_MASK    0x00007000 /* All interrupts */
  65
  66 /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
  67 #define XAXIDMA_BD_CTRL_TXSOF_MASK      0x08000000 /* First tx packet */
  68 #define XAXIDMA_BD_CTRL_TXEOF_MASK      0x04000000 /* Last tx packet */
  69
  70 #define DMAALIGN        128
  71
  72 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
  73
  74 /* Reflect dma offsets */
  75 struct axidma_reg {
  76         u32 control; /* DMACR */
  77         u32 status; /* DMASR */
  78         u32 current; /* CURDESC */
  79         u32 reserved;
  80         u32 tail; /* TAILDESC */
  81 };
  82
  83 /* Private driver structures */
  84 struct axidma_priv {
  85         struct axidma_reg *dmatx;
  86         struct axidma_reg *dmarx;
  87         int phyaddr;
  88         struct axi_regs *iobase;
  89         phy_interface_t interface;
  90         struct phy_device *phydev;
  91         struct mii_dev *bus;
  92 };
  93
  94 /* BD descriptors */
  95 struct axidma_bd {
  96         u32 next;       /* Next descriptor pointer */
  97         u32 reserved1;
  98         u32 phys;       /* Buffer address */
  99         u32 reserved2;
 100         u32 reserved3;
 101         u32 reserved4;
 102         u32 cntrl;      /* Control */
 103         u32 status;     /* Status */
 104         u32 app0;
 105         u32 app1;       /* TX start << 16 | insert */
 106         u32 app2;       /* TX csum seed */
 107         u32 app3;
 108         u32 app4;
 109         u32 sw_id_offset;
 110         u32 reserved5;
 111         u32 reserved6;
 112 };
 113
 114 /* Static BDs - driver uses only one BD */
 115 static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
 116 static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
 117
 118 struct axi_regs {
 119         u32 reserved[3];
 120         u32 is; /* 0xC: Interrupt status */
 121         u32 reserved2;
 122         u32 ie; /* 0x14: Interrupt enable */
 123         u32 reserved3[251];
 124         u32 rcw1; /* 0x404: Rx Configuration Word 1 */
 125         u32 tc; /* 0x408: Tx Configuration */
 126         u32 reserved4;
 127         u32 emmc; /* 0x410: EMAC mode configuration */
 128         u32 reserved5[59];
 129         u32 mdio_mc; /* 0x500: MII Management Config */
 130         u32 mdio_mcr; /* 0x504: MII Management Control */
 131         u32 mdio_mwd; /* 0x508: MII Management Write Data */
 132         u32 mdio_mrd; /* 0x50C: MII Management Read Data */
 133         u32 reserved6[124];
 134         u32 uaw0; /* 0x700: Unicast address word 0 */
 135         u32 uaw1; /* 0x704: Unicast address word 1 */
 136 };
 137
 138 /* Use MII register 1 (MII status register) to detect PHY */
 139 #define PHY_DETECT_REG  1
 140
 141 /*
 142  * Mask used to verify certain PHY features (or register contents)
 143  * in the register above:
 144  *  0x1000: 10Mbps full duplex support
 145  *  0x0800: 10Mbps half duplex support
 146  *  0x0008: Auto-negotiation support
 147  */
 148 #define PHY_DETECT_MASK 0x1808
 149
 150 static inline int mdio_wait(struct axi_regs *regs)
 151 {
 152         u32 timeout = 200;
 153
 154         /* Wait till MDIO interface is ready to accept a new transaction. */
 155         while (timeout && (!(in_be32(&regs->mdio_mcr)
 156                                                 & XAE_MDIO_MCR_READY_MASK))) {
 157                 timeout--;
 158                 udelay(1);
 159         }
 160         if (!timeout) {
 161                 printf("%s: Timeout\n", __func__);
 162                 return 1;
 163         }
 164         return 0;
 165 }
 166
 167 static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
 168                    u16 *val)
 169 {
 170         struct axi_regs *regs = priv->iobase;
 171         u32 mdioctrlreg = 0;
 172
 173         if (mdio_wait(regs))
 174                 return 1;
 175
 176         mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
 177                         XAE_MDIO_MCR_PHYAD_MASK) |
 178                         ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
 179                         & XAE_MDIO_MCR_REGAD_MASK) |
 180                         XAE_MDIO_MCR_INITIATE_MASK |
 181                         XAE_MDIO_MCR_OP_READ_MASK;
 182
 183         out_be32(&regs->mdio_mcr, mdioctrlreg);
 184
 185         if (mdio_wait(regs))
 186                 return 1;
 187
 188         /* Read data */
 189         *val = in_be32(&regs->mdio_mrd);
 190         return 0;
 191 }
 192
 193 static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
 194                     u32 data)
 195 {
 196         struct axi_regs *regs = priv->iobase;
 197         u32 mdioctrlreg = 0;
 198
 199         if (mdio_wait(regs))
 200                 return 1;
 201
 202         mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
 203                         XAE_MDIO_MCR_PHYAD_MASK) |
 204                         ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
 205                         & XAE_MDIO_MCR_REGAD_MASK) |
 206                         XAE_MDIO_MCR_INITIATE_MASK |
 207                         XAE_MDIO_MCR_OP_WRITE_MASK;
 208
 209         /* Write data */
 210         out_be32(&regs->mdio_mwd, data);
 211
 212         out_be32(&regs->mdio_mcr, mdioctrlreg);
 213
 214         if (mdio_wait(regs))
 215                 return 1;
 216
 217         return 0;
 218 }
 219
 220 static int axiemac_phy_init(struct udevice *dev)
 221 {
 222         u16 phyreg;
 223         u32 i, ret;
 224         struct axidma_priv *priv = dev_get_priv(dev);
 225         struct axi_regs *regs = priv->iobase;
 226         struct phy_device *phydev;
 227
 228         u32 supported = SUPPORTED_10baseT_Half |
 229                         SUPPORTED_10baseT_Full |
 230                         SUPPORTED_100baseT_Half |
 231                         SUPPORTED_100baseT_Full |
 232                         SUPPORTED_1000baseT_Half |
 233                         SUPPORTED_1000baseT_Full;
 234
 235         /* Set default MDIO divisor */
 236         out_be32(&regs->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK);
 237
 238         if (priv->phyaddr == -1) {
 239                 /* Detect the PHY address */
 240                 for (i = 31; i >= 0; i--) {
 241                         ret = phyread(priv, i, PHY_DETECT_REG, &phyreg);
 242                         if (!ret && (phyreg != 0xFFFF) &&
 243                         ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
 244                                 /* Found a valid PHY address */
 245                                 priv->phyaddr = i;
 246                                 debug("axiemac: Found valid phy address, %x\n",
 247                                       i);
 248                                 break;
 249                         }
 250                 }
 251         }
 252
 253         /* Interface - look at tsec */
 254         phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
 255
 256         phydev->supported &= supported;
 257         phydev->advertising = phydev->supported;
 258         priv->phydev = phydev;
 259         phy_config(phydev);
 260
 261         return 0;
 262 }
 263
 264 /* Setting axi emac and phy to proper setting */
 265 static int setup_phy(struct udevice *dev)
 266 {
 267         u32 speed, emmc_reg;
 268         struct axidma_priv *priv = dev_get_priv(dev);
 269         struct axi_regs *regs = priv->iobase;
 270         struct phy_device *phydev = priv->phydev;
 271
 272         if (phy_startup(phydev)) {
 273                 printf("axiemac: could not initialize PHY %s\n",
 274                        phydev->dev->name);
 275                 return 0;
 276         }
 277         if (!phydev->link) {
 278                 printf("%s: No link.\n", phydev->dev->name);
 279                 return 0;
 280         }
 281
 282         switch (phydev->speed) {
 283         case 1000:
 284                 speed = XAE_EMMC_LINKSPD_1000;
 285                 break;
 286         case 100:
 287                 speed = XAE_EMMC_LINKSPD_100;
 288                 break;
 289         case 10:
 290                 speed = XAE_EMMC_LINKSPD_10;
 291                 break;
 292         default:
 293                 return 0;
 294         }
 295
 296         /* Setup the emac for the phy speed */
 297         emmc_reg = in_be32(&regs->emmc);
 298         emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
 299         emmc_reg |= speed;
 300
 301         /* Write new speed setting out to Axi Ethernet */
 302         out_be32(&regs->emmc, emmc_reg);
 303
 304         /*
 305         * Setting the operating speed of the MAC needs a delay. There
 306         * doesn't seem to be register to poll, so please consider this
 307         * during your application design.
 308         */
 309         udelay(1);
 310
 311         return 1;
 312 }
 313
 314 /* STOP DMA transfers */
 315 static void axiemac_stop(struct udevice *dev)
 316 {
 317         struct axidma_priv *priv = dev_get_priv(dev);
 318         u32 temp;
 319
 320         /* Stop the hardware */
 321         temp = in_be32(&priv->dmatx->control);
 322         temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
 323         out_be32(&priv->dmatx->control, temp);
 324
 325         temp = in_be32(&priv->dmarx->control);
 326         temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
 327         out_be32(&priv->dmarx->control, temp);
 328
 329         debug("axiemac: Halted\n");
 330 }
 331
 332 static int axi_ethernet_init(struct axidma_priv *priv)
 333 {
 334         struct axi_regs *regs = priv->iobase;
 335         u32 timeout = 200;
 336
 337         /*
 338          * Check the status of the MgtRdy bit in the interrupt status
 339          * registers. This must be done to allow the MGT clock to become stable
 340          * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
 341          * will be valid until this bit is valid.
 342          * The bit is always a 1 for all other PHY interfaces.
 343          */
 344         while (timeout && (!(in_be32(&regs->is) & XAE_INT_MGTRDY_MASK))) {
 345                 timeout--;
 346                 udelay(1);
 347         }
 348         if (!timeout) {
 349                 printf("%s: Timeout\n", __func__);
 350                 return 1;
 351         }
 352
 353         /* Stop the device and reset HW */
 354         /* Disable interrupts */
 355         out_be32(&regs->ie, 0);
 356
 357         /* Disable the receiver */
 358         out_be32(&regs->rcw1, in_be32(&regs->rcw1) & ~XAE_RCW1_RX_MASK);
 359
 360         /*
 361          * Stopping the receiver in mid-packet causes a dropped packet
 362          * indication from HW. Clear it.
 363          */
 364         /* Set the interrupt status register to clear the interrupt */
 365         out_be32(&regs->is, XAE_INT_RXRJECT_MASK);
 366
 367         /* Setup HW */
 368         /* Set default MDIO divisor */
 369         out_be32(&regs->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK);
 370
 371         debug("axiemac: InitHw done\n");
 372         return 0;
 373 }
 374
 375 static int axiemac_write_hwaddr(struct udevice *dev)
 376 {
 377         struct eth_pdata *pdata = dev_get_platdata(dev);
 378         struct axidma_priv *priv = dev_get_priv(dev);
 379         struct axi_regs *regs = priv->iobase;
 380
 381         /* Set the MAC address */
 382         int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
 383                 (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
 384         out_be32(&regs->uaw0, val);
 385
 386         val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
 387         val |= in_be32(&regs->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
 388         out_be32(&regs->uaw1, val);
 389         return 0;
 390 }
 391
 392 /* Reset DMA engine */
 393 static void axi_dma_init(struct axidma_priv *priv)
 394 {
 395         u32 timeout = 500;
 396
 397         /* Reset the engine so the hardware starts from a known state */
 398         out_be32(&priv->dmatx->control, XAXIDMA_CR_RESET_MASK);
 399         out_be32(&priv->dmarx->control, XAXIDMA_CR_RESET_MASK);
 400
 401         /* At the initialization time, hardware should finish reset quickly */
 402         while (timeout--) {
 403                 /* Check transmit/receive channel */
 404                 /* Reset is done when the reset bit is low */
 405                 if (!((in_be32(&priv->dmatx->control) |
 406                                 in_be32(&priv->dmarx->control))
 407                                                 & XAXIDMA_CR_RESET_MASK)) {
 408                         break;
 409                 }
 410         }
 411         if (!timeout)
 412                 printf("%s: Timeout\n", __func__);
 413 }
 414
 415 static int axiemac_start(struct udevice *dev)
 416 {
 417         struct axidma_priv *priv = dev_get_priv(dev);
 418         struct axi_regs *regs = priv->iobase;
 419         u32 temp;
 420
 421         debug("axiemac: Init started\n");
 422         /*
 423          * Initialize AXIDMA engine. AXIDMA engine must be initialized before
 424          * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
 425          * reset, and since AXIDMA reset line is connected to AxiEthernet, this
 426          * would ensure a reset of AxiEthernet.
 427          */
 428         axi_dma_init(priv);
 429
 430         /* Initialize AxiEthernet hardware. */
 431         if (axi_ethernet_init(priv))
 432                 return -1;
 433
 434         /* Disable all RX interrupts before RxBD space setup */
 435         temp = in_be32(&priv->dmarx->control);
 436         temp &= ~XAXIDMA_IRQ_ALL_MASK;
 437         out_be32(&priv->dmarx->control, temp);
 438
 439         /* Start DMA RX channel. Now it's ready to receive data.*/
 440         out_be32(&priv->dmarx->current, (u32)&rx_bd);
 441
 442         /* Setup the BD. */
 443         memset(&rx_bd, 0, sizeof(rx_bd));
 444         rx_bd.next = (u32)&rx_bd;
 445         rx_bd.phys = (u32)&rxframe;
 446         rx_bd.cntrl = sizeof(rxframe);
 447         /* Flush the last BD so DMA core could see the updates */
 448         flush_cache((u32)&rx_bd, sizeof(rx_bd));
 449
 450         /* It is necessary to flush rxframe because if you don't do it
 451          * then cache can contain uninitialized data */
 452         flush_cache((u32)&rxframe, sizeof(rxframe));
 453
 454         /* Start the hardware */
 455         temp = in_be32(&priv->dmarx->control);
 456         temp |= XAXIDMA_CR_RUNSTOP_MASK;
 457         out_be32(&priv->dmarx->control, temp);
 458
 459         /* Rx BD is ready - start */
 460         out_be32(&priv->dmarx->tail, (u32)&rx_bd);
 461
 462         /* Enable TX */
 463         out_be32(&regs->tc, XAE_TC_TX_MASK);
 464         /* Enable RX */
 465         out_be32(&regs->rcw1, XAE_RCW1_RX_MASK);
 466
 467         /* PHY setup */
 468         if (!setup_phy(dev)) {
 469                 axiemac_stop(dev);
 470                 return -1;
 471         }
 472
 473         debug("axiemac: Init complete\n");
 474         return 0;
 475 }
 476
 477 static int axiemac_send(struct udevice *dev, void *ptr, int len)
 478 {
 479         struct axidma_priv *priv = dev_get_priv(dev);
 480         u32 timeout;
 481
 482         if (len > PKTSIZE_ALIGN)
 483                 len = PKTSIZE_ALIGN;
 484
 485         /* Flush packet to main memory to be trasfered by DMA */
 486         flush_cache((u32)ptr, len);
 487
 488         /* Setup Tx BD */
 489         memset(&tx_bd, 0, sizeof(tx_bd));
 490         /* At the end of the ring, link the last BD back to the top */
 491         tx_bd.next = (u32)&tx_bd;
 492         tx_bd.phys = (u32)ptr;
 493         /* Save len */
 494         tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
 495                                                 XAXIDMA_BD_CTRL_TXEOF_MASK;
 496
 497         /* Flush the last BD so DMA core could see the updates */
 498         flush_cache((u32)&tx_bd, sizeof(tx_bd));
 499
 500         if (in_be32(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
 501                 u32 temp;
 502                 out_be32(&priv->dmatx->current, (u32)&tx_bd);
 503                 /* Start the hardware */
 504                 temp = in_be32(&priv->dmatx->control);
 505                 temp |= XAXIDMA_CR_RUNSTOP_MASK;
 506                 out_be32(&priv->dmatx->control, temp);
 507         }
 508
 509         /* Start transfer */
 510         out_be32(&priv->dmatx->tail, (u32)&tx_bd);
 511
 512         /* Wait for transmission to complete */
 513         debug("axiemac: Waiting for tx to be done\n");
 514         timeout = 200;
 515         while (timeout && (!(in_be32(&priv->dmatx->status) &
 516                         (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
 517                 timeout--;
 518                 udelay(1);
 519         }
 520         if (!timeout) {
 521                 printf("%s: Timeout\n", __func__);
 522                 return 1;
 523         }
 524
 525         debug("axiemac: Sending complete\n");
 526         return 0;
 527 }
 528
 529 static int isrxready(struct axidma_priv *priv)
 530 {
 531         u32 status;
 532
 533         /* Read pending interrupts */
 534         status = in_be32(&priv->dmarx->status);
 535
 536         /* Acknowledge pending interrupts */
 537         out_be32(&priv->dmarx->status, status & XAXIDMA_IRQ_ALL_MASK);
 538
 539         /*
 540          * If Reception done interrupt is asserted, call RX call back function
 541          * to handle the processed BDs and then raise the according flag.
 542          */
 543         if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
 544                 return 1;
 545
 546         return 0;
 547 }
 548
 549 static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
 550 {
 551         u32 length;
 552         struct axidma_priv *priv = dev_get_priv(dev);
 553         u32 temp;
 554
 555         /* Wait for an incoming packet */
 556         if (!isrxready(priv))
 557                 return -1;
 558
 559         debug("axiemac: RX data ready\n");
 560
 561         /* Disable IRQ for a moment till packet is handled */
 562         temp = in_be32(&priv->dmarx->control);
 563         temp &= ~XAXIDMA_IRQ_ALL_MASK;
 564         out_be32(&priv->dmarx->control, temp);
 565
 566         length = rx_bd.app4 & 0xFFFF; /* max length mask */
 567 #ifdef DEBUG
 568         print_buffer(&rxframe, &rxframe[0], 1, length, 16);
 569 #endif
 570
 571         *packetp = rxframe;
 572         return length;
 573 }
 574
 575 static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
 576 {
 577         struct axidma_priv *priv = dev_get_priv(dev);
 578
 579 #ifdef DEBUG
 580         /* It is useful to clear buffer to be sure that it is consistent */
 581         memset(rxframe, 0, sizeof(rxframe));
 582 #endif
 583         /* Setup RxBD */
 584         /* Clear the whole buffer and setup it again - all flags are cleared */
 585         memset(&rx_bd, 0, sizeof(rx_bd));
 586         rx_bd.next = (u32)&rx_bd;
 587         rx_bd.phys = (u32)&rxframe;
 588         rx_bd.cntrl = sizeof(rxframe);
 589
 590         /* Write bd to HW */
 591         flush_cache((u32)&rx_bd, sizeof(rx_bd));
 592
 593         /* It is necessary to flush rxframe because if you don't do it
 594          * then cache will contain previous packet */
 595         flush_cache((u32)&rxframe, sizeof(rxframe));
 596
 597         /* Rx BD is ready - start again */
 598         out_be32(&priv->dmarx->tail, (u32)&rx_bd);
 599
 600         debug("axiemac: RX completed, framelength = %d\n", length);
 601
 602         return 0;
 603 }
 604
 605 static int axiemac_miiphy_read(struct mii_dev *bus, int addr,
 606                                int devad, int reg)
 607 {
 608         int ret;
 609         u16 value;
 610
 611         ret = phyread(bus->priv, addr, reg, &value);
 612         debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg,
 613               value, ret);
 614         return value;
 615 }
 616
 617 static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,
 618                                 int reg, u16 value)
 619 {
 620         debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
 621         return phywrite(bus->priv, addr, reg, value);
 622 }
 623
 624 static int axi_emac_probe(struct udevice *dev)
 625 {
 626         struct axidma_priv *priv = dev_get_priv(dev);
 627         int ret;
 628
 629         priv->bus = mdio_alloc();
 630         priv->bus->read = axiemac_miiphy_read;
 631         priv->bus->write = axiemac_miiphy_write;
 632         priv->bus->priv = priv;
 633         strcpy(priv->bus->name, "axi_emac");
 634
 635         ret = mdio_register(priv->bus);
 636         if (ret)
 637                 return ret;
 638
 639         axiemac_phy_init(dev);
 640
 641         return 0;
 642 }
 643
 644 static int axi_emac_remove(struct udevice *dev)
 645 {
 646         struct axidma_priv *priv = dev_get_priv(dev);
 647
 648         free(priv->phydev);
 649         mdio_unregister(priv->bus);
 650         mdio_free(priv->bus);
 651
 652         return 0;
 653 }
 654
 655 static const struct eth_ops axi_emac_ops = {
 656         .start                  = axiemac_start,
 657         .send                   = axiemac_send,
 658         .recv                   = axiemac_recv,
 659         .free_pkt               = axiemac_free_pkt,
 660         .stop                   = axiemac_stop,
 661         .write_hwaddr           = axiemac_write_hwaddr,
 662 };
 663
 664 static int axi_emac_ofdata_to_platdata(struct udevice *dev)
 665 {
 666         struct eth_pdata *pdata = dev_get_platdata(dev);
 667         struct axidma_priv *priv = dev_get_priv(dev);
 668         int offset = 0;
 669         const char *phy_mode;
 670
 671         pdata->iobase = (phys_addr_t)dev_get_addr(dev);
 672         priv->iobase = (struct axi_regs *)pdata->iobase;
 673
 674         offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
 675                                        "axistream-connected");
 676         if (offset <= 0) {
 677                 printf("%s: axistream is not found\n", __func__);
 678                 return -EINVAL;
 679         }
 680         priv->dmatx = (struct axidma_reg *)fdtdec_get_int(gd->fdt_blob,
 681                                                           offset, "reg", 0);
 682         if (!priv->dmatx) {
 683                 printf("%s: axi_dma register space not found\n", __func__);
 684                 return -EINVAL;
 685         }
 686         /* RX channel offset is 0x30 */
 687         priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30);
 688
 689         priv->phyaddr = -1;
 690
 691         offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
 692                                        "phy-handle");
 693         if (offset > 0)
 694                 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
 695
 696         phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
 697         if (phy_mode)
 698                 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
 699         if (pdata->phy_interface == -1) {
 700                 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
 701                 return -EINVAL;
 702         }
 703         priv->interface = pdata->phy_interface;
 704
 705         printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
 706                priv->phyaddr, phy_string_for_interface(priv->interface));
 707
 708         return 0;
 709 }
 710
 711 static const struct udevice_id axi_emac_ids[] = {
 712         { .compatible = "xlnx,axi-ethernet-1.00.a" },
 713         { }
 714 };
 715
 716 U_BOOT_DRIVER(axi_emac) = {
 717         .name   = "axi_emac",
 718         .id     = UCLASS_ETH,
 719         .of_match = axi_emac_ids,
 720         .ofdata_to_platdata = axi_emac_ofdata_to_platdata,
 721         .probe  = axi_emac_probe,
 722         .remove = axi_emac_remove,
 723         .ops    = &axi_emac_ops,
 724         .priv_auto_alloc_size = sizeof(struct axidma_priv),
 725         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 726 };