drivers/net/xilinx_axi_emac.c

   1 /*
   2  * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
   3  * Copyright (C) 2011 PetaLogix
   4  * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <config.h>
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <net.h>
  13 #include <malloc.h>
  14 #include <asm/io.h>
  15 #include <phy.h>
  16 #include <miiphy.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 #if !defined(CONFIG_PHYLIB)
  21 # error AXI_ETHERNET requires PHYLIB
  22 #endif
  23
  24 /* Link setup */
  25 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
  26 #define XAE_EMMC_LINKSPD_10     0x00000000 /* Link Speed mask for 10 Mbit */
  27 #define XAE_EMMC_LINKSPD_100    0x40000000 /* Link Speed mask for 100 Mbit */
  28 #define XAE_EMMC_LINKSPD_1000   0x80000000 /* Link Speed mask for 1000 Mbit */
  29
  30 /* Interrupt Status/Enable/Mask Registers bit definitions */
  31 #define XAE_INT_RXRJECT_MASK    0x00000008 /* Rx frame rejected */
  32 #define XAE_INT_MGTRDY_MASK     0x00000080 /* MGT clock Lock */
  33
  34 /* Receive Configuration Word 1 (RCW1) Register bit definitions */
  35 #define XAE_RCW1_RX_MASK        0x10000000 /* Receiver enable */
  36
  37 /* Transmitter Configuration (TC) Register bit definitions */
  38 #define XAE_TC_TX_MASK          0x10000000 /* Transmitter enable */
  39
  40 #define XAE_UAW1_UNICASTADDR_MASK       0x0000FFFF
  41
  42 /* MDIO Management Configuration (MC) Register bit definitions */
  43 #define XAE_MDIO_MC_MDIOEN_MASK         0x00000040 /* MII management enable*/
  44
  45 /* MDIO Management Control Register (MCR) Register bit definitions */
  46 #define XAE_MDIO_MCR_PHYAD_MASK         0x1F000000 /* Phy Address Mask */
  47 #define XAE_MDIO_MCR_PHYAD_SHIFT        24         /* Phy Address Shift */
  48 #define XAE_MDIO_MCR_REGAD_MASK         0x001F0000 /* Reg Address Mask */
  49 #define XAE_MDIO_MCR_REGAD_SHIFT        16         /* Reg Address Shift */
  50 #define XAE_MDIO_MCR_OP_READ_MASK       0x00008000 /* Op Code Read Mask */
  51 #define XAE_MDIO_MCR_OP_WRITE_MASK      0x00004000 /* Op Code Write Mask */
  52 #define XAE_MDIO_MCR_INITIATE_MASK      0x00000800 /* Ready Mask */
  53 #define XAE_MDIO_MCR_READY_MASK         0x00000080 /* Ready Mask */
  54
  55 #define XAE_MDIO_DIV_DFT        29      /* Default MDIO clock divisor */
  56
  57 /* DMA macros */
  58 /* Bitmasks of XAXIDMA_CR_OFFSET register */
  59 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
  60 #define XAXIDMA_CR_RESET_MASK   0x00000004 /* Reset DMA engine */
  61
  62 /* Bitmasks of XAXIDMA_SR_OFFSET register */
  63 #define XAXIDMA_HALTED_MASK     0x00000001  /* DMA channel halted */
  64
  65 /* Bitmask for interrupts */
  66 #define XAXIDMA_IRQ_IOC_MASK    0x00001000 /* Completion intr */
  67 #define XAXIDMA_IRQ_DELAY_MASK  0x00002000 /* Delay interrupt */
  68 #define XAXIDMA_IRQ_ALL_MASK    0x00007000 /* All interrupts */
  69
  70 /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
  71 #define XAXIDMA_BD_CTRL_TXSOF_MASK      0x08000000 /* First tx packet */
  72 #define XAXIDMA_BD_CTRL_TXEOF_MASK      0x04000000 /* Last tx packet */
  73
  74 #define DMAALIGN        128
  75
  76 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
  77
  78 /* Reflect dma offsets */
  79 struct axidma_reg {
  80         u32 control; /* DMACR */
  81         u32 status; /* DMASR */
  82         u32 current; /* CURDESC */
  83         u32 reserved;
  84         u32 tail; /* TAILDESC */
  85 };
  86
  87 /* Private driver structures */
  88 struct axidma_priv {
  89         struct axidma_reg *dmatx;
  90         struct axidma_reg *dmarx;
  91         int phyaddr;
  92         struct axi_regs *iobase;
  93         phy_interface_t interface;
  94         struct phy_device *phydev;
  95         struct mii_dev *bus;
  96 };
  97
  98 /* BD descriptors */
  99 struct axidma_bd {
 100         u32 next;       /* Next descriptor pointer */
 101         u32 reserved1;
 102         u32 phys;       /* Buffer address */
 103         u32 reserved2;
 104         u32 reserved3;
 105         u32 reserved4;
 106         u32 cntrl;      /* Control */
 107         u32 status;     /* Status */
 108         u32 app0;
 109         u32 app1;       /* TX start << 16 | insert */
 110         u32 app2;       /* TX csum seed */
 111         u32 app3;
 112         u32 app4;
 113         u32 sw_id_offset;
 114         u32 reserved5;
 115         u32 reserved6;
 116 };
 117
 118 /* Static BDs - driver uses only one BD */
 119 static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
 120 static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
 121
 122 struct axi_regs {
 123         u32 reserved[3];
 124         u32 is; /* 0xC: Interrupt status */
 125         u32 reserved2;
 126         u32 ie; /* 0x14: Interrupt enable */
 127         u32 reserved3[251];
 128         u32 rcw1; /* 0x404: Rx Configuration Word 1 */
 129         u32 tc; /* 0x408: Tx Configuration */
 130         u32 reserved4;
 131         u32 emmc; /* 0x410: EMAC mode configuration */
 132         u32 reserved5[59];
 133         u32 mdio_mc; /* 0x500: MII Management Config */
 134         u32 mdio_mcr; /* 0x504: MII Management Control */
 135         u32 mdio_mwd; /* 0x508: MII Management Write Data */
 136         u32 mdio_mrd; /* 0x50C: MII Management Read Data */
 137         u32 reserved6[124];
 138         u32 uaw0; /* 0x700: Unicast address word 0 */
 139         u32 uaw1; /* 0x704: Unicast address word 1 */
 140 };
 141
 142 /* Use MII register 1 (MII status register) to detect PHY */
 143 #define PHY_DETECT_REG  1
 144
 145 /*
 146  * Mask used to verify certain PHY features (or register contents)
 147  * in the register above:
 148  *  0x1000: 10Mbps full duplex support
 149  *  0x0800: 10Mbps half duplex support
 150  *  0x0008: Auto-negotiation support
 151  */
 152 #define PHY_DETECT_MASK 0x1808
 153
 154 static inline int mdio_wait(struct axi_regs *regs)
 155 {
 156         u32 timeout = 200;
 157
 158         /* Wait till MDIO interface is ready to accept a new transaction. */
 159         while (timeout && (!(in_be32(&regs->mdio_mcr)
 160                                                 & XAE_MDIO_MCR_READY_MASK))) {
 161                 timeout--;
 162                 udelay(1);
 163         }
 164         if (!timeout) {
 165                 printf("%s: Timeout\n", __func__);
 166                 return 1;
 167         }
 168         return 0;
 169 }
 170
 171 static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
 172                    u16 *val)
 173 {
 174         struct axi_regs *regs = priv->iobase;
 175         u32 mdioctrlreg = 0;
 176
 177         if (mdio_wait(regs))
 178                 return 1;
 179
 180         mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
 181                         XAE_MDIO_MCR_PHYAD_MASK) |
 182                         ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
 183                         & XAE_MDIO_MCR_REGAD_MASK) |
 184                         XAE_MDIO_MCR_INITIATE_MASK |
 185                         XAE_MDIO_MCR_OP_READ_MASK;
 186
 187         out_be32(&regs->mdio_mcr, mdioctrlreg);
 188
 189         if (mdio_wait(regs))
 190                 return 1;
 191
 192         /* Read data */
 193         *val = in_be32(&regs->mdio_mrd);
 194         return 0;
 195 }
 196
 197 static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
 198                     u32 data)
 199 {
 200         struct axi_regs *regs = priv->iobase;
 201         u32 mdioctrlreg = 0;
 202
 203         if (mdio_wait(regs))
 204                 return 1;
 205
 206         mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
 207                         XAE_MDIO_MCR_PHYAD_MASK) |
 208                         ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
 209                         & XAE_MDIO_MCR_REGAD_MASK) |
 210                         XAE_MDIO_MCR_INITIATE_MASK |
 211                         XAE_MDIO_MCR_OP_WRITE_MASK;
 212
 213         /* Write data */
 214         out_be32(&regs->mdio_mwd, data);
 215
 216         out_be32(&regs->mdio_mcr, mdioctrlreg);
 217
 218         if (mdio_wait(regs))
 219                 return 1;
 220
 221         return 0;
 222 }
 223
 224 /* Setting axi emac and phy to proper setting */
 225 static int setup_phy(struct udevice *dev)
 226 {
 227         u16 phyreg;
 228         u32 i, speed, emmc_reg, ret;
 229         struct axidma_priv *priv = dev_get_priv(dev);
 230         struct axi_regs *regs = priv->iobase;
 231         struct phy_device *phydev;
 232
 233         u32 supported = SUPPORTED_10baseT_Half |
 234                         SUPPORTED_10baseT_Full |
 235                         SUPPORTED_100baseT_Half |
 236                         SUPPORTED_100baseT_Full |
 237                         SUPPORTED_1000baseT_Half |
 238                         SUPPORTED_1000baseT_Full;
 239
 240         if (priv->phyaddr == -1) {
 241                 /* Detect the PHY address */
 242                 for (i = 31; i >= 0; i--) {
 243                         ret = phyread(priv, i, PHY_DETECT_REG, &phyreg);
 244                         if (!ret && (phyreg != 0xFFFF) &&
 245                         ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
 246                                 /* Found a valid PHY address */
 247                                 priv->phyaddr = i;
 248                                 debug("axiemac: Found valid phy address, %x\n",
 249                                       i);
 250                                 break;
 251                         }
 252                 }
 253         }
 254
 255         /* Interface - look at tsec */
 256         phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
 257
 258         phydev->supported &= supported;
 259         phydev->advertising = phydev->supported;
 260         priv->phydev = phydev;
 261         phy_config(phydev);
 262         if (phy_startup(phydev)) {
 263                 printf("axiemac: could not initialize PHY %s\n",
 264                        phydev->dev->name);
 265                 return 0;
 266         }
 267         if (!phydev->link) {
 268                 printf("%s: No link.\n", phydev->dev->name);
 269                 return 0;
 270         }
 271
 272         switch (phydev->speed) {
 273         case 1000:
 274                 speed = XAE_EMMC_LINKSPD_1000;
 275                 break;
 276         case 100:
 277                 speed = XAE_EMMC_LINKSPD_100;
 278                 break;
 279         case 10:
 280                 speed = XAE_EMMC_LINKSPD_10;
 281                 break;
 282         default:
 283                 return 0;
 284         }
 285
 286         /* Setup the emac for the phy speed */
 287         emmc_reg = in_be32(&regs->emmc);
 288         emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
 289         emmc_reg |= speed;
 290
 291         /* Write new speed setting out to Axi Ethernet */
 292         out_be32(&regs->emmc, emmc_reg);
 293
 294         /*
 295         * Setting the operating speed of the MAC needs a delay. There
 296         * doesn't seem to be register to poll, so please consider this
 297         * during your application design.
 298         */
 299         udelay(1);
 300
 301         return 1;
 302 }
 303
 304 /* STOP DMA transfers */
 305 static void axiemac_halt(struct udevice *dev)
 306 {
 307         struct axidma_priv *priv = dev_get_priv(dev);
 308         u32 temp;
 309
 310         /* Stop the hardware */
 311         temp = in_be32(&priv->dmatx->control);
 312         temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
 313         out_be32(&priv->dmatx->control, temp);
 314
 315         temp = in_be32(&priv->dmarx->control);
 316         temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
 317         out_be32(&priv->dmarx->control, temp);
 318
 319         debug("axiemac: Halted\n");
 320 }
 321
 322 static int axi_ethernet_init(struct axidma_priv *priv)
 323 {
 324         struct axi_regs *regs = priv->iobase;
 325         u32 timeout = 200;
 326
 327         /*
 328          * Check the status of the MgtRdy bit in the interrupt status
 329          * registers. This must be done to allow the MGT clock to become stable
 330          * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
 331          * will be valid until this bit is valid.
 332          * The bit is always a 1 for all other PHY interfaces.
 333          */
 334         while (timeout && (!(in_be32(&regs->is) & XAE_INT_MGTRDY_MASK))) {
 335                 timeout--;
 336                 udelay(1);
 337         }
 338         if (!timeout) {
 339                 printf("%s: Timeout\n", __func__);
 340                 return 1;
 341         }
 342
 343         /* Stop the device and reset HW */
 344         /* Disable interrupts */
 345         out_be32(&regs->ie, 0);
 346
 347         /* Disable the receiver */
 348         out_be32(&regs->rcw1, in_be32(&regs->rcw1) & ~XAE_RCW1_RX_MASK);
 349
 350         /*
 351          * Stopping the receiver in mid-packet causes a dropped packet
 352          * indication from HW. Clear it.
 353          */
 354         /* Set the interrupt status register to clear the interrupt */
 355         out_be32(&regs->is, XAE_INT_RXRJECT_MASK);
 356
 357         /* Setup HW */
 358         /* Set default MDIO divisor */
 359         out_be32(&regs->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK);
 360
 361         debug("axiemac: InitHw done\n");
 362         return 0;
 363 }
 364
 365 static int axiemac_setup_mac(struct udevice *dev)
 366 {
 367         struct eth_pdata *pdata = dev_get_platdata(dev);
 368         struct axidma_priv *priv = dev_get_priv(dev);
 369         struct axi_regs *regs = priv->iobase;
 370
 371         /* Set the MAC address */
 372         int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
 373                 (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
 374         out_be32(&regs->uaw0, val);
 375
 376         val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
 377         val |= in_be32(&regs->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
 378         out_be32(&regs->uaw1, val);
 379         return 0;
 380 }
 381
 382 /* Reset DMA engine */
 383 static void axi_dma_init(struct axidma_priv *priv)
 384 {
 385         u32 timeout = 500;
 386
 387         /* Reset the engine so the hardware starts from a known state */
 388         out_be32(&priv->dmatx->control, XAXIDMA_CR_RESET_MASK);
 389         out_be32(&priv->dmarx->control, XAXIDMA_CR_RESET_MASK);
 390
 391         /* At the initialization time, hardware should finish reset quickly */
 392         while (timeout--) {
 393                 /* Check transmit/receive channel */
 394                 /* Reset is done when the reset bit is low */
 395                 if (!((in_be32(&priv->dmatx->control) |
 396                                 in_be32(&priv->dmarx->control))
 397                                                 & XAXIDMA_CR_RESET_MASK)) {
 398                         break;
 399                 }
 400         }
 401         if (!timeout)
 402                 printf("%s: Timeout\n", __func__);
 403 }
 404
 405 static int axiemac_init(struct udevice *dev)
 406 {
 407         struct axidma_priv *priv = dev_get_priv(dev);
 408         struct axi_regs *regs = priv->iobase;
 409         u32 temp;
 410
 411         debug("axiemac: Init started\n");
 412         /*
 413          * Initialize AXIDMA engine. AXIDMA engine must be initialized before
 414          * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
 415          * reset, and since AXIDMA reset line is connected to AxiEthernet, this
 416          * would ensure a reset of AxiEthernet.
 417          */
 418         axi_dma_init(priv);
 419
 420         /* Initialize AxiEthernet hardware. */
 421         if (axi_ethernet_init(priv))
 422                 return -1;
 423
 424         /* Disable all RX interrupts before RxBD space setup */
 425         temp = in_be32(&priv->dmarx->control);
 426         temp &= ~XAXIDMA_IRQ_ALL_MASK;
 427         out_be32(&priv->dmarx->control, temp);
 428
 429         /* Start DMA RX channel. Now it's ready to receive data.*/
 430         out_be32(&priv->dmarx->current, (u32)&rx_bd);
 431
 432         /* Setup the BD. */
 433         memset(&rx_bd, 0, sizeof(rx_bd));
 434         rx_bd.next = (u32)&rx_bd;
 435         rx_bd.phys = (u32)&rxframe;
 436         rx_bd.cntrl = sizeof(rxframe);
 437         /* Flush the last BD so DMA core could see the updates */
 438         flush_cache((u32)&rx_bd, sizeof(rx_bd));
 439
 440         /* It is necessary to flush rxframe because if you don't do it
 441          * then cache can contain uninitialized data */
 442         flush_cache((u32)&rxframe, sizeof(rxframe));
 443
 444         /* Start the hardware */
 445         temp = in_be32(&priv->dmarx->control);
 446         temp |= XAXIDMA_CR_RUNSTOP_MASK;
 447         out_be32(&priv->dmarx->control, temp);
 448
 449         /* Rx BD is ready - start */
 450         out_be32(&priv->dmarx->tail, (u32)&rx_bd);
 451
 452         /* Enable TX */
 453         out_be32(&regs->tc, XAE_TC_TX_MASK);
 454         /* Enable RX */
 455         out_be32(&regs->rcw1, XAE_RCW1_RX_MASK);
 456
 457         /* PHY setup */
 458         if (!setup_phy(dev)) {
 459                 axiemac_halt(dev);
 460                 return -1;
 461         }
 462
 463         debug("axiemac: Init complete\n");
 464         return 0;
 465 }
 466
 467 static int axiemac_send(struct udevice *dev, void *ptr, int len)
 468 {
 469         struct axidma_priv *priv = dev_get_priv(dev);
 470         u32 timeout;
 471
 472         if (len > PKTSIZE_ALIGN)
 473                 len = PKTSIZE_ALIGN;
 474
 475         /* Flush packet to main memory to be trasfered by DMA */
 476         flush_cache((u32)ptr, len);
 477
 478         /* Setup Tx BD */
 479         memset(&tx_bd, 0, sizeof(tx_bd));
 480         /* At the end of the ring, link the last BD back to the top */
 481         tx_bd.next = (u32)&tx_bd;
 482         tx_bd.phys = (u32)ptr;
 483         /* Save len */
 484         tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
 485                                                 XAXIDMA_BD_CTRL_TXEOF_MASK;
 486
 487         /* Flush the last BD so DMA core could see the updates */
 488         flush_cache((u32)&tx_bd, sizeof(tx_bd));
 489
 490         if (in_be32(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
 491                 u32 temp;
 492                 out_be32(&priv->dmatx->current, (u32)&tx_bd);
 493                 /* Start the hardware */
 494                 temp = in_be32(&priv->dmatx->control);
 495                 temp |= XAXIDMA_CR_RUNSTOP_MASK;
 496                 out_be32(&priv->dmatx->control, temp);
 497         }
 498
 499         /* Start transfer */
 500         out_be32(&priv->dmatx->tail, (u32)&tx_bd);
 501
 502         /* Wait for transmission to complete */
 503         debug("axiemac: Waiting for tx to be done\n");
 504         timeout = 200;
 505         while (timeout && (!(in_be32(&priv->dmatx->status) &
 506                         (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
 507                 timeout--;
 508                 udelay(1);
 509         }
 510         if (!timeout) {
 511                 printf("%s: Timeout\n", __func__);
 512                 return 1;
 513         }
 514
 515         debug("axiemac: Sending complete\n");
 516         return 0;
 517 }
 518
 519 static int isrxready(struct axidma_priv *priv)
 520 {
 521         u32 status;
 522
 523         /* Read pending interrupts */
 524         status = in_be32(&priv->dmarx->status);
 525
 526         /* Acknowledge pending interrupts */
 527         out_be32(&priv->dmarx->status, status & XAXIDMA_IRQ_ALL_MASK);
 528
 529         /*
 530          * If Reception done interrupt is asserted, call RX call back function
 531          * to handle the processed BDs and then raise the according flag.
 532          */
 533         if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
 534                 return 1;
 535
 536         return 0;
 537 }
 538
 539 static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
 540 {
 541         u32 length;
 542         struct axidma_priv *priv = dev_get_priv(dev);
 543         u32 temp;
 544
 545         /* Wait for an incoming packet */
 546         if (!isrxready(priv))
 547                 return -1;
 548
 549         debug("axiemac: RX data ready\n");
 550
 551         /* Disable IRQ for a moment till packet is handled */
 552         temp = in_be32(&priv->dmarx->control);
 553         temp &= ~XAXIDMA_IRQ_ALL_MASK;
 554         out_be32(&priv->dmarx->control, temp);
 555
 556         length = rx_bd.app4 & 0xFFFF; /* max length mask */
 557 #ifdef DEBUG
 558         print_buffer(&rxframe, &rxframe[0], 1, length, 16);
 559 #endif
 560         /* Pass the received frame up for processing */
 561         if (length)
 562                 net_process_received_packet(rxframe, length);
 563
 564 #ifdef DEBUG
 565         /* It is useful to clear buffer to be sure that it is consistent */
 566         memset(rxframe, 0, sizeof(rxframe));
 567 #endif
 568         /* Setup RxBD */
 569         /* Clear the whole buffer and setup it again - all flags are cleared */
 570         memset(&rx_bd, 0, sizeof(rx_bd));
 571         rx_bd.next = (u32)&rx_bd;
 572         rx_bd.phys = (u32)&rxframe;
 573         rx_bd.cntrl = sizeof(rxframe);
 574
 575         /* Write bd to HW */
 576         flush_cache((u32)&rx_bd, sizeof(rx_bd));
 577
 578         /* It is necessary to flush rxframe because if you don't do it
 579          * then cache will contain previous packet */
 580         flush_cache((u32)&rxframe, sizeof(rxframe));
 581
 582         /* Rx BD is ready - start again */
 583         out_be32(&priv->dmarx->tail, (u32)&rx_bd);
 584
 585         debug("axiemac: RX completed, framelength = %d\n", length);
 586
 587         return 0;
 588 }
 589
 590 static int axiemac_miiphy_read(struct mii_dev *bus, int addr,
 591                                int devad, int reg)
 592 {
 593         int ret;
 594         u16 value;
 595
 596         ret = phyread(bus->priv, addr, reg, &value);
 597         debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg,
 598               value, ret);
 599         return value;
 600 }
 601
 602 static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,
 603                                 int reg, u16 value)
 604 {
 605         debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
 606         return phywrite(bus->priv, addr, reg, value);
 607 }
 608
 609 static int axi_emac_probe(struct udevice *dev)
 610 {
 611         struct axidma_priv *priv = dev_get_priv(dev);
 612         int ret;
 613
 614         priv->bus = mdio_alloc();
 615         priv->bus->read = axiemac_miiphy_read;
 616         priv->bus->write = axiemac_miiphy_write;
 617         priv->bus->priv = priv;
 618         strcpy(priv->bus->name, "axi_emac");
 619
 620         ret = mdio_register(priv->bus);
 621         if (ret)
 622                 return ret;
 623
 624         return 0;
 625 }
 626
 627 static int axi_emac_remove(struct udevice *dev)
 628 {
 629         struct axidma_priv *priv = dev_get_priv(dev);
 630
 631         free(priv->phydev);
 632         mdio_unregister(priv->bus);
 633         mdio_free(priv->bus);
 634
 635         return 0;
 636 }
 637
 638 static const struct eth_ops axi_emac_ops = {
 639         .start                  = axiemac_init,
 640         .send                   = axiemac_send,
 641         .recv                   = axiemac_recv,
 642         .stop                   = axiemac_halt,
 643         .write_hwaddr           = axiemac_setup_mac,
 644 };
 645
 646 static int axi_emac_ofdata_to_platdata(struct udevice *dev)
 647 {
 648         struct eth_pdata *pdata = dev_get_platdata(dev);
 649         struct axidma_priv *priv = dev_get_priv(dev);
 650         int offset = 0;
 651         const char *phy_mode;
 652
 653         pdata->iobase = (phys_addr_t)dev_get_addr(dev);
 654         priv->iobase = (struct axi_regs *)pdata->iobase;
 655
 656         offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
 657                                        "axistream-connected");
 658         if (offset <= 0) {
 659                 printf("%s: axistream is not found\n", __func__);
 660                 return -EINVAL;
 661         }
 662         priv->dmatx = (struct axidma_reg *)fdtdec_get_int(gd->fdt_blob,
 663                                                           offset, "reg", 0);
 664         if (!priv->dmatx) {
 665                 printf("%s: axi_dma register space not found\n", __func__);
 666                 return -EINVAL;
 667         }
 668         /* RX channel offset is 0x30 */
 669         priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30);
 670
 671         priv->phyaddr = -1;
 672
 673         offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
 674                                        "phy-handle");
 675         if (offset > 0)
 676                 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
 677
 678         phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
 679         if (phy_mode)
 680                 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
 681         if (pdata->phy_interface == -1) {
 682                 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
 683                 return -EINVAL;
 684         }
 685         priv->interface = pdata->phy_interface;
 686
 687         printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
 688                priv->phyaddr, phy_string_for_interface(priv->interface));
 689
 690         return 0;
 691 }
 692
 693 static const struct udevice_id axi_emac_ids[] = {
 694         { .compatible = "xlnx,axi-ethernet-1.00.a" },
 695         { }
 696 };
 697
 698 U_BOOT_DRIVER(axi_emac) = {
 699         .name   = "axi_emac",
 700         .id     = UCLASS_ETH,
 701         .of_match = axi_emac_ids,
 702         .ofdata_to_platdata = axi_emac_ofdata_to_platdata,
 703         .probe  = axi_emac_probe,
 704         .remove = axi_emac_remove,
 705         .ops    = &axi_emac_ops,
 706         .priv_auto_alloc_size = sizeof(struct axidma_priv),
 707         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 708 };