drivers/net/xilinx_emaclite.c

   1 /*
   2  * (C) Copyright 2007-2009 Michal Simek
   3  * (C) Copyright 2003 Xilinx Inc.
   4  *
   5  * Michal SIMEK <monstr@monstr.eu>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <net.h>
  12 #include <config.h>
  13 #include <dm.h>
  14 #include <console.h>
  15 #include <malloc.h>
  16 #include <asm/io.h>
  17 #include <phy.h>
  18 #include <miiphy.h>
  19 #include <fdtdec.h>
  20 #include <asm-generic/errno.h>
  21 #include <linux/kernel.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #define ENET_ADDR_LENGTH        6
  26 #define ETH_FCS_LEN             4 /* Octets in the FCS */
  27
  28 /* Xmit complete */
  29 #define XEL_TSR_XMIT_BUSY_MASK          0x00000001UL
  30 /* Xmit interrupt enable bit */
  31 #define XEL_TSR_XMIT_IE_MASK            0x00000008UL
  32 /* Program the MAC address */
  33 #define XEL_TSR_PROGRAM_MASK            0x00000002UL
  34 /* define for programming the MAC address into the EMAC Lite */
  35 #define XEL_TSR_PROG_MAC_ADDR   (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
  36
  37 /* Transmit packet length upper byte */
  38 #define XEL_TPLR_LENGTH_MASK_HI         0x0000FF00UL
  39 /* Transmit packet length lower byte */
  40 #define XEL_TPLR_LENGTH_MASK_LO         0x000000FFUL
  41
  42 /* Recv complete */
  43 #define XEL_RSR_RECV_DONE_MASK          0x00000001UL
  44 /* Recv interrupt enable bit */
  45 #define XEL_RSR_RECV_IE_MASK            0x00000008UL
  46
  47 /* MDIO Address Register Bit Masks */
  48 #define XEL_MDIOADDR_REGADR_MASK  0x0000001F    /* Register Address */
  49 #define XEL_MDIOADDR_PHYADR_MASK  0x000003E0    /* PHY Address */
  50 #define XEL_MDIOADDR_PHYADR_SHIFT 5
  51 #define XEL_MDIOADDR_OP_MASK      0x00000400    /* RD/WR Operation */
  52
  53 /* MDIO Write Data Register Bit Masks */
  54 #define XEL_MDIOWR_WRDATA_MASK    0x0000FFFF    /* Data to be Written */
  55
  56 /* MDIO Read Data Register Bit Masks */
  57 #define XEL_MDIORD_RDDATA_MASK    0x0000FFFF    /* Data to be Read */
  58
  59 /* MDIO Control Register Bit Masks */
  60 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001    /* MDIO Status Mask */
  61 #define XEL_MDIOCTRL_MDIOEN_MASK  0x00000008    /* MDIO Enable */
  62
  63 struct emaclite_regs {
  64         u32 tx_ping; /* 0x0 - TX Ping buffer */
  65         u32 reserved1[504];
  66         u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
  67         u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
  68         u32 mdiord;/* 0x7ec - MDIO Read Data Register */
  69         u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
  70         u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
  71         u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
  72         u32 tx_ping_tsr; /* 0x7fc - Tx status */
  73         u32 tx_pong; /* 0x800 - TX Pong buffer */
  74         u32 reserved2[508];
  75         u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
  76         u32 reserved3; /* 0xff8 */
  77         u32 tx_pong_tsr; /* 0xffc - Tx status */
  78         u32 rx_ping; /* 0x1000 - Receive Buffer */
  79         u32 reserved4[510];
  80         u32 rx_ping_rsr; /* 0x17fc - Rx status */
  81         u32 rx_pong; /* 0x1800 - Receive Buffer */
  82         u32 reserved5[510];
  83         u32 rx_pong_rsr; /* 0x1ffc - Rx status */
  84 };
  85
  86 struct xemaclite {
  87         bool use_rx_pong_buffer_next;   /* Next RX buffer to read from */
  88         u32 txpp;               /* TX ping pong buffer */
  89         u32 rxpp;               /* RX ping pong buffer */
  90         int phyaddr;
  91         struct emaclite_regs *regs;
  92         struct phy_device *phydev;
  93         struct mii_dev *bus;
  94 };
  95
  96 static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */
  97
  98 static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
  99 {
 100         u32 i;
 101         u32 alignbuffer;
 102         u32 *to32ptr;
 103         u32 *from32ptr;
 104         u8 *to8ptr;
 105         u8 *from8ptr;
 106
 107         from32ptr = (u32 *) srcptr;
 108
 109         /* Word aligned buffer, no correction needed. */
 110         to32ptr = (u32 *) destptr;
 111         while (bytecount > 3) {
 112                 *to32ptr++ = *from32ptr++;
 113                 bytecount -= 4;
 114         }
 115         to8ptr = (u8 *) to32ptr;
 116
 117         alignbuffer = *from32ptr++;
 118         from8ptr = (u8 *) &alignbuffer;
 119
 120         for (i = 0; i < bytecount; i++)
 121                 *to8ptr++ = *from8ptr++;
 122 }
 123
 124 static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount)
 125 {
 126         u32 i;
 127         u32 alignbuffer;
 128         u32 *to32ptr = (u32 *) destptr;
 129         u32 *from32ptr;
 130         u8 *to8ptr;
 131         u8 *from8ptr;
 132
 133         from32ptr = (u32 *) srcptr;
 134         while (bytecount > 3) {
 135
 136                 *to32ptr++ = *from32ptr++;
 137                 bytecount -= 4;
 138         }
 139
 140         alignbuffer = 0;
 141         to8ptr = (u8 *) &alignbuffer;
 142         from8ptr = (u8 *) from32ptr;
 143
 144         for (i = 0; i < bytecount; i++)
 145                 *to8ptr++ = *from8ptr++;
 146
 147         *to32ptr++ = alignbuffer;
 148 }
 149
 150 static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
 151                         bool set, unsigned int timeout)
 152 {
 153         u32 val;
 154         unsigned long start = get_timer(0);
 155
 156         while (1) {
 157                 val = readl(reg);
 158
 159                 if (!set)
 160                         val = ~val;
 161
 162                 if ((val & mask) == mask)
 163                         return 0;
 164
 165                 if (get_timer(start) > timeout)
 166                         break;
 167
 168                 if (ctrlc()) {
 169                         puts("Abort\n");
 170                         return -EINTR;
 171                 }
 172
 173                 udelay(1);
 174         }
 175
 176         debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
 177               func, reg, mask, set);
 178
 179         return -ETIMEDOUT;
 180 }
 181
 182 static int mdio_wait(struct emaclite_regs *regs)
 183 {
 184         return wait_for_bit(__func__, &regs->mdioctrl,
 185                             XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
 186 }
 187
 188 static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
 189                    u16 *data)
 190 {
 191         struct emaclite_regs *regs = emaclite->regs;
 192
 193         if (mdio_wait(regs))
 194                 return 1;
 195
 196         u32 ctrl_reg = in_be32(&regs->mdioctrl);
 197         out_be32(&regs->mdioaddr, XEL_MDIOADDR_OP_MASK |
 198                  ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
 199         out_be32(&regs->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
 200
 201         if (mdio_wait(regs))
 202                 return 1;
 203
 204         /* Read data */
 205         *data = in_be32(&regs->mdiord);
 206         return 0;
 207 }
 208
 209 static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
 210                     u16 data)
 211 {
 212         struct emaclite_regs *regs = emaclite->regs;
 213
 214         if (mdio_wait(regs))
 215                 return 1;
 216
 217         /*
 218          * Write the PHY address, register number and clear the OP bit in the
 219          * MDIO Address register and then write the value into the MDIO Write
 220          * Data register. Finally, set the Status bit in the MDIO Control
 221          * register to start a MDIO write transaction.
 222          */
 223         u32 ctrl_reg = in_be32(&regs->mdioctrl);
 224         out_be32(&regs->mdioaddr, ~XEL_MDIOADDR_OP_MASK &
 225                  ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
 226         out_be32(&regs->mdiowr, data);
 227         out_be32(&regs->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
 228
 229         if (mdio_wait(regs))
 230                 return 1;
 231
 232         return 0;
 233 }
 234
 235 static void emaclite_stop(struct udevice *dev)
 236 {
 237         debug("eth_stop\n");
 238 }
 239
 240 /* Use MII register 1 (MII status register) to detect PHY */
 241 #define PHY_DETECT_REG  1
 242
 243 /* Mask used to verify certain PHY features (or register contents)
 244  * in the register above:
 245  *  0x1000: 10Mbps full duplex support
 246  *  0x0800: 10Mbps half duplex support
 247  *  0x0008: Auto-negotiation support
 248  */
 249 #define PHY_DETECT_MASK 0x1808
 250
 251 static int setup_phy(struct udevice *dev)
 252 {
 253         int i;
 254         u16 phyreg;
 255         struct xemaclite *emaclite = dev_get_priv(dev);
 256         struct phy_device *phydev;
 257
 258         u32 supported = SUPPORTED_10baseT_Half |
 259                         SUPPORTED_10baseT_Full |
 260                         SUPPORTED_100baseT_Half |
 261                         SUPPORTED_100baseT_Full;
 262
 263         if (emaclite->phyaddr != -1) {
 264                 phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
 265                 if ((phyreg != 0xFFFF) &&
 266                     ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
 267                         /* Found a valid PHY address */
 268                         debug("Default phy address %d is valid\n",
 269                               emaclite->phyaddr);
 270                 } else {
 271                         debug("PHY address is not setup correctly %d\n",
 272                               emaclite->phyaddr);
 273                         emaclite->phyaddr = -1;
 274                 }
 275         }
 276
 277         if (emaclite->phyaddr == -1) {
 278                 /* detect the PHY address */
 279                 for (i = 31; i >= 0; i--) {
 280                         phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
 281                         if ((phyreg != 0xFFFF) &&
 282                             ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
 283                                 /* Found a valid PHY address */
 284                                 emaclite->phyaddr = i;
 285                                 debug("emaclite: Found valid phy address, %d\n",
 286                                       i);
 287                                 break;
 288                         }
 289                 }
 290         }
 291
 292         /* interface - look at tsec */
 293         phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
 294                              PHY_INTERFACE_MODE_MII);
 295         /*
 296          * Phy can support 1000baseT but device NOT that's why phydev->supported
 297          * must be setup for 1000baseT. phydev->advertising setups what speeds
 298          * will be used for autonegotiation where 1000baseT must be disabled.
 299          */
 300         phydev->supported = supported | SUPPORTED_1000baseT_Half |
 301                                                 SUPPORTED_1000baseT_Full;
 302         phydev->advertising = supported;
 303         emaclite->phydev = phydev;
 304         phy_config(phydev);
 305         phy_startup(phydev);
 306
 307         if (!phydev->link) {
 308                 printf("%s: No link.\n", phydev->dev->name);
 309                 return 0;
 310         }
 311
 312         /* Do not setup anything */
 313         return 1;
 314 }
 315
 316 static int emaclite_start(struct udevice *dev)
 317 {
 318         struct xemaclite *emaclite = dev_get_priv(dev);
 319         struct eth_pdata *pdata = dev_get_platdata(dev);
 320         struct emaclite_regs *regs = emaclite->regs;
 321
 322         debug("EmacLite Initialization Started\n");
 323
 324 /*
 325  * TX - TX_PING & TX_PONG initialization
 326  */
 327         /* Restart PING TX */
 328         out_be32(&regs->tx_ping_tsr, 0);
 329         /* Copy MAC address */
 330         xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_ping,
 331                                ENET_ADDR_LENGTH);
 332         /* Set the length */
 333         out_be32(&regs->tx_ping_tplr, ENET_ADDR_LENGTH);
 334         /* Update the MAC address in the EMAC Lite */
 335         out_be32(&regs->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR);
 336         /* Wait for EMAC Lite to finish with the MAC address update */
 337         while ((in_be32 (&regs->tx_ping_tsr) &
 338                 XEL_TSR_PROG_MAC_ADDR) != 0)
 339                 ;
 340
 341         if (emaclite->txpp) {
 342                 /* The same operation with PONG TX */
 343                 out_be32(&regs->tx_pong_tsr, 0);
 344                 xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_pong,
 345                                        ENET_ADDR_LENGTH);
 346                 out_be32(&regs->tx_pong_tplr, ENET_ADDR_LENGTH);
 347                 out_be32(&regs->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR);
 348                 while ((in_be32(&regs->tx_pong_tsr) &
 349                        XEL_TSR_PROG_MAC_ADDR) != 0)
 350                         ;
 351         }
 352
 353 /*
 354  * RX - RX_PING & RX_PONG initialization
 355  */
 356         /* Write out the value to flush the RX buffer */
 357         out_be32(&regs->rx_ping_rsr, XEL_RSR_RECV_IE_MASK);
 358
 359         if (emaclite->rxpp)
 360                 out_be32(&regs->rx_pong_rsr, XEL_RSR_RECV_IE_MASK);
 361
 362         out_be32(&regs->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);
 363         if (in_be32(&regs->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
 364                 if (!setup_phy(dev))
 365                         return -1;
 366
 367         debug("EmacLite Initialization complete\n");
 368         return 0;
 369 }
 370
 371 static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
 372 {
 373         u32 tmp;
 374         struct emaclite_regs *regs = emaclite->regs;
 375
 376         /*
 377          * Read the other buffer register
 378          * and determine if the other buffer is available
 379          */
 380         tmp = ~in_be32(&regs->tx_ping_tsr);
 381         if (emaclite->txpp)
 382                 tmp |= ~in_be32(&regs->tx_pong_tsr);
 383
 384         return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
 385 }
 386
 387 static int emaclite_send(struct udevice *dev, void *ptr, int len)
 388 {
 389         u32 reg;
 390         struct xemaclite *emaclite = dev_get_priv(dev);
 391         struct emaclite_regs *regs = emaclite->regs;
 392
 393         u32 maxtry = 1000;
 394
 395         if (len > PKTSIZE)
 396                 len = PKTSIZE;
 397
 398         while (xemaclite_txbufferavailable(emaclite) && maxtry) {
 399                 udelay(10);
 400                 maxtry--;
 401         }
 402
 403         if (!maxtry) {
 404                 printf("Error: Timeout waiting for ethernet TX buffer\n");
 405                 /* Restart PING TX */
 406                 out_be32(&regs->tx_ping_tsr, 0);
 407                 if (emaclite->txpp) {
 408                         out_be32(&regs->tx_pong_tsr, 0);
 409                 }
 410                 return -1;
 411         }
 412
 413         /* Determine if the expected buffer address is empty */
 414         reg = in_be32(&regs->tx_ping_tsr);
 415         if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
 416                 debug("Send packet from tx_ping buffer\n");
 417                 /* Write the frame to the buffer */
 418                 xemaclite_alignedwrite(ptr, &regs->tx_ping, len);
 419                 out_be32(&regs->tx_ping_tplr, len &
 420                         (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO));
 421                 reg = in_be32(&regs->tx_ping_tsr);
 422                 reg |= XEL_TSR_XMIT_BUSY_MASK;
 423                 out_be32(&regs->tx_ping_tsr, reg);
 424                 return 0;
 425         }
 426
 427         if (emaclite->txpp) {
 428                 /* Determine if the expected buffer address is empty */
 429                 reg = in_be32(&regs->tx_pong_tsr);
 430                 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
 431                         debug("Send packet from tx_pong buffer\n");
 432                         /* Write the frame to the buffer */
 433                         xemaclite_alignedwrite(ptr, &regs->tx_pong, len);
 434                         out_be32(&regs->tx_pong_tplr, len &
 435                                  (XEL_TPLR_LENGTH_MASK_HI |
 436                                   XEL_TPLR_LENGTH_MASK_LO));
 437                         reg = in_be32(&regs->tx_pong_tsr);
 438                         reg |= XEL_TSR_XMIT_BUSY_MASK;
 439                         out_be32(&regs->tx_pong_tsr, reg);
 440                         return 0;
 441                 }
 442         }
 443
 444         puts("Error while sending frame\n");
 445         return -1;
 446 }
 447
 448 static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp)
 449 {
 450         u32 length, first_read, reg, attempt = 0;
 451         void *addr, *ack;
 452         struct xemaclite *emaclite = dev->priv;
 453         struct emaclite_regs *regs = emaclite->regs;
 454         struct ethernet_hdr *eth;
 455         struct ip_udp_hdr *ip;
 456
 457 try_again:
 458         if (!emaclite->use_rx_pong_buffer_next) {
 459                 reg = in_be32(&regs->rx_ping_rsr);
 460                 debug("Testing data at rx_ping\n");
 461                 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
 462                         debug("Data found in rx_ping buffer\n");
 463                         addr = &regs->rx_ping;
 464                         ack = &regs->rx_ping_rsr;
 465                 } else {
 466                         debug("Data not found in rx_ping buffer\n");
 467                         /* Pong buffer is not available - return immediately */
 468                         if (!emaclite->rxpp)
 469                                 return -1;
 470
 471                         /* Try pong buffer if this is first attempt */
 472                         if (attempt++)
 473                                 return -1;
 474                         emaclite->use_rx_pong_buffer_next =
 475                                         !emaclite->use_rx_pong_buffer_next;
 476                         goto try_again;
 477                 }
 478         } else {
 479                 reg = in_be32(&regs->rx_pong_rsr);
 480                 debug("Testing data at rx_pong\n");
 481                 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
 482                         debug("Data found in rx_pong buffer\n");
 483                         addr = &regs->rx_pong;
 484                         ack = &regs->rx_pong_rsr;
 485                 } else {
 486                         debug("Data not found in rx_pong buffer\n");
 487                         /* Try ping buffer if this is first attempt */
 488                         if (attempt++)
 489                                 return -1;
 490                         emaclite->use_rx_pong_buffer_next =
 491                                         !emaclite->use_rx_pong_buffer_next;
 492                         goto try_again;
 493                 }
 494         }
 495
 496         /* Read all bytes for ARP packet with 32bit alignment - 48bytes  */
 497         first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4);
 498         xemaclite_alignedread(addr, etherrxbuff, first_read);
 499
 500         /* Detect real packet size */
 501         eth = (struct ethernet_hdr *)etherrxbuff;
 502         switch (ntohs(eth->et_protlen)) {
 503         case PROT_ARP:
 504                 length = first_read;
 505                 debug("ARP Packet %x\n", length);
 506                 break;
 507         case PROT_IP:
 508                 ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE);
 509                 length = ntohs(ip->ip_len);
 510                 length += ETHER_HDR_SIZE + ETH_FCS_LEN;
 511                 debug("IP Packet %x\n", length);
 512                 break;
 513         default:
 514                 debug("Other Packet\n");
 515                 length = PKTSIZE;
 516                 break;
 517         }
 518
 519         /* Read the rest of the packet which is longer then first read */
 520         if (length != first_read)
 521                 xemaclite_alignedread(addr + first_read,
 522                                       etherrxbuff + first_read,
 523                                       length - first_read);
 524
 525         /* Acknowledge the frame */
 526         reg = in_be32(ack);
 527         reg &= ~XEL_RSR_RECV_DONE_MASK;
 528         out_be32(ack, reg);
 529
 530         debug("Packet receive from 0x%p, length %dB\n", addr, length);
 531         *packetp = etherrxbuff;
 532         return length;
 533 }
 534
 535 static int emaclite_miiphy_read(struct mii_dev *bus, int addr,
 536                                 int devad, int reg)
 537 {
 538         u32 ret;
 539         u16 val = 0;
 540
 541         ret = phyread(bus->priv, addr, reg, &val);
 542         debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret);
 543         return val;
 544 }
 545
 546 static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad,
 547                                  int reg, u16 value)
 548 {
 549         debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
 550         return phywrite(bus->priv, addr, reg, value);
 551 }
 552
 553 static int emaclite_probe(struct udevice *dev)
 554 {
 555         struct xemaclite *emaclite = dev_get_priv(dev);
 556         int ret;
 557
 558         emaclite->bus = mdio_alloc();
 559         emaclite->bus->read = emaclite_miiphy_read;
 560         emaclite->bus->write = emaclite_miiphy_write;
 561         emaclite->bus->priv = emaclite;
 562         strcpy(emaclite->bus->name, "emaclite");
 563
 564         ret = mdio_register(emaclite->bus);
 565         if (ret)
 566                 return ret;
 567
 568         return 0;
 569 }
 570
 571 static int emaclite_remove(struct udevice *dev)
 572 {
 573         struct xemaclite *emaclite = dev_get_priv(dev);
 574
 575         free(emaclite->phydev);
 576         mdio_unregister(emaclite->bus);
 577         mdio_free(emaclite->bus);
 578
 579         return 0;
 580 }
 581
 582 static const struct eth_ops emaclite_ops = {
 583         .start = emaclite_start,
 584         .send = emaclite_send,
 585         .recv = emaclite_recv,
 586         .stop = emaclite_stop,
 587 };
 588
 589 static int emaclite_ofdata_to_platdata(struct udevice *dev)
 590 {
 591         struct eth_pdata *pdata = dev_get_platdata(dev);
 592         struct xemaclite *emaclite = dev_get_priv(dev);
 593         int offset = 0;
 594
 595         pdata->iobase = (phys_addr_t)dev_get_addr(dev);
 596         emaclite->regs = (struct emaclite_regs *)pdata->iobase;
 597
 598         emaclite->phyaddr = -1;
 599
 600         offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
 601                                       "phy-handle");
 602         if (offset > 0)
 603                 emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
 604                                                    "reg", -1);
 605
 606         emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
 607                                         "xlnx,tx-ping-pong", 0);
 608         emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
 609                                         "xlnx,rx-ping-pong", 0);
 610
 611         printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
 612                emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
 613
 614         return 0;
 615 }
 616
 617 static const struct udevice_id emaclite_ids[] = {
 618         { .compatible = "xlnx,xps-ethernetlite-1.00.a" },
 619         { }
 620 };
 621
 622 U_BOOT_DRIVER(emaclite) = {
 623         .name   = "emaclite",
 624         .id     = UCLASS_ETH,
 625         .of_match = emaclite_ids,
 626         .ofdata_to_platdata = emaclite_ofdata_to_platdata,
 627         .probe  = emaclite_probe,
 628         .remove = emaclite_remove,
 629         .ops    = &emaclite_ops,
 630         .priv_auto_alloc_size = sizeof(struct xemaclite),
 631         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 632 };