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git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/net/xilinx_emaclite.c
2 * (C) Copyright 2007-2009 Michal Simek
3 * (C) Copyright 2003 Xilinx Inc.
5 * Michal SIMEK <monstr@monstr.eu>
7 * SPDX-License-Identifier: GPL-2.0+
19 #define ENET_ADDR_LENGTH 6
21 /* EmacLite constants */
22 #define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */
23 #define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */
24 #define XEL_TSR_OFFSET 0x07FC /* Tx status */
25 #define XEL_RSR_OFFSET 0x17FC /* Rx status */
26 #define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
29 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
30 /* Xmit interrupt enable bit */
31 #define XEL_TSR_XMIT_IE_MASK 0x00000008UL
32 /* Buffer is active, SW bit only */
33 #define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL
34 /* Program the MAC address */
35 #define XEL_TSR_PROGRAM_MASK 0x00000002UL
36 /* define for programming the MAC address into the EMAC Lite */
37 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
39 /* Transmit packet length upper byte */
40 #define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
41 /* Transmit packet length lower byte */
42 #define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
45 #define XEL_RSR_RECV_DONE_MASK 0x00000001UL
46 /* Recv interrupt enable bit */
47 #define XEL_RSR_RECV_IE_MASK 0x00000008UL
50 u32 nexttxbuffertouse
; /* Next TX buffer to write to */
51 u32 nextrxbuffertouse
; /* Next RX buffer to read from */
52 u32 txpp
; /* TX ping pong buffer */
53 u32 rxpp
; /* RX ping pong buffer */
56 static u32 etherrxbuff
[PKTSIZE_ALIGN
/4]; /* Receive buffer */
58 static void xemaclite_alignedread(u32
*srcptr
, void *destptr
, u32 bytecount
)
67 from32ptr
= (u32
*) srcptr
;
69 /* Word aligned buffer, no correction needed. */
70 to32ptr
= (u32
*) destptr
;
71 while (bytecount
> 3) {
72 *to32ptr
++ = *from32ptr
++;
75 to8ptr
= (u8
*) to32ptr
;
77 alignbuffer
= *from32ptr
++;
78 from8ptr
= (u8
*) &alignbuffer
;
80 for (i
= 0; i
< bytecount
; i
++)
81 *to8ptr
++ = *from8ptr
++;
84 static void xemaclite_alignedwrite(void *srcptr
, u32 destptr
, u32 bytecount
)
88 u32
*to32ptr
= (u32
*) destptr
;
93 from32ptr
= (u32
*) srcptr
;
94 while (bytecount
> 3) {
96 *to32ptr
++ = *from32ptr
++;
101 to8ptr
= (u8
*) &alignbuffer
;
102 from8ptr
= (u8
*) from32ptr
;
104 for (i
= 0; i
< bytecount
; i
++)
105 *to8ptr
++ = *from8ptr
++;
107 *to32ptr
++ = alignbuffer
;
110 static void emaclite_halt(struct eth_device
*dev
)
115 static int emaclite_init(struct eth_device
*dev
, bd_t
*bis
)
117 struct xemaclite
*emaclite
= dev
->priv
;
118 debug("EmacLite Initialization Started\n");
121 * TX - TX_PING & TX_PONG initialization
123 /* Restart PING TX */
124 out_be32 (dev
->iobase
+ XEL_TSR_OFFSET
, 0);
125 /* Copy MAC address */
126 xemaclite_alignedwrite(dev
->enetaddr
, dev
->iobase
, ENET_ADDR_LENGTH
);
128 out_be32 (dev
->iobase
+ XEL_TPLR_OFFSET
, ENET_ADDR_LENGTH
);
129 /* Update the MAC address in the EMAC Lite */
130 out_be32 (dev
->iobase
+ XEL_TSR_OFFSET
, XEL_TSR_PROG_MAC_ADDR
);
131 /* Wait for EMAC Lite to finish with the MAC address update */
132 while ((in_be32 (dev
->iobase
+ XEL_TSR_OFFSET
) &
133 XEL_TSR_PROG_MAC_ADDR
) != 0)
136 if (emaclite
->txpp
) {
137 /* The same operation with PONG TX */
138 out_be32 (dev
->iobase
+ XEL_TSR_OFFSET
+ XEL_BUFFER_OFFSET
, 0);
139 xemaclite_alignedwrite(dev
->enetaddr
, dev
->iobase
+
140 XEL_BUFFER_OFFSET
, ENET_ADDR_LENGTH
);
141 out_be32 (dev
->iobase
+ XEL_TPLR_OFFSET
, ENET_ADDR_LENGTH
);
142 out_be32 (dev
->iobase
+ XEL_TSR_OFFSET
+ XEL_BUFFER_OFFSET
,
143 XEL_TSR_PROG_MAC_ADDR
);
144 while ((in_be32 (dev
->iobase
+ XEL_TSR_OFFSET
+
145 XEL_BUFFER_OFFSET
) & XEL_TSR_PROG_MAC_ADDR
) != 0)
150 * RX - RX_PING & RX_PONG initialization
152 /* Write out the value to flush the RX buffer */
153 out_be32 (dev
->iobase
+ XEL_RSR_OFFSET
, XEL_RSR_RECV_IE_MASK
);
156 out_be32 (dev
->iobase
+ XEL_RSR_OFFSET
+ XEL_BUFFER_OFFSET
,
157 XEL_RSR_RECV_IE_MASK
);
159 debug("EmacLite Initialization complete\n");
163 static int xemaclite_txbufferavailable(struct eth_device
*dev
)
168 struct xemaclite
*emaclite
= dev
->priv
;
171 * Read the other buffer register
172 * and determine if the other buffer is available
174 reg
= in_be32 (dev
->iobase
+
175 emaclite
->nexttxbuffertouse
+ 0);
176 txpingbusy
= ((reg
& XEL_TSR_XMIT_BUSY_MASK
) ==
177 XEL_TSR_XMIT_BUSY_MASK
);
179 reg
= in_be32 (dev
->iobase
+
180 (emaclite
->nexttxbuffertouse
^ XEL_TSR_OFFSET
) + 0);
181 txpongbusy
= ((reg
& XEL_TSR_XMIT_BUSY_MASK
) ==
182 XEL_TSR_XMIT_BUSY_MASK
);
184 return !(txpingbusy
&& txpongbusy
);
187 static int emaclite_send(struct eth_device
*dev
, void *ptr
, int len
)
191 struct xemaclite
*emaclite
= dev
->priv
;
198 while (!xemaclite_txbufferavailable(dev
) && maxtry
) {
204 printf("Error: Timeout waiting for ethernet TX buffer\n");
205 /* Restart PING TX */
206 out_be32 (dev
->iobase
+ XEL_TSR_OFFSET
, 0);
207 if (emaclite
->txpp
) {
208 out_be32 (dev
->iobase
+ XEL_TSR_OFFSET
+
209 XEL_BUFFER_OFFSET
, 0);
214 /* Determine the expected TX buffer address */
215 baseaddress
= (dev
->iobase
+ emaclite
->nexttxbuffertouse
);
217 /* Determine if the expected buffer address is empty */
218 reg
= in_be32 (baseaddress
+ XEL_TSR_OFFSET
);
219 if (((reg
& XEL_TSR_XMIT_BUSY_MASK
) == 0)
220 && ((in_be32 ((baseaddress
) + XEL_TSR_OFFSET
)
221 & XEL_TSR_XMIT_ACTIVE_MASK
) == 0)) {
224 emaclite
->nexttxbuffertouse
^= XEL_BUFFER_OFFSET
;
226 debug("Send packet from 0x%x\n", baseaddress
);
227 /* Write the frame to the buffer */
228 xemaclite_alignedwrite(ptr
, baseaddress
, len
);
229 out_be32 (baseaddress
+ XEL_TPLR_OFFSET
,(len
&
230 (XEL_TPLR_LENGTH_MASK_HI
| XEL_TPLR_LENGTH_MASK_LO
)));
231 reg
= in_be32 (baseaddress
+ XEL_TSR_OFFSET
);
232 reg
|= XEL_TSR_XMIT_BUSY_MASK
;
233 if ((reg
& XEL_TSR_XMIT_IE_MASK
) != 0)
234 reg
|= XEL_TSR_XMIT_ACTIVE_MASK
;
235 out_be32 (baseaddress
+ XEL_TSR_OFFSET
, reg
);
239 if (emaclite
->txpp
) {
240 /* Switch to second buffer */
241 baseaddress
^= XEL_BUFFER_OFFSET
;
242 /* Determine if the expected buffer address is empty */
243 reg
= in_be32 (baseaddress
+ XEL_TSR_OFFSET
);
244 if (((reg
& XEL_TSR_XMIT_BUSY_MASK
) == 0)
245 && ((in_be32 ((baseaddress
) + XEL_TSR_OFFSET
)
246 & XEL_TSR_XMIT_ACTIVE_MASK
) == 0)) {
247 debug("Send packet from 0x%x\n", baseaddress
);
248 /* Write the frame to the buffer */
249 xemaclite_alignedwrite(ptr
, baseaddress
, len
);
250 out_be32 (baseaddress
+ XEL_TPLR_OFFSET
, (len
&
251 (XEL_TPLR_LENGTH_MASK_HI
|
252 XEL_TPLR_LENGTH_MASK_LO
)));
253 reg
= in_be32 (baseaddress
+ XEL_TSR_OFFSET
);
254 reg
|= XEL_TSR_XMIT_BUSY_MASK
;
255 if ((reg
& XEL_TSR_XMIT_IE_MASK
) != 0)
256 reg
|= XEL_TSR_XMIT_ACTIVE_MASK
;
257 out_be32 (baseaddress
+ XEL_TSR_OFFSET
, reg
);
262 puts("Error while sending frame\n");
266 static int emaclite_recv(struct eth_device
*dev
)
271 struct xemaclite
*emaclite
= dev
->priv
;
273 baseaddress
= dev
->iobase
+ emaclite
->nextrxbuffertouse
;
274 reg
= in_be32 (baseaddress
+ XEL_RSR_OFFSET
);
275 debug("Testing data at address 0x%x\n", baseaddress
);
276 if ((reg
& XEL_RSR_RECV_DONE_MASK
) == XEL_RSR_RECV_DONE_MASK
) {
278 emaclite
->nextrxbuffertouse
^= XEL_BUFFER_OFFSET
;
281 if (!emaclite
->rxpp
) {
282 debug("No data was available - address 0x%x\n",
286 baseaddress
^= XEL_BUFFER_OFFSET
;
287 reg
= in_be32 (baseaddress
+ XEL_RSR_OFFSET
);
288 if ((reg
& XEL_RSR_RECV_DONE_MASK
) !=
289 XEL_RSR_RECV_DONE_MASK
) {
290 debug("No data was available - address 0x%x\n",
296 /* Get the length of the frame that arrived */
297 switch(((ntohl(in_be32 (baseaddress
+ XEL_RXBUFF_OFFSET
+ 0xC))) &
298 0xFFFF0000 ) >> 16) {
300 length
= 42 + 20; /* FIXME size of ARP */
301 debug("ARP Packet\n");
305 (((ntohl(in_be32 (baseaddress
+ XEL_RXBUFF_OFFSET
+
306 0x10))) & 0xFFFF0000) >> 16);
307 /* FIXME size of IP packet */
308 debug ("IP Packet\n");
311 debug("Other Packet\n");
316 xemaclite_alignedread((u32
*) (baseaddress
+ XEL_RXBUFF_OFFSET
),
317 etherrxbuff
, length
);
319 /* Acknowledge the frame */
320 reg
= in_be32 (baseaddress
+ XEL_RSR_OFFSET
);
321 reg
&= ~XEL_RSR_RECV_DONE_MASK
;
322 out_be32 (baseaddress
+ XEL_RSR_OFFSET
, reg
);
324 debug("Packet receive from 0x%x, length %dB\n", baseaddress
, length
);
325 net_process_received_packet((uchar
*)etherrxbuff
, length
);
330 int xilinx_emaclite_initialize(bd_t
*bis
, unsigned long base_addr
,
333 struct eth_device
*dev
;
334 struct xemaclite
*emaclite
;
336 dev
= calloc(1, sizeof(*dev
));
340 emaclite
= calloc(1, sizeof(struct xemaclite
));
341 if (emaclite
== NULL
) {
346 dev
->priv
= emaclite
;
348 emaclite
->txpp
= txpp
;
349 emaclite
->rxpp
= rxpp
;
351 sprintf(dev
->name
, "Xelite.%lx", base_addr
);
353 dev
->iobase
= base_addr
;
354 dev
->init
= emaclite_init
;
355 dev
->halt
= emaclite_halt
;
356 dev
->send
= emaclite_send
;
357 dev
->recv
= emaclite_recv
;
364 #ifdef CONFIG_OF_CONTROL
365 int xilinx_emaclite_of_init(const void *blob
)
372 offset
= fdt_node_offset_by_compatible(blob
, offset
,
373 "xlnx,xps-ethernetlite-1.00.a");
375 reg
= fdtdec_get_addr(blob
, offset
, "reg");
376 if (reg
!= FDT_ADDR_T_NONE
) {
377 u32 rxpp
= fdtdec_get_int(blob
, offset
,
378 "xlnx,rx-ping-pong", 0);
379 u32 txpp
= fdtdec_get_int(blob
, offset
,
380 "xlnx,tx-ping-pong", 0);
381 ret
|= xilinx_emaclite_initialize(NULL
, reg
,
384 debug("EMACLITE: Can't get base address\n");
388 } while (offset
!= -1);