drivers/net/xilinx_emaclite.c

   1 /*
   2  * (C) Copyright 2007-2009 Michal Simek
   3  * (C) Copyright 2003 Xilinx Inc.
   4  *
   5  * Michal SIMEK <monstr@monstr.eu>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <net.h>
  12 #include <config.h>
  13 #include <console.h>
  14 #include <malloc.h>
  15 #include <asm/io.h>
  16 #include <phy.h>
  17 #include <miiphy.h>
  18 #include <fdtdec.h>
  19 #include <asm-generic/errno.h>
  20
  21 #undef DEBUG
  22
  23 #define ENET_ADDR_LENGTH        6
  24
  25 /* EmacLite constants */
  26 #define XEL_BUFFER_OFFSET       0x0800  /* Next buffer's offset */
  27 #define XEL_TPLR_OFFSET         0x07F4  /* Tx packet length */
  28 #define XEL_TSR_OFFSET          0x07FC  /* Tx status */
  29 #define XEL_RSR_OFFSET          0x17FC  /* Rx status */
  30 #define XEL_RXBUFF_OFFSET       0x1000  /* Receive Buffer */
  31
  32 /* Xmit complete */
  33 #define XEL_TSR_XMIT_BUSY_MASK          0x00000001UL
  34 /* Xmit interrupt enable bit */
  35 #define XEL_TSR_XMIT_IE_MASK            0x00000008UL
  36 /* Buffer is active, SW bit only */
  37 #define XEL_TSR_XMIT_ACTIVE_MASK        0x80000000UL
  38 /* Program the MAC address */
  39 #define XEL_TSR_PROGRAM_MASK            0x00000002UL
  40 /* define for programming the MAC address into the EMAC Lite */
  41 #define XEL_TSR_PROG_MAC_ADDR   (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
  42
  43 /* Transmit packet length upper byte */
  44 #define XEL_TPLR_LENGTH_MASK_HI         0x0000FF00UL
  45 /* Transmit packet length lower byte */
  46 #define XEL_TPLR_LENGTH_MASK_LO         0x000000FFUL
  47
  48 /* Recv complete */
  49 #define XEL_RSR_RECV_DONE_MASK          0x00000001UL
  50 /* Recv interrupt enable bit */
  51 #define XEL_RSR_RECV_IE_MASK            0x00000008UL
  52
  53 /* MDIO Address Register Bit Masks */
  54 #define XEL_MDIOADDR_REGADR_MASK  0x0000001F    /* Register Address */
  55 #define XEL_MDIOADDR_PHYADR_MASK  0x000003E0    /* PHY Address */
  56 #define XEL_MDIOADDR_PHYADR_SHIFT 5
  57 #define XEL_MDIOADDR_OP_MASK      0x00000400    /* RD/WR Operation */
  58
  59 /* MDIO Write Data Register Bit Masks */
  60 #define XEL_MDIOWR_WRDATA_MASK    0x0000FFFF    /* Data to be Written */
  61
  62 /* MDIO Read Data Register Bit Masks */
  63 #define XEL_MDIORD_RDDATA_MASK    0x0000FFFF    /* Data to be Read */
  64
  65 /* MDIO Control Register Bit Masks */
  66 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001    /* MDIO Status Mask */
  67 #define XEL_MDIOCTRL_MDIOEN_MASK  0x00000008    /* MDIO Enable */
  68
  69 struct emaclite_regs {
  70         u32 tx_ping; /* 0x0 - TX Ping buffer */
  71         u32 reserved1[504];
  72         u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
  73         u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
  74         u32 mdiord;/* 0x7ec - MDIO Read Data Register */
  75         u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
  76         u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
  77         u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
  78         u32 tx_ping_tsr; /* 0x7fc - Tx status */
  79         u32 tx_pong; /* 0x800 - TX Pong buffer */
  80         u32 reserved2[508];
  81         u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
  82         u32 reserved3; /* 0xff8 */
  83         u32 tx_pong_tsr; /* 0xffc - Tx status */
  84         u32 rx_ping; /* 0x1000 - Receive Buffer */
  85         u32 reserved4[510];
  86         u32 rx_ping_rsr; /* 0x17fc - Rx status */
  87         u32 rx_pong; /* 0x1800 - Receive Buffer */
  88         u32 reserved5[510];
  89         u32 rx_pong_rsr; /* 0x1ffc - Rx status */
  90 };
  91
  92 struct xemaclite {
  93         u32 nexttxbuffertouse;  /* Next TX buffer to write to */
  94         u32 nextrxbuffertouse;  /* Next RX buffer to read from */
  95         u32 txpp;               /* TX ping pong buffer */
  96         u32 rxpp;               /* RX ping pong buffer */
  97         int phyaddr;
  98         struct emaclite_regs *regs;
  99         struct phy_device *phydev;
 100         struct mii_dev *bus;
 101 };
 102
 103 static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
 104
 105 static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
 106 {
 107         u32 i;
 108         u32 alignbuffer;
 109         u32 *to32ptr;
 110         u32 *from32ptr;
 111         u8 *to8ptr;
 112         u8 *from8ptr;
 113
 114         from32ptr = (u32 *) srcptr;
 115
 116         /* Word aligned buffer, no correction needed. */
 117         to32ptr = (u32 *) destptr;
 118         while (bytecount > 3) {
 119                 *to32ptr++ = *from32ptr++;
 120                 bytecount -= 4;
 121         }
 122         to8ptr = (u8 *) to32ptr;
 123
 124         alignbuffer = *from32ptr++;
 125         from8ptr = (u8 *) &alignbuffer;
 126
 127         for (i = 0; i < bytecount; i++)
 128                 *to8ptr++ = *from8ptr++;
 129 }
 130
 131 static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount)
 132 {
 133         u32 i;
 134         u32 alignbuffer;
 135         u32 *to32ptr = (u32 *) destptr;
 136         u32 *from32ptr;
 137         u8 *to8ptr;
 138         u8 *from8ptr;
 139
 140         from32ptr = (u32 *) srcptr;
 141         while (bytecount > 3) {
 142
 143                 *to32ptr++ = *from32ptr++;
 144                 bytecount -= 4;
 145         }
 146
 147         alignbuffer = 0;
 148         to8ptr = (u8 *) &alignbuffer;
 149         from8ptr = (u8 *) from32ptr;
 150
 151         for (i = 0; i < bytecount; i++)
 152                 *to8ptr++ = *from8ptr++;
 153
 154         *to32ptr++ = alignbuffer;
 155 }
 156
 157 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
 158 static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
 159                         bool set, unsigned int timeout)
 160 {
 161         u32 val;
 162         unsigned long start = get_timer(0);
 163
 164         while (1) {
 165                 val = readl(reg);
 166
 167                 if (!set)
 168                         val = ~val;
 169
 170                 if ((val & mask) == mask)
 171                         return 0;
 172
 173                 if (get_timer(start) > timeout)
 174                         break;
 175
 176                 if (ctrlc()) {
 177                         puts("Abort\n");
 178                         return -EINTR;
 179                 }
 180
 181                 udelay(1);
 182         }
 183
 184         debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
 185               func, reg, mask, set);
 186
 187         return -ETIMEDOUT;
 188 }
 189
 190 static int mdio_wait(struct emaclite_regs *regs)
 191 {
 192         return wait_for_bit(__func__, &regs->mdioctrl,
 193                             XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
 194 }
 195
 196 static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
 197                    u16 *data)
 198 {
 199         struct emaclite_regs *regs = emaclite->regs;
 200
 201         if (mdio_wait(regs))
 202                 return 1;
 203
 204         u32 ctrl_reg = in_be32(&regs->mdioctrl);
 205         out_be32(&regs->mdioaddr, XEL_MDIOADDR_OP_MASK |
 206                  ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
 207         out_be32(&regs->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
 208
 209         if (mdio_wait(regs))
 210                 return 1;
 211
 212         /* Read data */
 213         *data = in_be32(&regs->mdiord);
 214         return 0;
 215 }
 216
 217 static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
 218                     u16 data)
 219 {
 220         struct emaclite_regs *regs = emaclite->regs;
 221
 222         if (mdio_wait(regs))
 223                 return 1;
 224
 225         /*
 226          * Write the PHY address, register number and clear the OP bit in the
 227          * MDIO Address register and then write the value into the MDIO Write
 228          * Data register. Finally, set the Status bit in the MDIO Control
 229          * register to start a MDIO write transaction.
 230          */
 231         u32 ctrl_reg = in_be32(&regs->mdioctrl);
 232         out_be32(&regs->mdioaddr, ~XEL_MDIOADDR_OP_MASK &
 233                  ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
 234         out_be32(&regs->mdiowr, data);
 235         out_be32(&regs->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
 236
 237         if (mdio_wait(regs))
 238                 return 1;
 239
 240         return 0;
 241 }
 242 #endif
 243
 244 static void emaclite_halt(struct eth_device *dev)
 245 {
 246         debug("eth_halt\n");
 247 }
 248
 249 /* Use MII register 1 (MII status register) to detect PHY */
 250 #define PHY_DETECT_REG  1
 251
 252 /* Mask used to verify certain PHY features (or register contents)
 253  * in the register above:
 254  *  0x1000: 10Mbps full duplex support
 255  *  0x0800: 10Mbps half duplex support
 256  *  0x0008: Auto-negotiation support
 257  */
 258 #define PHY_DETECT_MASK 0x1808
 259
 260 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
 261 static int setup_phy(struct eth_device *dev)
 262 {
 263         int i;
 264         u16 phyreg;
 265         struct xemaclite *emaclite = dev->priv;
 266         struct phy_device *phydev;
 267
 268         u32 supported = SUPPORTED_10baseT_Half |
 269                         SUPPORTED_10baseT_Full |
 270                         SUPPORTED_100baseT_Half |
 271                         SUPPORTED_100baseT_Full;
 272
 273         if (emaclite->phyaddr != -1) {
 274                 phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
 275                 if ((phyreg != 0xFFFF) &&
 276                     ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
 277                         /* Found a valid PHY address */
 278                         debug("Default phy address %d is valid\n",
 279                               emaclite->phyaddr);
 280                 } else {
 281                         debug("PHY address is not setup correctly %d\n",
 282                               emaclite->phyaddr);
 283                         emaclite->phyaddr = -1;
 284                 }
 285         }
 286
 287         if (emaclite->phyaddr == -1) {
 288                 /* detect the PHY address */
 289                 for (i = 31; i >= 0; i--) {
 290                         phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
 291                         if ((phyreg != 0xFFFF) &&
 292                             ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
 293                                 /* Found a valid PHY address */
 294                                 emaclite->phyaddr = i;
 295                                 debug("emaclite: Found valid phy address, %d\n",
 296                                       i);
 297                                 break;
 298                         }
 299                 }
 300         }
 301
 302         /* interface - look at tsec */
 303         phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
 304                              PHY_INTERFACE_MODE_MII);
 305         /*
 306          * Phy can support 1000baseT but device NOT that's why phydev->supported
 307          * must be setup for 1000baseT. phydev->advertising setups what speeds
 308          * will be used for autonegotiation where 1000baseT must be disabled.
 309          */
 310         phydev->supported = supported | SUPPORTED_1000baseT_Half |
 311                                                 SUPPORTED_1000baseT_Full;
 312         phydev->advertising = supported;
 313         emaclite->phydev = phydev;
 314         phy_config(phydev);
 315         phy_startup(phydev);
 316
 317         if (!phydev->link) {
 318                 printf("%s: No link.\n", phydev->dev->name);
 319                 return 0;
 320         }
 321
 322         /* Do not setup anything */
 323         return 1;
 324 }
 325 #endif
 326
 327 static int emaclite_init(struct eth_device *dev, bd_t *bis)
 328 {
 329         struct xemaclite *emaclite = dev->priv;
 330         struct emaclite_regs *regs = emaclite->regs;
 331
 332         debug("EmacLite Initialization Started\n");
 333
 334 /*
 335  * TX - TX_PING & TX_PONG initialization
 336  */
 337         /* Restart PING TX */
 338         out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
 339         /* Copy MAC address */
 340         xemaclite_alignedwrite(dev->enetaddr, dev->iobase, ENET_ADDR_LENGTH);
 341         /* Set the length */
 342         out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
 343         /* Update the MAC address in the EMAC Lite */
 344         out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
 345         /* Wait for EMAC Lite to finish with the MAC address update */
 346         while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) &
 347                 XEL_TSR_PROG_MAC_ADDR) != 0)
 348                 ;
 349
 350         if (emaclite->txpp) {
 351                 /* The same operation with PONG TX */
 352                 out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
 353                 xemaclite_alignedwrite(dev->enetaddr, dev->iobase +
 354                         XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
 355                 out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
 356                 out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
 357                         XEL_TSR_PROG_MAC_ADDR);
 358                 while ((in_be32 (dev->iobase + XEL_TSR_OFFSET +
 359                         XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0)
 360                         ;
 361         }
 362
 363 /*
 364  * RX - RX_PING & RX_PONG initialization
 365  */
 366         /* Write out the value to flush the RX buffer */
 367         out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
 368
 369         if (emaclite->rxpp)
 370                 out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
 371                         XEL_RSR_RECV_IE_MASK);
 372
 373 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
 374         out_be32(&regs->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);
 375         if (in_be32(&regs->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
 376                 if (!setup_phy(dev))
 377                         return -1;
 378 #endif
 379         debug("EmacLite Initialization complete\n");
 380         return 0;
 381 }
 382
 383 static int xemaclite_txbufferavailable(struct eth_device *dev)
 384 {
 385         u32 reg;
 386         u32 txpingbusy;
 387         u32 txpongbusy;
 388         struct xemaclite *emaclite = dev->priv;
 389
 390         /*
 391          * Read the other buffer register
 392          * and determine if the other buffer is available
 393          */
 394         reg = in_be32 (dev->iobase +
 395                         emaclite->nexttxbuffertouse + 0);
 396         txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
 397                         XEL_TSR_XMIT_BUSY_MASK);
 398
 399         reg = in_be32 (dev->iobase +
 400                         (emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
 401         txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
 402                         XEL_TSR_XMIT_BUSY_MASK);
 403
 404         return !(txpingbusy && txpongbusy);
 405 }
 406
 407 static int emaclite_send(struct eth_device *dev, void *ptr, int len)
 408 {
 409         u32 reg;
 410         u32 baseaddress;
 411         struct xemaclite *emaclite = dev->priv;
 412
 413         u32 maxtry = 1000;
 414
 415         if (len > PKTSIZE)
 416                 len = PKTSIZE;
 417
 418         while (!xemaclite_txbufferavailable(dev) && maxtry) {
 419                 udelay(10);
 420                 maxtry--;
 421         }
 422
 423         if (!maxtry) {
 424                 printf("Error: Timeout waiting for ethernet TX buffer\n");
 425                 /* Restart PING TX */
 426                 out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
 427                 if (emaclite->txpp) {
 428                         out_be32 (dev->iobase + XEL_TSR_OFFSET +
 429                                 XEL_BUFFER_OFFSET, 0);
 430                 }
 431                 return -1;
 432         }
 433
 434         /* Determine the expected TX buffer address */
 435         baseaddress = (dev->iobase + emaclite->nexttxbuffertouse);
 436
 437         /* Determine if the expected buffer address is empty */
 438         reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
 439         if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
 440                 && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
 441                         & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
 442
 443                 if (emaclite->txpp)
 444                         emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
 445
 446                 debug("Send packet from 0x%x\n", baseaddress);
 447                 /* Write the frame to the buffer */
 448                 xemaclite_alignedwrite(ptr, baseaddress, len);
 449                 out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
 450                         (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
 451                 reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
 452                 reg |= XEL_TSR_XMIT_BUSY_MASK;
 453                 if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
 454                         reg |= XEL_TSR_XMIT_ACTIVE_MASK;
 455                 out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
 456                 return 0;
 457         }
 458
 459         if (emaclite->txpp) {
 460                 /* Switch to second buffer */
 461                 baseaddress ^= XEL_BUFFER_OFFSET;
 462                 /* Determine if the expected buffer address is empty */
 463                 reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
 464                 if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
 465                         && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
 466                                 & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
 467                         debug("Send packet from 0x%x\n", baseaddress);
 468                         /* Write the frame to the buffer */
 469                         xemaclite_alignedwrite(ptr, baseaddress, len);
 470                         out_be32 (baseaddress + XEL_TPLR_OFFSET, (len &
 471                                 (XEL_TPLR_LENGTH_MASK_HI |
 472                                         XEL_TPLR_LENGTH_MASK_LO)));
 473                         reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
 474                         reg |= XEL_TSR_XMIT_BUSY_MASK;
 475                         if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
 476                                 reg |= XEL_TSR_XMIT_ACTIVE_MASK;
 477                         out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
 478                         return 0;
 479                 }
 480         }
 481
 482         puts("Error while sending frame\n");
 483         return -1;
 484 }
 485
 486 static int emaclite_recv(struct eth_device *dev)
 487 {
 488         u32 length;
 489         u32 reg;
 490         u32 baseaddress;
 491         struct xemaclite *emaclite = dev->priv;
 492
 493         baseaddress = dev->iobase + emaclite->nextrxbuffertouse;
 494         reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
 495         debug("Testing data at address 0x%x\n", baseaddress);
 496         if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
 497                 if (emaclite->rxpp)
 498                         emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
 499         } else {
 500
 501                 if (!emaclite->rxpp) {
 502                         debug("No data was available - address 0x%x\n",
 503                                                                 baseaddress);
 504                         return 0;
 505                 } else {
 506                         baseaddress ^= XEL_BUFFER_OFFSET;
 507                         reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
 508                         if ((reg & XEL_RSR_RECV_DONE_MASK) !=
 509                                                 XEL_RSR_RECV_DONE_MASK) {
 510                                 debug("No data was available - address 0x%x\n",
 511                                                 baseaddress);
 512                                 return 0;
 513                         }
 514                 }
 515         }
 516         /* Get the length of the frame that arrived */
 517         switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
 518                         0xFFFF0000 ) >> 16) {
 519                 case 0x806:
 520                         length = 42 + 20; /* FIXME size of ARP */
 521                         debug("ARP Packet\n");
 522                         break;
 523                 case 0x800:
 524                         length = 14 + 14 +
 525                         (((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET +
 526                                                 0x10))) & 0xFFFF0000) >> 16);
 527                         /* FIXME size of IP packet */
 528                         debug ("IP Packet\n");
 529                         break;
 530                 default:
 531                         debug("Other Packet\n");
 532                         length = PKTSIZE;
 533                         break;
 534         }
 535
 536         xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
 537                         etherrxbuff, length);
 538
 539         /* Acknowledge the frame */
 540         reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
 541         reg &= ~XEL_RSR_RECV_DONE_MASK;
 542         out_be32 (baseaddress + XEL_RSR_OFFSET, reg);
 543
 544         debug("Packet receive from 0x%x, length %dB\n", baseaddress, length);
 545         net_process_received_packet((uchar *)etherrxbuff, length);
 546         return length;
 547
 548 }
 549
 550 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
 551 static int emaclite_miiphy_read(const char *devname, uchar addr,
 552                                 uchar reg, ushort *val)
 553 {
 554         u32 ret;
 555         struct eth_device *dev = eth_get_dev();
 556
 557         ret = phyread(dev->priv, addr, reg, val);
 558         debug("emaclite: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val);
 559         return ret;
 560 }
 561
 562 static int emaclite_miiphy_write(const char *devname, uchar addr,
 563                                  uchar reg, ushort val)
 564 {
 565         struct eth_device *dev = eth_get_dev();
 566
 567         debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val);
 568         return phywrite(dev->priv, addr, reg, val);
 569 }
 570 #endif
 571
 572 int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
 573                                                         int txpp, int rxpp)
 574 {
 575         struct eth_device *dev;
 576         struct xemaclite *emaclite;
 577         struct emaclite_regs *regs;
 578
 579         dev = calloc(1, sizeof(*dev));
 580         if (dev == NULL)
 581                 return -1;
 582
 583         emaclite = calloc(1, sizeof(struct xemaclite));
 584         if (emaclite == NULL) {
 585                 free(dev);
 586                 return -1;
 587         }
 588
 589         dev->priv = emaclite;
 590
 591         emaclite->txpp = txpp;
 592         emaclite->rxpp = rxpp;
 593
 594         sprintf(dev->name, "Xelite.%lx", base_addr);
 595
 596         emaclite->regs = (struct emaclite_regs *)base_addr;
 597         regs = emaclite->regs;
 598         dev->iobase = base_addr;
 599         dev->init = emaclite_init;
 600         dev->halt = emaclite_halt;
 601         dev->send = emaclite_send;
 602         dev->recv = emaclite_recv;
 603
 604 #ifdef CONFIG_PHY_ADDR
 605         emaclite->phyaddr = CONFIG_PHY_ADDR;
 606 #else
 607         emaclite->phyaddr = -1;
 608 #endif
 609
 610         eth_register(dev);
 611
 612 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
 613         miiphy_register(dev->name, emaclite_miiphy_read, emaclite_miiphy_write);
 614         emaclite->bus = miiphy_get_dev_by_name(dev->name);
 615
 616         out_be32(&regs->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);
 617 #endif
 618
 619         return 1;
 620 }