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git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/net/xilinx_emaclite.c
2 * (C) Copyright 2007-2009 Michal Simek
3 * (C) Copyright 2003 Xilinx Inc.
5 * Michal SIMEK <monstr@monstr.eu>
7 * SPDX-License-Identifier: GPL-2.0+
17 DECLARE_GLOBAL_DATA_PTR
;
21 #define ENET_ADDR_LENGTH 6
23 /* EmacLite constants */
24 #define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */
25 #define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */
26 #define XEL_TSR_OFFSET 0x07FC /* Tx status */
27 #define XEL_RSR_OFFSET 0x17FC /* Rx status */
28 #define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
31 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
32 /* Xmit interrupt enable bit */
33 #define XEL_TSR_XMIT_IE_MASK 0x00000008UL
34 /* Buffer is active, SW bit only */
35 #define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL
36 /* Program the MAC address */
37 #define XEL_TSR_PROGRAM_MASK 0x00000002UL
38 /* define for programming the MAC address into the EMAC Lite */
39 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
41 /* Transmit packet length upper byte */
42 #define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
43 /* Transmit packet length lower byte */
44 #define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
47 #define XEL_RSR_RECV_DONE_MASK 0x00000001UL
48 /* Recv interrupt enable bit */
49 #define XEL_RSR_RECV_IE_MASK 0x00000008UL
52 u32 nexttxbuffertouse
; /* Next TX buffer to write to */
53 u32 nextrxbuffertouse
; /* Next RX buffer to read from */
54 u32 txpp
; /* TX ping pong buffer */
55 u32 rxpp
; /* RX ping pong buffer */
58 static u32 etherrxbuff
[PKTSIZE_ALIGN
/4]; /* Receive buffer */
60 static void xemaclite_alignedread(u32
*srcptr
, void *destptr
, u32 bytecount
)
69 from32ptr
= (u32
*) srcptr
;
71 /* Word aligned buffer, no correction needed. */
72 to32ptr
= (u32
*) destptr
;
73 while (bytecount
> 3) {
74 *to32ptr
++ = *from32ptr
++;
77 to8ptr
= (u8
*) to32ptr
;
79 alignbuffer
= *from32ptr
++;
80 from8ptr
= (u8
*) &alignbuffer
;
82 for (i
= 0; i
< bytecount
; i
++)
83 *to8ptr
++ = *from8ptr
++;
86 static void xemaclite_alignedwrite(void *srcptr
, u32 destptr
, u32 bytecount
)
90 u32
*to32ptr
= (u32
*) destptr
;
95 from32ptr
= (u32
*) srcptr
;
96 while (bytecount
> 3) {
98 *to32ptr
++ = *from32ptr
++;
103 to8ptr
= (u8
*) &alignbuffer
;
104 from8ptr
= (u8
*) from32ptr
;
106 for (i
= 0; i
< bytecount
; i
++)
107 *to8ptr
++ = *from8ptr
++;
109 *to32ptr
++ = alignbuffer
;
112 static void emaclite_halt(struct eth_device
*dev
)
117 static int emaclite_init(struct eth_device
*dev
, bd_t
*bis
)
119 struct xemaclite
*emaclite
= dev
->priv
;
120 debug("EmacLite Initialization Started\n");
123 * TX - TX_PING & TX_PONG initialization
125 /* Restart PING TX */
126 out_be32 (dev
->iobase
+ XEL_TSR_OFFSET
, 0);
127 /* Copy MAC address */
128 xemaclite_alignedwrite(dev
->enetaddr
, dev
->iobase
, ENET_ADDR_LENGTH
);
130 out_be32 (dev
->iobase
+ XEL_TPLR_OFFSET
, ENET_ADDR_LENGTH
);
131 /* Update the MAC address in the EMAC Lite */
132 out_be32 (dev
->iobase
+ XEL_TSR_OFFSET
, XEL_TSR_PROG_MAC_ADDR
);
133 /* Wait for EMAC Lite to finish with the MAC address update */
134 while ((in_be32 (dev
->iobase
+ XEL_TSR_OFFSET
) &
135 XEL_TSR_PROG_MAC_ADDR
) != 0)
138 if (emaclite
->txpp
) {
139 /* The same operation with PONG TX */
140 out_be32 (dev
->iobase
+ XEL_TSR_OFFSET
+ XEL_BUFFER_OFFSET
, 0);
141 xemaclite_alignedwrite(dev
->enetaddr
, dev
->iobase
+
142 XEL_BUFFER_OFFSET
, ENET_ADDR_LENGTH
);
143 out_be32 (dev
->iobase
+ XEL_TPLR_OFFSET
, ENET_ADDR_LENGTH
);
144 out_be32 (dev
->iobase
+ XEL_TSR_OFFSET
+ XEL_BUFFER_OFFSET
,
145 XEL_TSR_PROG_MAC_ADDR
);
146 while ((in_be32 (dev
->iobase
+ XEL_TSR_OFFSET
+
147 XEL_BUFFER_OFFSET
) & XEL_TSR_PROG_MAC_ADDR
) != 0)
152 * RX - RX_PING & RX_PONG initialization
154 /* Write out the value to flush the RX buffer */
155 out_be32 (dev
->iobase
+ XEL_RSR_OFFSET
, XEL_RSR_RECV_IE_MASK
);
158 out_be32 (dev
->iobase
+ XEL_RSR_OFFSET
+ XEL_BUFFER_OFFSET
,
159 XEL_RSR_RECV_IE_MASK
);
161 debug("EmacLite Initialization complete\n");
165 static int xemaclite_txbufferavailable(struct eth_device
*dev
)
170 struct xemaclite
*emaclite
= dev
->priv
;
173 * Read the other buffer register
174 * and determine if the other buffer is available
176 reg
= in_be32 (dev
->iobase
+
177 emaclite
->nexttxbuffertouse
+ 0);
178 txpingbusy
= ((reg
& XEL_TSR_XMIT_BUSY_MASK
) ==
179 XEL_TSR_XMIT_BUSY_MASK
);
181 reg
= in_be32 (dev
->iobase
+
182 (emaclite
->nexttxbuffertouse
^ XEL_TSR_OFFSET
) + 0);
183 txpongbusy
= ((reg
& XEL_TSR_XMIT_BUSY_MASK
) ==
184 XEL_TSR_XMIT_BUSY_MASK
);
186 return !(txpingbusy
&& txpongbusy
);
189 static int emaclite_send(struct eth_device
*dev
, void *ptr
, int len
)
193 struct xemaclite
*emaclite
= dev
->priv
;
200 while (!xemaclite_txbufferavailable(dev
) && maxtry
) {
206 printf("Error: Timeout waiting for ethernet TX buffer\n");
207 /* Restart PING TX */
208 out_be32 (dev
->iobase
+ XEL_TSR_OFFSET
, 0);
209 if (emaclite
->txpp
) {
210 out_be32 (dev
->iobase
+ XEL_TSR_OFFSET
+
211 XEL_BUFFER_OFFSET
, 0);
216 /* Determine the expected TX buffer address */
217 baseaddress
= (dev
->iobase
+ emaclite
->nexttxbuffertouse
);
219 /* Determine if the expected buffer address is empty */
220 reg
= in_be32 (baseaddress
+ XEL_TSR_OFFSET
);
221 if (((reg
& XEL_TSR_XMIT_BUSY_MASK
) == 0)
222 && ((in_be32 ((baseaddress
) + XEL_TSR_OFFSET
)
223 & XEL_TSR_XMIT_ACTIVE_MASK
) == 0)) {
226 emaclite
->nexttxbuffertouse
^= XEL_BUFFER_OFFSET
;
228 debug("Send packet from 0x%x\n", baseaddress
);
229 /* Write the frame to the buffer */
230 xemaclite_alignedwrite(ptr
, baseaddress
, len
);
231 out_be32 (baseaddress
+ XEL_TPLR_OFFSET
,(len
&
232 (XEL_TPLR_LENGTH_MASK_HI
| XEL_TPLR_LENGTH_MASK_LO
)));
233 reg
= in_be32 (baseaddress
+ XEL_TSR_OFFSET
);
234 reg
|= XEL_TSR_XMIT_BUSY_MASK
;
235 if ((reg
& XEL_TSR_XMIT_IE_MASK
) != 0)
236 reg
|= XEL_TSR_XMIT_ACTIVE_MASK
;
237 out_be32 (baseaddress
+ XEL_TSR_OFFSET
, reg
);
241 if (emaclite
->txpp
) {
242 /* Switch to second buffer */
243 baseaddress
^= XEL_BUFFER_OFFSET
;
244 /* Determine if the expected buffer address is empty */
245 reg
= in_be32 (baseaddress
+ XEL_TSR_OFFSET
);
246 if (((reg
& XEL_TSR_XMIT_BUSY_MASK
) == 0)
247 && ((in_be32 ((baseaddress
) + XEL_TSR_OFFSET
)
248 & XEL_TSR_XMIT_ACTIVE_MASK
) == 0)) {
249 debug("Send packet from 0x%x\n", baseaddress
);
250 /* Write the frame to the buffer */
251 xemaclite_alignedwrite(ptr
, baseaddress
, len
);
252 out_be32 (baseaddress
+ XEL_TPLR_OFFSET
, (len
&
253 (XEL_TPLR_LENGTH_MASK_HI
|
254 XEL_TPLR_LENGTH_MASK_LO
)));
255 reg
= in_be32 (baseaddress
+ XEL_TSR_OFFSET
);
256 reg
|= XEL_TSR_XMIT_BUSY_MASK
;
257 if ((reg
& XEL_TSR_XMIT_IE_MASK
) != 0)
258 reg
|= XEL_TSR_XMIT_ACTIVE_MASK
;
259 out_be32 (baseaddress
+ XEL_TSR_OFFSET
, reg
);
264 puts("Error while sending frame\n");
268 static int emaclite_recv(struct eth_device
*dev
)
273 struct xemaclite
*emaclite
= dev
->priv
;
275 baseaddress
= dev
->iobase
+ emaclite
->nextrxbuffertouse
;
276 reg
= in_be32 (baseaddress
+ XEL_RSR_OFFSET
);
277 debug("Testing data at address 0x%x\n", baseaddress
);
278 if ((reg
& XEL_RSR_RECV_DONE_MASK
) == XEL_RSR_RECV_DONE_MASK
) {
280 emaclite
->nextrxbuffertouse
^= XEL_BUFFER_OFFSET
;
283 if (!emaclite
->rxpp
) {
284 debug("No data was available - address 0x%x\n",
288 baseaddress
^= XEL_BUFFER_OFFSET
;
289 reg
= in_be32 (baseaddress
+ XEL_RSR_OFFSET
);
290 if ((reg
& XEL_RSR_RECV_DONE_MASK
) !=
291 XEL_RSR_RECV_DONE_MASK
) {
292 debug("No data was available - address 0x%x\n",
298 /* Get the length of the frame that arrived */
299 switch(((ntohl(in_be32 (baseaddress
+ XEL_RXBUFF_OFFSET
+ 0xC))) &
300 0xFFFF0000 ) >> 16) {
302 length
= 42 + 20; /* FIXME size of ARP */
303 debug("ARP Packet\n");
307 (((ntohl(in_be32 (baseaddress
+ XEL_RXBUFF_OFFSET
+
308 0x10))) & 0xFFFF0000) >> 16);
309 /* FIXME size of IP packet */
310 debug ("IP Packet\n");
313 debug("Other Packet\n");
318 xemaclite_alignedread((u32
*) (baseaddress
+ XEL_RXBUFF_OFFSET
),
319 etherrxbuff
, length
);
321 /* Acknowledge the frame */
322 reg
= in_be32 (baseaddress
+ XEL_RSR_OFFSET
);
323 reg
&= ~XEL_RSR_RECV_DONE_MASK
;
324 out_be32 (baseaddress
+ XEL_RSR_OFFSET
, reg
);
326 debug("Packet receive from 0x%x, length %dB\n", baseaddress
, length
);
327 NetReceive((uchar
*) etherrxbuff
, length
);
332 int xilinx_emaclite_initialize(bd_t
*bis
, unsigned long base_addr
,
335 struct eth_device
*dev
;
336 struct xemaclite
*emaclite
;
338 dev
= calloc(1, sizeof(*dev
));
342 emaclite
= calloc(1, sizeof(struct xemaclite
));
343 if (emaclite
== NULL
) {
348 dev
->priv
= emaclite
;
350 emaclite
->txpp
= txpp
;
351 emaclite
->rxpp
= rxpp
;
353 sprintf(dev
->name
, "Xelite.%lx", base_addr
);
355 dev
->iobase
= base_addr
;
356 dev
->init
= emaclite_init
;
357 dev
->halt
= emaclite_halt
;
358 dev
->send
= emaclite_send
;
359 dev
->recv
= emaclite_recv
;
366 #ifdef CONFIG_OF_CONTROL
367 int xilinx_emaclite_init(bd_t
*bis
)
374 offset
= fdt_node_offset_by_compatible(gd
->fdt_blob
, offset
,
375 "xlnx,xps-ethernetlite-1.00.a");
377 reg
= fdtdec_get_addr(gd
->fdt_blob
, offset
, "reg");
378 if (reg
!= FDT_ADDR_T_NONE
) {
379 u32 rxpp
= fdtdec_get_int(gd
->fdt_blob
, offset
,
380 "xlnx,rx-ping-pong", 0);
381 u32 txpp
= fdtdec_get_int(gd
->fdt_blob
, offset
,
382 "xlnx,tx-ping-pong", 0);
383 ret
|= xilinx_emaclite_initialize(bis
, reg
,
387 } while (offset
!= -1);