drivers/net/xilinx_emaclite.c

   1 /*
   2  * (C) Copyright 2007-2009 Michal Simek
   3  * (C) Copyright 2003 Xilinx Inc.
   4  *
   5  * Michal SIMEK <monstr@monstr.eu>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <net.h>
  28 #include <config.h>
  29 #include <malloc.h>
  30 #include <asm/io.h>
  31 #include <fdtdec.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #undef DEBUG
  36
  37 #define ENET_ADDR_LENGTH        6
  38
  39 /* EmacLite constants */
  40 #define XEL_BUFFER_OFFSET       0x0800  /* Next buffer's offset */
  41 #define XEL_TPLR_OFFSET         0x07F4  /* Tx packet length */
  42 #define XEL_TSR_OFFSET          0x07FC  /* Tx status */
  43 #define XEL_RSR_OFFSET          0x17FC  /* Rx status */
  44 #define XEL_RXBUFF_OFFSET       0x1000  /* Receive Buffer */
  45
  46 /* Xmit complete */
  47 #define XEL_TSR_XMIT_BUSY_MASK          0x00000001UL
  48 /* Xmit interrupt enable bit */
  49 #define XEL_TSR_XMIT_IE_MASK            0x00000008UL
  50 /* Buffer is active, SW bit only */
  51 #define XEL_TSR_XMIT_ACTIVE_MASK        0x80000000UL
  52 /* Program the MAC address */
  53 #define XEL_TSR_PROGRAM_MASK            0x00000002UL
  54 /* define for programming the MAC address into the EMAC Lite */
  55 #define XEL_TSR_PROG_MAC_ADDR   (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
  56
  57 /* Transmit packet length upper byte */
  58 #define XEL_TPLR_LENGTH_MASK_HI         0x0000FF00UL
  59 /* Transmit packet length lower byte */
  60 #define XEL_TPLR_LENGTH_MASK_LO         0x000000FFUL
  61
  62 /* Recv complete */
  63 #define XEL_RSR_RECV_DONE_MASK          0x00000001UL
  64 /* Recv interrupt enable bit */
  65 #define XEL_RSR_RECV_IE_MASK            0x00000008UL
  66
  67 struct xemaclite {
  68         u32 nexttxbuffertouse;  /* Next TX buffer to write to */
  69         u32 nextrxbuffertouse;  /* Next RX buffer to read from */
  70         u32 txpp;               /* TX ping pong buffer */
  71         u32 rxpp;               /* RX ping pong buffer */
  72 };
  73
  74 static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
  75
  76 static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
  77 {
  78         u32 i;
  79         u32 alignbuffer;
  80         u32 *to32ptr;
  81         u32 *from32ptr;
  82         u8 *to8ptr;
  83         u8 *from8ptr;
  84
  85         from32ptr = (u32 *) srcptr;
  86
  87         /* Word aligned buffer, no correction needed. */
  88         to32ptr = (u32 *) destptr;
  89         while (bytecount > 3) {
  90                 *to32ptr++ = *from32ptr++;
  91                 bytecount -= 4;
  92         }
  93         to8ptr = (u8 *) to32ptr;
  94
  95         alignbuffer = *from32ptr++;
  96         from8ptr = (u8 *) &alignbuffer;
  97
  98         for (i = 0; i < bytecount; i++)
  99                 *to8ptr++ = *from8ptr++;
 100 }
 101
 102 static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount)
 103 {
 104         u32 i;
 105         u32 alignbuffer;
 106         u32 *to32ptr = (u32 *) destptr;
 107         u32 *from32ptr;
 108         u8 *to8ptr;
 109         u8 *from8ptr;
 110
 111         from32ptr = (u32 *) srcptr;
 112         while (bytecount > 3) {
 113
 114                 *to32ptr++ = *from32ptr++;
 115                 bytecount -= 4;
 116         }
 117
 118         alignbuffer = 0;
 119         to8ptr = (u8 *) &alignbuffer;
 120         from8ptr = (u8 *) from32ptr;
 121
 122         for (i = 0; i < bytecount; i++)
 123                 *to8ptr++ = *from8ptr++;
 124
 125         *to32ptr++ = alignbuffer;
 126 }
 127
 128 static void emaclite_halt(struct eth_device *dev)
 129 {
 130         debug("eth_halt\n");
 131 }
 132
 133 static int emaclite_init(struct eth_device *dev, bd_t *bis)
 134 {
 135         struct xemaclite *emaclite = dev->priv;
 136         debug("EmacLite Initialization Started\n");
 137
 138 /*
 139  * TX - TX_PING & TX_PONG initialization
 140  */
 141         /* Restart PING TX */
 142         out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
 143         /* Copy MAC address */
 144         xemaclite_alignedwrite(dev->enetaddr, dev->iobase, ENET_ADDR_LENGTH);
 145         /* Set the length */
 146         out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
 147         /* Update the MAC address in the EMAC Lite */
 148         out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
 149         /* Wait for EMAC Lite to finish with the MAC address update */
 150         while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) &
 151                 XEL_TSR_PROG_MAC_ADDR) != 0)
 152                 ;
 153
 154         if (emaclite->txpp) {
 155                 /* The same operation with PONG TX */
 156                 out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
 157                 xemaclite_alignedwrite(dev->enetaddr, dev->iobase +
 158                         XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
 159                 out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
 160                 out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
 161                         XEL_TSR_PROG_MAC_ADDR);
 162                 while ((in_be32 (dev->iobase + XEL_TSR_OFFSET +
 163                         XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0)
 164                         ;
 165         }
 166
 167 /*
 168  * RX - RX_PING & RX_PONG initialization
 169  */
 170         /* Write out the value to flush the RX buffer */
 171         out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
 172
 173         if (emaclite->rxpp)
 174                 out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
 175                         XEL_RSR_RECV_IE_MASK);
 176
 177         debug("EmacLite Initialization complete\n");
 178         return 0;
 179 }
 180
 181 static int xemaclite_txbufferavailable(struct eth_device *dev)
 182 {
 183         u32 reg;
 184         u32 txpingbusy;
 185         u32 txpongbusy;
 186         struct xemaclite *emaclite = dev->priv;
 187
 188         /*
 189          * Read the other buffer register
 190          * and determine if the other buffer is available
 191          */
 192         reg = in_be32 (dev->iobase +
 193                         emaclite->nexttxbuffertouse + 0);
 194         txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
 195                         XEL_TSR_XMIT_BUSY_MASK);
 196
 197         reg = in_be32 (dev->iobase +
 198                         (emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
 199         txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
 200                         XEL_TSR_XMIT_BUSY_MASK);
 201
 202         return !(txpingbusy && txpongbusy);
 203 }
 204
 205 static int emaclite_send(struct eth_device *dev, void *ptr, int len)
 206 {
 207         u32 reg;
 208         u32 baseaddress;
 209         struct xemaclite *emaclite = dev->priv;
 210
 211         u32 maxtry = 1000;
 212
 213         if (len > PKTSIZE)
 214                 len = PKTSIZE;
 215
 216         while (!xemaclite_txbufferavailable(dev) && maxtry) {
 217                 udelay(10);
 218                 maxtry--;
 219         }
 220
 221         if (!maxtry) {
 222                 printf("Error: Timeout waiting for ethernet TX buffer\n");
 223                 /* Restart PING TX */
 224                 out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
 225                 if (emaclite->txpp) {
 226                         out_be32 (dev->iobase + XEL_TSR_OFFSET +
 227                                 XEL_BUFFER_OFFSET, 0);
 228                 }
 229                 return -1;
 230         }
 231
 232         /* Determine the expected TX buffer address */
 233         baseaddress = (dev->iobase + emaclite->nexttxbuffertouse);
 234
 235         /* Determine if the expected buffer address is empty */
 236         reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
 237         if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
 238                 && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
 239                         & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
 240
 241                 if (emaclite->txpp)
 242                         emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
 243
 244                 debug("Send packet from 0x%x\n", baseaddress);
 245                 /* Write the frame to the buffer */
 246                 xemaclite_alignedwrite(ptr, baseaddress, len);
 247                 out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
 248                         (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
 249                 reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
 250                 reg |= XEL_TSR_XMIT_BUSY_MASK;
 251                 if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
 252                         reg |= XEL_TSR_XMIT_ACTIVE_MASK;
 253                 out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
 254                 return 0;
 255         }
 256
 257         if (emaclite->txpp) {
 258                 /* Switch to second buffer */
 259                 baseaddress ^= XEL_BUFFER_OFFSET;
 260                 /* Determine if the expected buffer address is empty */
 261                 reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
 262                 if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
 263                         && ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
 264                                 & XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
 265                         debug("Send packet from 0x%x\n", baseaddress);
 266                         /* Write the frame to the buffer */
 267                         xemaclite_alignedwrite(ptr, baseaddress, len);
 268                         out_be32 (baseaddress + XEL_TPLR_OFFSET, (len &
 269                                 (XEL_TPLR_LENGTH_MASK_HI |
 270                                         XEL_TPLR_LENGTH_MASK_LO)));
 271                         reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
 272                         reg |= XEL_TSR_XMIT_BUSY_MASK;
 273                         if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
 274                                 reg |= XEL_TSR_XMIT_ACTIVE_MASK;
 275                         out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
 276                         return 0;
 277                 }
 278         }
 279
 280         puts("Error while sending frame\n");
 281         return -1;
 282 }
 283
 284 static int emaclite_recv(struct eth_device *dev)
 285 {
 286         u32 length;
 287         u32 reg;
 288         u32 baseaddress;
 289         struct xemaclite *emaclite = dev->priv;
 290
 291         baseaddress = dev->iobase + emaclite->nextrxbuffertouse;
 292         reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
 293         debug("Testing data at address 0x%x\n", baseaddress);
 294         if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
 295                 if (emaclite->rxpp)
 296                         emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
 297         } else {
 298
 299                 if (!emaclite->rxpp) {
 300                         debug("No data was available - address 0x%x\n",
 301                                                                 baseaddress);
 302                         return 0;
 303                 } else {
 304                         baseaddress ^= XEL_BUFFER_OFFSET;
 305                         reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
 306                         if ((reg & XEL_RSR_RECV_DONE_MASK) !=
 307                                                 XEL_RSR_RECV_DONE_MASK) {
 308                                 debug("No data was available - address 0x%x\n",
 309                                                 baseaddress);
 310                                 return 0;
 311                         }
 312                 }
 313         }
 314         /* Get the length of the frame that arrived */
 315         switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
 316                         0xFFFF0000 ) >> 16) {
 317                 case 0x806:
 318                         length = 42 + 20; /* FIXME size of ARP */
 319                         debug("ARP Packet\n");
 320                         break;
 321                 case 0x800:
 322                         length = 14 + 14 +
 323                         (((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET +
 324                                                 0x10))) & 0xFFFF0000) >> 16);
 325                         /* FIXME size of IP packet */
 326                         debug ("IP Packet\n");
 327                         break;
 328                 default:
 329                         debug("Other Packet\n");
 330                         length = PKTSIZE;
 331                         break;
 332         }
 333
 334         xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
 335                         etherrxbuff, length);
 336
 337         /* Acknowledge the frame */
 338         reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
 339         reg &= ~XEL_RSR_RECV_DONE_MASK;
 340         out_be32 (baseaddress + XEL_RSR_OFFSET, reg);
 341
 342         debug("Packet receive from 0x%x, length %dB\n", baseaddress, length);
 343         NetReceive((uchar *) etherrxbuff, length);
 344         return length;
 345
 346 }
 347
 348 int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
 349                                                         int txpp, int rxpp)
 350 {
 351         struct eth_device *dev;
 352         struct xemaclite *emaclite;
 353
 354         dev = calloc(1, sizeof(*dev));
 355         if (dev == NULL)
 356                 return -1;
 357
 358         emaclite = calloc(1, sizeof(struct xemaclite));
 359         if (emaclite == NULL) {
 360                 free(dev);
 361                 return -1;
 362         }
 363
 364         dev->priv = emaclite;
 365
 366         emaclite->txpp = txpp;
 367         emaclite->rxpp = rxpp;
 368
 369         sprintf(dev->name, "Xelite.%lx", base_addr);
 370
 371         dev->iobase = base_addr;
 372         dev->init = emaclite_init;
 373         dev->halt = emaclite_halt;
 374         dev->send = emaclite_send;
 375         dev->recv = emaclite_recv;
 376
 377         eth_register(dev);
 378
 379         return 1;
 380 }
 381
 382 #ifdef CONFIG_OF_CONTROL
 383 int xilinx_emaclite_init(bd_t *bis)
 384 {
 385         int offset = 0;
 386         u32 ret = 0;
 387         u32 reg;
 388
 389         do {
 390                 offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
 391                                         "xlnx,xps-ethernetlite-1.00.a");
 392                 if (offset != -1) {
 393                         reg = fdtdec_get_addr(gd->fdt_blob, offset, "reg");
 394                         if (reg != FDT_ADDR_T_NONE) {
 395                                 u32 rxpp = fdtdec_get_int(gd->fdt_blob, offset,
 396                                                         "xlnx,rx-ping-pong", 0);
 397                                 u32 txpp = fdtdec_get_int(gd->fdt_blob, offset,
 398                                                         "xlnx,tx-ping-pong", 0);
 399                                 ret |= xilinx_emaclite_initialize(bis, reg,
 400                                                                 txpp, rxpp);
 401                         }
 402                 }
 403         } while (offset != -1);
 404
 405         return ret;
 406 }
 407 #endif