drivers/pci/pci_auto.c

   1 /*
   2  * arch/powerpc/kernel/pci_auto.c
   3  *
   4  * PCI autoconfiguration library
   5  *
   6  * Author: Matt Porter <mporter@mvista.com>
   7  *
   8  * Copyright 2000 MontaVista Software Inc.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14
  15 #include <pci.h>
  16
  17 #undef DEBUG
  18 #ifdef DEBUG
  19 #define DEBUGF(x...) printf(x)
  20 #else
  21 #define DEBUGF(x...)
  22 #endif /* DEBUG */
  23
  24 #define PCIAUTO_IDE_MODE_MASK           0x05
  25
  26 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
  27 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
  28 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  8
  29 #endif
  30
  31 /*
  32  *
  33  */
  34
  35 void pciauto_region_init(struct pci_region *res)
  36 {
  37         /*
  38          * Avoid allocating PCI resources from address 0 -- this is illegal
  39          * according to PCI 2.1 and moreover, this is known to cause Linux IDE
  40          * drivers to fail. Use a reasonable starting value of 0x1000 instead.
  41          */
  42         res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
  43 }
  44
  45 void pciauto_region_align(struct pci_region *res, pci_size_t size)
  46 {
  47         res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
  48 }
  49
  50 int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
  51         pci_addr_t *bar)
  52 {
  53         pci_addr_t addr;
  54
  55         if (!res) {
  56                 DEBUGF("No resource");
  57                 goto error;
  58         }
  59
  60         addr = ((res->bus_lower - 1) | (size - 1)) + 1;
  61
  62         if (addr - res->bus_start + size > res->size) {
  63                 DEBUGF("No room in resource");
  64                 goto error;
  65         }
  66
  67         res->bus_lower = addr + size;
  68
  69         DEBUGF("address=0x%llx bus_lower=0x%llx", (u64)addr, (u64)res->bus_lower);
  70
  71         *bar = addr;
  72         return 0;
  73
  74  error:
  75         *bar = (pci_addr_t)-1;
  76         return -1;
  77 }
  78
  79 /*
  80  *
  81  */
  82
  83 void pciauto_setup_device(struct pci_controller *hose,
  84                           pci_dev_t dev, int bars_num,
  85                           struct pci_region *mem,
  86                           struct pci_region *prefetch,
  87                           struct pci_region *io)
  88 {
  89         u32 bar_response;
  90         pci_size_t bar_size;
  91         u16 cmdstat = 0;
  92         int bar, bar_nr = 0;
  93 #ifndef CONFIG_PCI_ENUM_ONLY
  94         pci_addr_t bar_value;
  95         struct pci_region *bar_res;
  96         int found_mem64 = 0;
  97 #endif
  98
  99         pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
 100         cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
 101
 102         for (bar = PCI_BASE_ADDRESS_0;
 103                 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
 104                 /* Tickle the BAR and get the response */
 105 #ifndef CONFIG_PCI_ENUM_ONLY
 106                 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
 107 #endif
 108                 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
 109
 110                 /* If BAR is not implemented go to the next BAR */
 111                 if (!bar_response)
 112                         continue;
 113
 114 #ifndef CONFIG_PCI_ENUM_ONLY
 115                 found_mem64 = 0;
 116 #endif
 117
 118                 /* Check the BAR type and set our address mask */
 119                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 120                         bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
 121                                    & 0xffff) + 1;
 122 #ifndef CONFIG_PCI_ENUM_ONLY
 123                         bar_res = io;
 124 #endif
 125
 126                         DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", bar_nr, (u64)bar_size);
 127                 } else {
 128                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 129                              PCI_BASE_ADDRESS_MEM_TYPE_64) {
 130                                 u32 bar_response_upper;
 131                                 u64 bar64;
 132
 133 #ifndef CONFIG_PCI_ENUM_ONLY
 134                                 pci_hose_write_config_dword(hose, dev, bar + 4,
 135                                         0xffffffff);
 136 #endif
 137                                 pci_hose_read_config_dword(hose, dev, bar + 4,
 138                                         &bar_response_upper);
 139
 140                                 bar64 = ((u64)bar_response_upper << 32) | bar_response;
 141
 142                                 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
 143 #ifndef CONFIG_PCI_ENUM_ONLY
 144                                 found_mem64 = 1;
 145 #endif
 146                         } else {
 147                                 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
 148                         }
 149 #ifndef CONFIG_PCI_ENUM_ONLY
 150                         if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
 151                                 bar_res = prefetch;
 152                         else
 153                                 bar_res = mem;
 154 #endif
 155
 156                         DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ", bar_nr, (u64)bar_size);
 157                 }
 158
 159 #ifndef CONFIG_PCI_ENUM_ONLY
 160                 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
 161                         /* Write it out and update our limit */
 162                         pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
 163
 164                         if (found_mem64) {
 165                                 bar += 4;
 166 #ifdef CONFIG_SYS_PCI_64BIT
 167                                 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
 168 #else
 169                                 /*
 170                                  * If we are a 64-bit decoder then increment to the
 171                                  * upper 32 bits of the bar and force it to locate
 172                                  * in the lower 4GB of memory.
 173                                  */
 174                                 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
 175 #endif
 176                         }
 177
 178                 }
 179 #endif
 180                 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
 181                         PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
 182
 183                 DEBUGF("\n");
 184
 185                 bar_nr++;
 186         }
 187
 188         pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
 189         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
 190                 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
 191         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 192 }
 193
 194 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
 195                                          pci_dev_t dev, int sub_bus)
 196 {
 197         struct pci_region *pci_mem = hose->pci_mem;
 198         struct pci_region *pci_prefetch = hose->pci_prefetch;
 199         struct pci_region *pci_io = hose->pci_io;
 200         u16 cmdstat;
 201
 202         pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
 203
 204         /* Configure bus number registers */
 205         pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
 206                                    PCI_BUS(dev) - hose->first_busno);
 207         pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
 208                                    sub_bus - hose->first_busno);
 209         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
 210
 211         if (pci_mem) {
 212                 /* Round memory allocator to 1MB boundary */
 213                 pciauto_region_align(pci_mem, 0x100000);
 214
 215                 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 216                 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
 217                                         (pci_mem->bus_lower & 0xfff00000) >> 16);
 218
 219                 cmdstat |= PCI_COMMAND_MEMORY;
 220         }
 221
 222         if (pci_prefetch) {
 223                 /* Round memory allocator to 1MB boundary */
 224                 pciauto_region_align(pci_prefetch, 0x100000);
 225
 226                 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 227                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
 228                                         (pci_prefetch->bus_lower & 0xfff00000) >> 16);
 229
 230                 cmdstat |= PCI_COMMAND_MEMORY;
 231         } else {
 232                 /* We don't support prefetchable memory for now, so disable */
 233                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
 234                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
 235         }
 236
 237         if (pci_io) {
 238                 /* Round I/O allocator to 4KB boundary */
 239                 pciauto_region_align(pci_io, 0x1000);
 240
 241                 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
 242                                         (pci_io->bus_lower & 0x0000f000) >> 8);
 243                 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
 244                                         (pci_io->bus_lower & 0xffff0000) >> 16);
 245
 246                 cmdstat |= PCI_COMMAND_IO;
 247         }
 248
 249         /* Enable memory and I/O accesses, enable bus master */
 250         pci_hose_write_config_word(hose, dev, PCI_COMMAND,
 251                                         cmdstat | PCI_COMMAND_MASTER);
 252 }
 253
 254 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
 255                                           pci_dev_t dev, int sub_bus)
 256 {
 257         struct pci_region *pci_mem = hose->pci_mem;
 258         struct pci_region *pci_prefetch = hose->pci_prefetch;
 259         struct pci_region *pci_io = hose->pci_io;
 260
 261         /* Configure bus number registers */
 262         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
 263                                    sub_bus - hose->first_busno);
 264
 265         if (pci_mem) {
 266                 /* Round memory allocator to 1MB boundary */
 267                 pciauto_region_align(pci_mem, 0x100000);
 268
 269                 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
 270                                 (pci_mem->bus_lower - 1) >> 16);
 271         }
 272
 273         if (pci_prefetch) {
 274                 /* Round memory allocator to 1MB boundary */
 275                 pciauto_region_align(pci_prefetch, 0x100000);
 276
 277                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
 278                                 (pci_prefetch->bus_lower - 1) >> 16);
 279         }
 280
 281         if (pci_io) {
 282                 /* Round I/O allocator to 4KB boundary */
 283                 pciauto_region_align(pci_io, 0x1000);
 284
 285                 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
 286                                 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
 287                 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
 288                                 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
 289         }
 290 }
 291
 292 /*
 293  *
 294  */
 295
 296 void pciauto_config_init(struct pci_controller *hose)
 297 {
 298         int i;
 299
 300         hose->pci_io = hose->pci_mem = NULL;
 301
 302         for (i = 0; i < hose->region_count; i++) {
 303                 switch(hose->regions[i].flags) {
 304                 case PCI_REGION_IO:
 305                         if (!hose->pci_io ||
 306                             hose->pci_io->size < hose->regions[i].size)
 307                                 hose->pci_io = hose->regions + i;
 308                         break;
 309                 case PCI_REGION_MEM:
 310                         if (!hose->pci_mem ||
 311                             hose->pci_mem->size < hose->regions[i].size)
 312                                 hose->pci_mem = hose->regions + i;
 313                         break;
 314                 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
 315                         if (!hose->pci_prefetch ||
 316                             hose->pci_prefetch->size < hose->regions[i].size)
 317                                 hose->pci_prefetch = hose->regions + i;
 318                         break;
 319                 }
 320         }
 321
 322
 323         if (hose->pci_mem) {
 324                 pciauto_region_init(hose->pci_mem);
 325
 326                 DEBUGF("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n"
 327                        "\t\tPhysical Memory [%llx-%llxx]\n",
 328                     (u64)hose->pci_mem->bus_start,
 329                     (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1),
 330                     (u64)hose->pci_mem->phys_start,
 331                     (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1));
 332         }
 333
 334         if (hose->pci_prefetch) {
 335                 pciauto_region_init(hose->pci_prefetch);
 336
 337                 DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n"
 338                        "\t\tPhysical Memory [%llx-%llx]\n",
 339                     (u64)hose->pci_prefetch->bus_start,
 340                     (u64)(hose->pci_prefetch->bus_start +
 341                             hose->pci_prefetch->size - 1),
 342                     (u64)hose->pci_prefetch->phys_start,
 343                     (u64)(hose->pci_prefetch->phys_start +
 344                             hose->pci_prefetch->size - 1));
 345         }
 346
 347         if (hose->pci_io) {
 348                 pciauto_region_init(hose->pci_io);
 349
 350                 DEBUGF("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n"
 351                        "\t\tPhysical Memory: [%llx-%llx]\n",
 352                     (u64)hose->pci_io->bus_start,
 353                     (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1),
 354                     (u64)hose->pci_io->phys_start,
 355                     (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1));
 356
 357         }
 358 }
 359
 360 /*
 361  * HJF: Changed this to return int. I think this is required
 362  * to get the correct result when scanning bridges
 363  */
 364 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
 365 {
 366         unsigned int sub_bus = PCI_BUS(dev);
 367         unsigned short class;
 368         unsigned char prg_iface;
 369         int n;
 370
 371         pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 372
 373         switch (class) {
 374         case PCI_CLASS_BRIDGE_PCI:
 375                 hose->current_busno++;
 376                 pciauto_setup_device(hose, dev, 2, hose->pci_mem,
 377                         hose->pci_prefetch, hose->pci_io);
 378
 379                 DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
 380
 381                 /* Passing in current_busno allows for sibling P2P bridges */
 382                 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
 383                 /*
 384                  * need to figure out if this is a subordinate bridge on the bus
 385                  * to be able to properly set the pri/sec/sub bridge registers.
 386                  */
 387                 n = pci_hose_scan_bus(hose, hose->current_busno);
 388
 389                 /* figure out the deepest we've gone for this leg */
 390                 sub_bus = max(n, sub_bus);
 391                 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
 392
 393                 sub_bus = hose->current_busno;
 394                 break;
 395
 396         case PCI_CLASS_STORAGE_IDE:
 397                 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
 398                 if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
 399                         DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
 400                         return sub_bus;
 401                 }
 402
 403                 pciauto_setup_device(hose, dev, 6, hose->pci_mem,
 404                         hose->pci_prefetch, hose->pci_io);
 405                 break;
 406
 407         case PCI_CLASS_BRIDGE_CARDBUS:
 408                 /*
 409                  * just do a minimal setup of the bridge,
 410                  * let the OS take care of the rest
 411                  */
 412                 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
 413                         hose->pci_prefetch, hose->pci_io);
 414
 415                 DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
 416                         PCI_DEV(dev));
 417
 418                 hose->current_busno++;
 419                 break;
 420
 421 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
 422         case PCI_CLASS_BRIDGE_OTHER:
 423                 DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
 424                        PCI_DEV(dev));
 425                 break;
 426 #endif
 427 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
 428         case PCI_CLASS_BRIDGE_OTHER:
 429                 /*
 430                  * The host/PCI bridge 1 seems broken in 8349 - it presents
 431                  * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
 432                  * device claiming resources io/mem/irq.. we only allow for
 433                  * the PIMMR window to be allocated (BAR0 - 1MB size)
 434                  */
 435                 DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
 436                 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
 437                         hose->pci_prefetch, hose->pci_io);
 438                 break;
 439 #endif
 440
 441         case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
 442                 DEBUGF("PCI AutoConfig: Found PowerPC device\n");
 443
 444         default:
 445                 pciauto_setup_device(hose, dev, 6, hose->pci_mem,
 446                         hose->pci_prefetch, hose->pci_io);
 447                 break;
 448         }
 449
 450         return sub_bus;
 451 }