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dm: core: Replace of_offset with accessor
[people/ms/u-boot.git] / drivers / pci / pci_tegra.c
1 /*
2 * Copyright (c) 2010, CompuLab, Ltd.
3 * Author: Mike Rapoport <mike@compulab.co.il>
4 *
5 * Based on NVIDIA PCIe driver
6 * Copyright (c) 2008-2009, NVIDIA Corporation.
7 *
8 * Copyright (c) 2013-2014, NVIDIA Corporation.
9 *
10 * SPDX-License-Identifier: GPL-2.0
11 */
12
13 #define pr_fmt(fmt) "tegra-pcie: " fmt
14
15 #include <common.h>
16 #include <clk.h>
17 #include <dm.h>
18 #include <errno.h>
19 #include <fdtdec.h>
20 #include <malloc.h>
21 #include <pci.h>
22 #include <power-domain.h>
23 #include <reset.h>
24
25 #include <asm/io.h>
26 #include <asm/gpio.h>
27
28 #include <linux/list.h>
29
30 #ifndef CONFIG_TEGRA186
31 #include <asm/arch/clock.h>
32 #include <asm/arch/powergate.h>
33 #include <asm/arch-tegra/xusb-padctl.h>
34 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
35 #endif
36
37 /*
38 * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that
39 * should not be present. These are needed because newer Tegra SoCs support
40 * only the standard clock/reset APIs, whereas older Tegra SoCs support only
41 * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
42 * fixed to implement the standard APIs, and all drivers converted to solely
43 * use the new standard APIs, with no ifdefs.
44 */
45
46 DECLARE_GLOBAL_DATA_PTR;
47
48 #define AFI_AXI_BAR0_SZ 0x00
49 #define AFI_AXI_BAR1_SZ 0x04
50 #define AFI_AXI_BAR2_SZ 0x08
51 #define AFI_AXI_BAR3_SZ 0x0c
52 #define AFI_AXI_BAR4_SZ 0x10
53 #define AFI_AXI_BAR5_SZ 0x14
54
55 #define AFI_AXI_BAR0_START 0x18
56 #define AFI_AXI_BAR1_START 0x1c
57 #define AFI_AXI_BAR2_START 0x20
58 #define AFI_AXI_BAR3_START 0x24
59 #define AFI_AXI_BAR4_START 0x28
60 #define AFI_AXI_BAR5_START 0x2c
61
62 #define AFI_FPCI_BAR0 0x30
63 #define AFI_FPCI_BAR1 0x34
64 #define AFI_FPCI_BAR2 0x38
65 #define AFI_FPCI_BAR3 0x3c
66 #define AFI_FPCI_BAR4 0x40
67 #define AFI_FPCI_BAR5 0x44
68
69 #define AFI_CACHE_BAR0_SZ 0x48
70 #define AFI_CACHE_BAR0_ST 0x4c
71 #define AFI_CACHE_BAR1_SZ 0x50
72 #define AFI_CACHE_BAR1_ST 0x54
73
74 #define AFI_MSI_BAR_SZ 0x60
75 #define AFI_MSI_FPCI_BAR_ST 0x64
76 #define AFI_MSI_AXI_BAR_ST 0x68
77
78 #define AFI_CONFIGURATION 0xac
79 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
80
81 #define AFI_FPCI_ERROR_MASKS 0xb0
82
83 #define AFI_INTR_MASK 0xb4
84 #define AFI_INTR_MASK_INT_MASK (1 << 0)
85 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
86
87 #define AFI_SM_INTR_ENABLE 0xc4
88 #define AFI_SM_INTR_INTA_ASSERT (1 << 0)
89 #define AFI_SM_INTR_INTB_ASSERT (1 << 1)
90 #define AFI_SM_INTR_INTC_ASSERT (1 << 2)
91 #define AFI_SM_INTR_INTD_ASSERT (1 << 3)
92 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
93 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
94 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
95 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
96
97 #define AFI_AFI_INTR_ENABLE 0xc8
98 #define AFI_INTR_EN_INI_SLVERR (1 << 0)
99 #define AFI_INTR_EN_INI_DECERR (1 << 1)
100 #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
101 #define AFI_INTR_EN_TGT_DECERR (1 << 3)
102 #define AFI_INTR_EN_TGT_WRERR (1 << 4)
103 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
104 #define AFI_INTR_EN_AXI_DECERR (1 << 6)
105 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
106 #define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
107
108 #define AFI_PCIE_CONFIG 0x0f8
109 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
110 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
111 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
112 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
113 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20)
114 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20)
115 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
116 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
117 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)
118 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
119 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401 (0x0 << 20)
120 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211 (0x1 << 20)
121 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111 (0x2 << 20)
122
123 #define AFI_FUSE 0x104
124 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
125
126 #define AFI_PEX0_CTRL 0x110
127 #define AFI_PEX1_CTRL 0x118
128 #define AFI_PEX2_CTRL 0x128
129 #define AFI_PEX2_CTRL_T186 0x19c
130 #define AFI_PEX_CTRL_RST (1 << 0)
131 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
132 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
133 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
134
135 #define AFI_PLLE_CONTROL 0x160
136 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
137 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
138
139 #define AFI_PEXBIAS_CTRL_0 0x168
140
141 #define PADS_CTL_SEL 0x0000009C
142
143 #define PADS_CTL 0x000000A0
144 #define PADS_CTL_IDDQ_1L (1 << 0)
145 #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
146 #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
147
148 #define PADS_PLL_CTL_TEGRA20 0x000000B8
149 #define PADS_PLL_CTL_TEGRA30 0x000000B4
150 #define PADS_PLL_CTL_RST_B4SM (0x1 << 1)
151 #define PADS_PLL_CTL_LOCKDET (0x1 << 8)
152 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
153 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16)
154 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16)
155 #define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16)
156 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
157 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20)
158 #define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20)
159 #define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22)
160
161 #define PADS_REFCLK_CFG0 0x000000C8
162 #define PADS_REFCLK_CFG1 0x000000CC
163
164 /*
165 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
166 * entries, one entry per PCIe port. These field definitions and desired
167 * values aren't in the TRM, but do come from NVIDIA.
168 */
169 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */
170 #define PADS_REFCLK_CFG_E_TERM_SHIFT 7
171 #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */
172 #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */
173
174 #define RP_VEND_XP 0x00000F00
175 #define RP_VEND_XP_DL_UP (1 << 30)
176
177 #define RP_VEND_CTL2 0x00000FA8
178 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7)
179
180 #define RP_PRIV_MISC 0x00000FE0
181 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0)
182 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0)
183
184 #define RP_LINK_CONTROL_STATUS 0x00000090
185 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
186 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
187
188 enum tegra_pci_id {
189 TEGRA20_PCIE,
190 TEGRA30_PCIE,
191 TEGRA124_PCIE,
192 TEGRA210_PCIE,
193 TEGRA186_PCIE,
194 };
195
196 struct tegra_pcie_port {
197 struct tegra_pcie *pcie;
198
199 struct fdt_resource regs;
200 unsigned int num_lanes;
201 unsigned int index;
202
203 struct list_head list;
204 };
205
206 struct tegra_pcie_soc {
207 unsigned int num_ports;
208 unsigned long pads_pll_ctl;
209 unsigned long tx_ref_sel;
210 unsigned long afi_pex2_ctrl;
211 u32 pads_refclk_cfg0;
212 u32 pads_refclk_cfg1;
213 bool has_pex_clkreq_en;
214 bool has_pex_bias_ctrl;
215 bool has_cml_clk;
216 bool has_gen2;
217 bool force_pca_enable;
218 };
219
220 struct tegra_pcie {
221 struct pci_controller hose;
222
223 struct fdt_resource pads;
224 struct fdt_resource afi;
225 struct fdt_resource cs;
226
227 struct list_head ports;
228 unsigned long xbar;
229
230 const struct tegra_pcie_soc *soc;
231
232 #ifdef CONFIG_TEGRA186
233 struct clk clk_afi;
234 struct clk clk_pex;
235 struct reset_ctl reset_afi;
236 struct reset_ctl reset_pex;
237 struct reset_ctl reset_pcie_x;
238 struct power_domain pwrdom;
239 #else
240 struct tegra_xusb_phy *phy;
241 #endif
242 };
243
244 static void afi_writel(struct tegra_pcie *pcie, unsigned long value,
245 unsigned long offset)
246 {
247 writel(value, pcie->afi.start + offset);
248 }
249
250 static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset)
251 {
252 return readl(pcie->afi.start + offset);
253 }
254
255 static void pads_writel(struct tegra_pcie *pcie, unsigned long value,
256 unsigned long offset)
257 {
258 writel(value, pcie->pads.start + offset);
259 }
260
261 #ifndef CONFIG_TEGRA186
262 static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset)
263 {
264 return readl(pcie->pads.start + offset);
265 }
266 #endif
267
268 static unsigned long rp_readl(struct tegra_pcie_port *port,
269 unsigned long offset)
270 {
271 return readl(port->regs.start + offset);
272 }
273
274 static void rp_writel(struct tegra_pcie_port *port, unsigned long value,
275 unsigned long offset)
276 {
277 writel(value, port->regs.start + offset);
278 }
279
280 static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf, int where)
281 {
282 return ((where & 0xf00) << 16) | (PCI_BUS(bdf) << 16) |
283 (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) |
284 (where & 0xfc);
285 }
286
287 static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf,
288 int where, unsigned long *address)
289 {
290 unsigned int bus = PCI_BUS(bdf);
291
292 if (bus == 0) {
293 unsigned int dev = PCI_DEV(bdf);
294 struct tegra_pcie_port *port;
295
296 list_for_each_entry(port, &pcie->ports, list) {
297 if (port->index + 1 == dev) {
298 *address = port->regs.start + (where & ~3);
299 return 0;
300 }
301 }
302 return -EFAULT;
303 } else {
304 #ifdef CONFIG_TEGRA20
305 unsigned int dev = PCI_DEV(bdf);
306 if (dev != 0)
307 return -EFAULT;
308 #endif
309
310 *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where);
311 return 0;
312 }
313 }
314
315 static int pci_tegra_read_config(struct udevice *bus, pci_dev_t bdf,
316 uint offset, ulong *valuep,
317 enum pci_size_t size)
318 {
319 struct tegra_pcie *pcie = dev_get_priv(bus);
320 unsigned long address, value;
321 int err;
322
323 err = tegra_pcie_conf_address(pcie, bdf, offset, &address);
324 if (err < 0) {
325 value = 0xffffffff;
326 goto done;
327 }
328
329 value = readl(address);
330
331 #ifdef CONFIG_TEGRA20
332 /* fixup root port class */
333 if (PCI_BUS(bdf) == 0) {
334 if ((offset & ~3) == PCI_CLASS_REVISION) {
335 value &= ~0x00ff0000;
336 value |= PCI_CLASS_BRIDGE_PCI << 16;
337 }
338 }
339 #endif
340
341 done:
342 *valuep = pci_conv_32_to_size(value, offset, size);
343
344 return 0;
345 }
346
347 static int pci_tegra_write_config(struct udevice *bus, pci_dev_t bdf,
348 uint offset, ulong value,
349 enum pci_size_t size)
350 {
351 struct tegra_pcie *pcie = dev_get_priv(bus);
352 unsigned long address;
353 ulong old;
354 int err;
355
356 err = tegra_pcie_conf_address(pcie, bdf, offset, &address);
357 if (err < 0)
358 return 0;
359
360 old = readl(address);
361 value = pci_conv_size_to_32(old, value, offset, size);
362 writel(value, address);
363
364 return 0;
365 }
366
367 static int tegra_pcie_port_parse_dt(const void *fdt, int node,
368 struct tegra_pcie_port *port)
369 {
370 const u32 *addr;
371 int len;
372
373 addr = fdt_getprop(fdt, node, "assigned-addresses", &len);
374 if (!addr) {
375 error("property \"assigned-addresses\" not found");
376 return -FDT_ERR_NOTFOUND;
377 }
378
379 port->regs.start = fdt32_to_cpu(addr[2]);
380 port->regs.end = port->regs.start + fdt32_to_cpu(addr[4]);
381
382 return 0;
383 }
384
385 static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes,
386 enum tegra_pci_id id, unsigned long *xbar)
387 {
388 switch (id) {
389 case TEGRA20_PCIE:
390 switch (lanes) {
391 case 0x00000004:
392 debug("single-mode configuration\n");
393 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE;
394 return 0;
395
396 case 0x00000202:
397 debug("dual-mode configuration\n");
398 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
399 return 0;
400 }
401 break;
402 case TEGRA30_PCIE:
403 switch (lanes) {
404 case 0x00000204:
405 debug("4x1, 2x1 configuration\n");
406 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420;
407 return 0;
408
409 case 0x00020202:
410 debug("2x3 configuration\n");
411 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222;
412 return 0;
413
414 case 0x00010104:
415 debug("4x1, 1x2 configuration\n");
416 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
417 return 0;
418 }
419 break;
420 case TEGRA124_PCIE:
421 case TEGRA210_PCIE:
422 switch (lanes) {
423 case 0x0000104:
424 debug("4x1, 1x1 configuration\n");
425 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
426 return 0;
427
428 case 0x0000102:
429 debug("2x1, 1x1 configuration\n");
430 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1;
431 return 0;
432 }
433 break;
434 case TEGRA186_PCIE:
435 switch (lanes) {
436 case 0x0010004:
437 debug("x4 x1 configuration\n");
438 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401;
439 return 0;
440
441 case 0x0010102:
442 debug("x2 x1 x1 configuration\n");
443 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211;
444 return 0;
445
446 case 0x0010101:
447 debug("x1 x1 x1 configuration\n");
448 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111;
449 return 0;
450 }
451 break;
452 default:
453 break;
454 }
455
456 return -FDT_ERR_NOTFOUND;
457 }
458
459 static int tegra_pcie_parse_port_info(const void *fdt, int node,
460 unsigned int *index,
461 unsigned int *lanes)
462 {
463 struct fdt_pci_addr addr;
464 int err;
465
466 err = fdtdec_get_int(fdt, node, "nvidia,num-lanes", 0);
467 if (err < 0) {
468 error("failed to parse \"nvidia,num-lanes\" property");
469 return err;
470 }
471
472 *lanes = err;
473
474 err = fdtdec_get_pci_addr(fdt, node, 0, "reg", &addr);
475 if (err < 0) {
476 error("failed to parse \"reg\" property");
477 return err;
478 }
479
480 *index = PCI_DEV(addr.phys_hi) - 1;
481
482 return 0;
483 }
484
485 int __weak tegra_pcie_board_init(void)
486 {
487 return 0;
488 }
489
490 static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id,
491 struct tegra_pcie *pcie)
492 {
493 int err, subnode;
494 u32 lanes = 0;
495
496 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "pads",
497 &pcie->pads);
498 if (err < 0) {
499 error("resource \"pads\" not found");
500 return err;
501 }
502
503 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "afi",
504 &pcie->afi);
505 if (err < 0) {
506 error("resource \"afi\" not found");
507 return err;
508 }
509
510 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "cs",
511 &pcie->cs);
512 if (err < 0) {
513 error("resource \"cs\" not found");
514 return err;
515 }
516
517 err = tegra_pcie_board_init();
518 if (err < 0) {
519 error("tegra_pcie_board_init() failed: err=%d", err);
520 return err;
521 }
522
523 #ifndef CONFIG_TEGRA186
524 pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE);
525 if (pcie->phy) {
526 err = tegra_xusb_phy_prepare(pcie->phy);
527 if (err < 0) {
528 error("failed to prepare PHY: %d", err);
529 return err;
530 }
531 }
532 #endif
533
534 fdt_for_each_subnode(subnode, fdt, node) {
535 unsigned int index = 0, num_lanes = 0;
536 struct tegra_pcie_port *port;
537
538 err = tegra_pcie_parse_port_info(fdt, subnode, &index,
539 &num_lanes);
540 if (err < 0) {
541 error("failed to obtain root port info");
542 continue;
543 }
544
545 lanes |= num_lanes << (index << 3);
546
547 if (!fdtdec_get_is_enabled(fdt, subnode))
548 continue;
549
550 port = malloc(sizeof(*port));
551 if (!port)
552 continue;
553
554 memset(port, 0, sizeof(*port));
555 port->num_lanes = num_lanes;
556 port->index = index;
557
558 err = tegra_pcie_port_parse_dt(fdt, subnode, port);
559 if (err < 0) {
560 free(port);
561 continue;
562 }
563
564 list_add_tail(&port->list, &pcie->ports);
565 port->pcie = pcie;
566 }
567
568 err = tegra_pcie_get_xbar_config(fdt, node, lanes, id, &pcie->xbar);
569 if (err < 0) {
570 error("invalid lane configuration");
571 return err;
572 }
573
574 return 0;
575 }
576
577 #ifdef CONFIG_TEGRA186
578 static int tegra_pcie_power_on(struct tegra_pcie *pcie)
579 {
580 int ret;
581
582 ret = power_domain_on(&pcie->pwrdom);
583 if (ret) {
584 error("power_domain_on() failed: %d\n", ret);
585 return ret;
586 }
587
588 ret = clk_enable(&pcie->clk_afi);
589 if (ret) {
590 error("clk_enable(afi) failed: %d\n", ret);
591 return ret;
592 }
593
594 ret = clk_enable(&pcie->clk_pex);
595 if (ret) {
596 error("clk_enable(pex) failed: %d\n", ret);
597 return ret;
598 }
599
600 ret = reset_deassert(&pcie->reset_afi);
601 if (ret) {
602 error("reset_deassert(afi) failed: %d\n", ret);
603 return ret;
604 }
605
606 ret = reset_deassert(&pcie->reset_pex);
607 if (ret) {
608 error("reset_deassert(pex) failed: %d\n", ret);
609 return ret;
610 }
611
612 return 0;
613 }
614 #else
615 static int tegra_pcie_power_on(struct tegra_pcie *pcie)
616 {
617 const struct tegra_pcie_soc *soc = pcie->soc;
618 unsigned long value;
619 int err;
620
621 /* reset PCIEXCLK logic, AFI controller and PCIe controller */
622 reset_set_enable(PERIPH_ID_PCIEXCLK, 1);
623 reset_set_enable(PERIPH_ID_AFI, 1);
624 reset_set_enable(PERIPH_ID_PCIE, 1);
625
626 err = tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
627 if (err < 0) {
628 error("failed to power off PCIe partition: %d", err);
629 return err;
630 }
631
632 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
633 PERIPH_ID_PCIE);
634 if (err < 0) {
635 error("failed to power up PCIe partition: %d", err);
636 return err;
637 }
638
639 /* take AFI controller out of reset */
640 reset_set_enable(PERIPH_ID_AFI, 0);
641
642 /* enable AFI clock */
643 clock_enable(PERIPH_ID_AFI);
644
645 if (soc->has_cml_clk) {
646 /* enable CML clock */
647 value = readl(NV_PA_CLK_RST_BASE + 0x48c);
648 value |= (1 << 0);
649 value &= ~(1 << 1);
650 writel(value, NV_PA_CLK_RST_BASE + 0x48c);
651 }
652
653 err = tegra_plle_enable();
654 if (err < 0) {
655 error("failed to enable PLLE: %d\n", err);
656 return err;
657 }
658
659 return 0;
660 }
661
662 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout)
663 {
664 const struct tegra_pcie_soc *soc = pcie->soc;
665 unsigned long start = get_timer(0);
666 u32 value;
667
668 while (get_timer(start) < timeout) {
669 value = pads_readl(pcie, soc->pads_pll_ctl);
670 if (value & PADS_PLL_CTL_LOCKDET)
671 return 0;
672 }
673
674 return -ETIMEDOUT;
675 }
676
677 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
678 {
679 const struct tegra_pcie_soc *soc = pcie->soc;
680 u32 value;
681 int err;
682
683 /* initialize internal PHY, enable up to 16 PCIe lanes */
684 pads_writel(pcie, 0, PADS_CTL_SEL);
685
686 /* override IDDQ to 1 on all 4 lanes */
687 value = pads_readl(pcie, PADS_CTL);
688 value |= PADS_CTL_IDDQ_1L;
689 pads_writel(pcie, value, PADS_CTL);
690
691 /*
692 * Set up PHY PLL inputs select PLLE output as refclock, set TX
693 * ref sel to div10 (not div5).
694 */
695 value = pads_readl(pcie, soc->pads_pll_ctl);
696 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
697 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
698 pads_writel(pcie, value, soc->pads_pll_ctl);
699
700 /* reset PLL */
701 value = pads_readl(pcie, soc->pads_pll_ctl);
702 value &= ~PADS_PLL_CTL_RST_B4SM;
703 pads_writel(pcie, value, soc->pads_pll_ctl);
704
705 udelay(20);
706
707 /* take PLL out of reset */
708 value = pads_readl(pcie, soc->pads_pll_ctl);
709 value |= PADS_PLL_CTL_RST_B4SM;
710 pads_writel(pcie, value, soc->pads_pll_ctl);
711
712 /* wait for the PLL to lock */
713 err = tegra_pcie_pll_wait(pcie, 500);
714 if (err < 0) {
715 error("PLL failed to lock: %d", err);
716 return err;
717 }
718
719 /* turn off IDDQ override */
720 value = pads_readl(pcie, PADS_CTL);
721 value &= ~PADS_CTL_IDDQ_1L;
722 pads_writel(pcie, value, PADS_CTL);
723
724 /* enable TX/RX data */
725 value = pads_readl(pcie, PADS_CTL);
726 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L;
727 pads_writel(pcie, value, PADS_CTL);
728
729 return 0;
730 }
731 #endif
732
733 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
734 {
735 const struct tegra_pcie_soc *soc = pcie->soc;
736 struct tegra_pcie_port *port;
737 u32 value;
738 int err;
739
740 #ifdef CONFIG_TEGRA186
741 {
742 #else
743 if (pcie->phy) {
744 #endif
745 value = afi_readl(pcie, AFI_PLLE_CONTROL);
746 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
747 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
748 afi_writel(pcie, value, AFI_PLLE_CONTROL);
749 }
750
751 if (soc->has_pex_bias_ctrl)
752 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
753
754 value = afi_readl(pcie, AFI_PCIE_CONFIG);
755 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
756 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar;
757
758 list_for_each_entry(port, &pcie->ports, list)
759 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
760
761 afi_writel(pcie, value, AFI_PCIE_CONFIG);
762
763 value = afi_readl(pcie, AFI_FUSE);
764
765 if (soc->has_gen2)
766 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
767 else
768 value |= AFI_FUSE_PCIE_T0_GEN2_DIS;
769
770 afi_writel(pcie, value, AFI_FUSE);
771
772 #ifndef CONFIG_TEGRA186
773 if (pcie->phy)
774 err = tegra_xusb_phy_enable(pcie->phy);
775 else
776 err = tegra_pcie_phy_enable(pcie);
777
778 if (err < 0) {
779 error("failed to power on PHY: %d\n", err);
780 return err;
781 }
782 #endif
783
784 /* take the PCIEXCLK logic out of reset */
785 #ifdef CONFIG_TEGRA186
786 err = reset_deassert(&pcie->reset_pcie_x);
787 if (err) {
788 error("reset_deassert(pcie_x) failed: %d\n", err);
789 return err;
790 }
791 #else
792 reset_set_enable(PERIPH_ID_PCIEXCLK, 0);
793 #endif
794
795 /* finally enable PCIe */
796 value = afi_readl(pcie, AFI_CONFIGURATION);
797 value |= AFI_CONFIGURATION_EN_FPCI;
798 afi_writel(pcie, value, AFI_CONFIGURATION);
799
800 /* disable all interrupts */
801 afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE);
802 afi_writel(pcie, 0, AFI_SM_INTR_ENABLE);
803 afi_writel(pcie, 0, AFI_INTR_MASK);
804 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
805
806 return 0;
807 }
808
809 static int tegra_pcie_setup_translations(struct udevice *bus)
810 {
811 struct tegra_pcie *pcie = dev_get_priv(bus);
812 unsigned long fpci, axi, size;
813 struct pci_region *io, *mem, *pref;
814 int count;
815
816 /* BAR 0: type 1 extended configuration space */
817 fpci = 0xfe100000;
818 size = fdt_resource_size(&pcie->cs);
819 axi = pcie->cs.start;
820
821 afi_writel(pcie, axi, AFI_AXI_BAR0_START);
822 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
823 afi_writel(pcie, fpci, AFI_FPCI_BAR0);
824
825 count = pci_get_regions(bus, &io, &mem, &pref);
826 if (count != 3)
827 return -EINVAL;
828
829 /* BAR 1: downstream I/O */
830 fpci = 0xfdfc0000;
831 size = io->size;
832 axi = io->phys_start;
833
834 afi_writel(pcie, axi, AFI_AXI_BAR1_START);
835 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
836 afi_writel(pcie, fpci, AFI_FPCI_BAR1);
837
838 /* BAR 2: prefetchable memory */
839 fpci = (((pref->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
840 size = pref->size;
841 axi = pref->phys_start;
842
843 afi_writel(pcie, axi, AFI_AXI_BAR2_START);
844 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
845 afi_writel(pcie, fpci, AFI_FPCI_BAR2);
846
847 /* BAR 3: non-prefetchable memory */
848 fpci = (((mem->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
849 size = mem->size;
850 axi = mem->phys_start;
851
852 afi_writel(pcie, axi, AFI_AXI_BAR3_START);
853 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
854 afi_writel(pcie, fpci, AFI_FPCI_BAR3);
855
856 /* NULL out the remaining BARs as they are not used */
857 afi_writel(pcie, 0, AFI_AXI_BAR4_START);
858 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
859 afi_writel(pcie, 0, AFI_FPCI_BAR4);
860
861 afi_writel(pcie, 0, AFI_AXI_BAR5_START);
862 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
863 afi_writel(pcie, 0, AFI_FPCI_BAR5);
864
865 /* map all upstream transactions as uncached */
866 afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST);
867 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
868 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
869 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
870
871 /* MSI translations are setup only when needed */
872 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
873 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
874 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
875 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
876
877 return 0;
878 }
879
880 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
881 {
882 unsigned long ret = 0;
883
884 switch (port->index) {
885 case 0:
886 ret = AFI_PEX0_CTRL;
887 break;
888
889 case 1:
890 ret = AFI_PEX1_CTRL;
891 break;
892
893 case 2:
894 ret = port->pcie->soc->afi_pex2_ctrl;
895 break;
896 }
897
898 return ret;
899 }
900
901 static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
902 {
903 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
904 unsigned long value;
905
906 /* pulse reset signel */
907 value = afi_readl(port->pcie, ctrl);
908 value &= ~AFI_PEX_CTRL_RST;
909 afi_writel(port->pcie, value, ctrl);
910
911 udelay(2000);
912
913 value = afi_readl(port->pcie, ctrl);
914 value |= AFI_PEX_CTRL_RST;
915 afi_writel(port->pcie, value, ctrl);
916 }
917
918 static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
919 {
920 struct tegra_pcie *pcie = port->pcie;
921 const struct tegra_pcie_soc *soc = pcie->soc;
922 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
923 unsigned long value;
924
925 /* enable reference clock */
926 value = afi_readl(pcie, ctrl);
927 value |= AFI_PEX_CTRL_REFCLK_EN;
928
929 if (pcie->soc->has_pex_clkreq_en)
930 value |= AFI_PEX_CTRL_CLKREQ_EN;
931
932 value |= AFI_PEX_CTRL_OVERRIDE_EN;
933
934 afi_writel(pcie, value, ctrl);
935
936 tegra_pcie_port_reset(port);
937
938 if (soc->force_pca_enable) {
939 value = rp_readl(port, RP_VEND_CTL2);
940 value |= RP_VEND_CTL2_PCA_ENABLE;
941 rp_writel(port, value, RP_VEND_CTL2);
942 }
943
944 /* configure the reference clock driver */
945 pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
946 if (soc->num_ports > 2)
947 pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
948 }
949
950 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
951 {
952 unsigned int retries = 3;
953 unsigned long value;
954
955 value = rp_readl(port, RP_PRIV_MISC);
956 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
957 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
958 rp_writel(port, value, RP_PRIV_MISC);
959
960 do {
961 unsigned int timeout = 200;
962
963 do {
964 value = rp_readl(port, RP_VEND_XP);
965 if (value & RP_VEND_XP_DL_UP)
966 break;
967
968 udelay(2000);
969 } while (--timeout);
970
971 if (!timeout) {
972 debug("link %u down, retrying\n", port->index);
973 goto retry;
974 }
975
976 timeout = 200;
977
978 do {
979 value = rp_readl(port, RP_LINK_CONTROL_STATUS);
980 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
981 return true;
982
983 udelay(2000);
984 } while (--timeout);
985
986 retry:
987 tegra_pcie_port_reset(port);
988 } while (--retries);
989
990 return false;
991 }
992
993 static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
994 {
995 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
996 unsigned long value;
997
998 /* assert port reset */
999 value = afi_readl(port->pcie, ctrl);
1000 value &= ~AFI_PEX_CTRL_RST;
1001 afi_writel(port->pcie, value, ctrl);
1002
1003 /* disable reference clock */
1004 value = afi_readl(port->pcie, ctrl);
1005 value &= ~AFI_PEX_CTRL_REFCLK_EN;
1006 afi_writel(port->pcie, value, ctrl);
1007 }
1008
1009 static void tegra_pcie_port_free(struct tegra_pcie_port *port)
1010 {
1011 list_del(&port->list);
1012 free(port);
1013 }
1014
1015 static int tegra_pcie_enable(struct tegra_pcie *pcie)
1016 {
1017 struct tegra_pcie_port *port, *tmp;
1018
1019 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
1020 debug("probing port %u, using %u lanes\n", port->index,
1021 port->num_lanes);
1022
1023 tegra_pcie_port_enable(port);
1024
1025 if (tegra_pcie_port_check_link(port))
1026 continue;
1027
1028 debug("link %u down, ignoring\n", port->index);
1029
1030 tegra_pcie_port_disable(port);
1031 tegra_pcie_port_free(port);
1032 }
1033
1034 return 0;
1035 }
1036
1037 static const struct tegra_pcie_soc pci_tegra_soc[] = {
1038 [TEGRA20_PCIE] = {
1039 .num_ports = 2,
1040 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
1041 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
1042 .pads_refclk_cfg0 = 0xfa5cfa5c,
1043 .has_pex_clkreq_en = false,
1044 .has_pex_bias_ctrl = false,
1045 .has_cml_clk = false,
1046 .has_gen2 = false,
1047 },
1048 [TEGRA30_PCIE] = {
1049 .num_ports = 3,
1050 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
1051 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
1052 .afi_pex2_ctrl = AFI_PEX2_CTRL,
1053 .pads_refclk_cfg0 = 0xfa5cfa5c,
1054 .pads_refclk_cfg1 = 0xfa5cfa5c,
1055 .has_pex_clkreq_en = true,
1056 .has_pex_bias_ctrl = true,
1057 .has_cml_clk = true,
1058 .has_gen2 = false,
1059 },
1060 [TEGRA124_PCIE] = {
1061 .num_ports = 2,
1062 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
1063 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
1064 .pads_refclk_cfg0 = 0x44ac44ac,
1065 .has_pex_clkreq_en = true,
1066 .has_pex_bias_ctrl = true,
1067 .has_cml_clk = true,
1068 .has_gen2 = true,
1069 },
1070 [TEGRA210_PCIE] = {
1071 .num_ports = 2,
1072 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
1073 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
1074 .pads_refclk_cfg0 = 0x90b890b8,
1075 .has_pex_clkreq_en = true,
1076 .has_pex_bias_ctrl = true,
1077 .has_cml_clk = true,
1078 .has_gen2 = true,
1079 .force_pca_enable = true,
1080 },
1081 [TEGRA186_PCIE] = {
1082 .num_ports = 3,
1083 .afi_pex2_ctrl = AFI_PEX2_CTRL_T186,
1084 .pads_refclk_cfg0 = 0x80b880b8,
1085 .pads_refclk_cfg1 = 0x000480b8,
1086 .has_pex_clkreq_en = true,
1087 .has_pex_bias_ctrl = true,
1088 .has_gen2 = true,
1089 },
1090 };
1091
1092 static int pci_tegra_ofdata_to_platdata(struct udevice *dev)
1093 {
1094 struct tegra_pcie *pcie = dev_get_priv(dev);
1095 enum tegra_pci_id id;
1096
1097 id = dev_get_driver_data(dev);
1098 pcie->soc = &pci_tegra_soc[id];
1099
1100 INIT_LIST_HEAD(&pcie->ports);
1101
1102 if (tegra_pcie_parse_dt(gd->fdt_blob, dev_of_offset(dev), id, pcie))
1103 return -EINVAL;
1104
1105 return 0;
1106 }
1107
1108 static int pci_tegra_probe(struct udevice *dev)
1109 {
1110 struct tegra_pcie *pcie = dev_get_priv(dev);
1111 int err;
1112
1113 #ifdef CONFIG_TEGRA186
1114 err = clk_get_by_name(dev, "afi", &pcie->clk_afi);
1115 if (err) {
1116 debug("clk_get_by_name(afi) failed: %d\n", err);
1117 return err;
1118 }
1119
1120 err = clk_get_by_name(dev, "pex", &pcie->clk_pex);
1121 if (err) {
1122 debug("clk_get_by_name(pex) failed: %d\n", err);
1123 return err;
1124 }
1125
1126 err = reset_get_by_name(dev, "afi", &pcie->reset_afi);
1127 if (err) {
1128 debug("reset_get_by_name(afi) failed: %d\n", err);
1129 return err;
1130 }
1131
1132 err = reset_get_by_name(dev, "pex", &pcie->reset_pex);
1133 if (err) {
1134 debug("reset_get_by_name(pex) failed: %d\n", err);
1135 return err;
1136 }
1137
1138 err = reset_get_by_name(dev, "pcie_x", &pcie->reset_pcie_x);
1139 if (err) {
1140 debug("reset_get_by_name(pcie_x) failed: %d\n", err);
1141 return err;
1142 }
1143
1144 err = power_domain_get(dev, &pcie->pwrdom);
1145 if (err) {
1146 debug("power_domain_get() failed: %d\n", err);
1147 return err;
1148 }
1149 #endif
1150
1151 err = tegra_pcie_power_on(pcie);
1152 if (err < 0) {
1153 error("failed to power on");
1154 return err;
1155 }
1156
1157 err = tegra_pcie_enable_controller(pcie);
1158 if (err < 0) {
1159 error("failed to enable controller");
1160 return err;
1161 }
1162
1163 err = tegra_pcie_setup_translations(dev);
1164 if (err < 0) {
1165 error("failed to decode ranges");
1166 return err;
1167 }
1168
1169 err = tegra_pcie_enable(pcie);
1170 if (err < 0) {
1171 error("failed to enable PCIe");
1172 return err;
1173 }
1174
1175 return 0;
1176 }
1177
1178 static const struct dm_pci_ops pci_tegra_ops = {
1179 .read_config = pci_tegra_read_config,
1180 .write_config = pci_tegra_write_config,
1181 };
1182
1183 static const struct udevice_id pci_tegra_ids[] = {
1184 { .compatible = "nvidia,tegra20-pcie", .data = TEGRA20_PCIE },
1185 { .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE },
1186 { .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE },
1187 { .compatible = "nvidia,tegra210-pcie", .data = TEGRA210_PCIE },
1188 { .compatible = "nvidia,tegra186-pcie", .data = TEGRA186_PCIE },
1189 { }
1190 };
1191
1192 U_BOOT_DRIVER(pci_tegra) = {
1193 .name = "pci_tegra",
1194 .id = UCLASS_PCI,
1195 .of_match = pci_tegra_ids,
1196 .ops = &pci_tegra_ops,
1197 .ofdata_to_platdata = pci_tegra_ofdata_to_platdata,
1198 .probe = pci_tegra_probe,
1199 .priv_auto_alloc_size = sizeof(struct tegra_pcie),
1200 };
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