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git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/pci/w83c553f.c
2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * Initialisation of the PCI-to-ISA bridge and disabling the BIOS
26 * write protection (for flash) in function 0 of the chip.
27 * Enabling function 1 (IDE controller of the chip.
38 #define out8(addr,val) do { \
39 out_8((u8*) (addr),(val)); udelay(1); \
41 #define out16(addr,val) do { \
42 out_be16((u16*) (addr),(val)); udelay(1); \
45 extern uint ide_bus_offset
[CONFIG_SYS_IDE_MAXBUS
];
47 void initialise_pic(void);
48 void initialise_dma(void);
50 void initialise_w83c553f(void)
57 devbusfn
= pci_find_device(W83C553F_VID
, W83C553F_DID
, 0);
60 printf("Error: Cannot find W83C553F controller on any PCI bus.");
64 pci_read_config_word(devbusfn
, PCI_COMMAND
, ®16
);
65 reg16
|= PCI_COMMAND_MASTER
| PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
;
66 pci_write_config_word(devbusfn
, PCI_COMMAND
, reg16
);
68 pci_read_config_byte(devbusfn
, WINBOND_IPADCR
, ®8
);
69 /* 16 MB ISA memory space */
70 reg8
|= (IPADCR_IPATOM4
| IPADCR_IPATOM5
| IPADCR_IPATOM6
| IPADCR_IPATOM7
);
71 reg8
&= ~IPADCR_MBE512
;
72 pci_write_config_byte(devbusfn
, WINBOND_IPADCR
, reg8
);
74 pci_read_config_byte(devbusfn
, WINBOND_CSCR
, ®8
);
75 /* switch off BIOS write protection */
76 reg8
|= CSCR_UBIOSCSE
;
78 pci_write_config_byte(devbusfn
, WINBOND_CSCR
, reg8
);
88 pci_write_config_byte(devbusfn
, WINBOND_IDEIRCR
, 0x90);
89 pci_write_config_word(devbusfn
, WINBOND_PCIIRCR
, 0xABEF);
92 * Read IDE bus offsets from function 1 device.
93 * We must unmask the LSB indicating that ist is an IO address.
95 devbusfn
|= PCI_BDF(0,0,1);
98 * Switch off legacy IRQ for IDE and IDE port 1.
100 pci_write_config_byte(devbusfn
, 0x09, 0x8F);
102 pci_read_config_dword(devbusfn
, WINDOND_IDECSR
, ®32
);
103 reg32
&= ~(IDECSR_LEGIRQ
| IDECSR_P1EN
| IDECSR_P1F16
);
104 pci_write_config_dword(devbusfn
, WINDOND_IDECSR
, reg32
);
106 pci_read_config_dword(devbusfn
, PCI_BASE_ADDRESS_0
, &ide_bus_offset
[0]);
107 ide_bus_offset
[0] &= ~1;
108 #if CONFIG_SYS_IDE_MAXBUS > 1
109 pci_read_config_dword(devbusfn
, PCI_BASE_ADDRESS_2
, &ide_bus_offset
[1]);
110 ide_bus_offset
[1] &= ~1;
114 * Enable function 1, IDE -> busmastering and IO space access
116 pci_read_config_word(devbusfn
, PCI_COMMAND
, ®16
);
117 reg16
|= PCI_COMMAND_MASTER
| PCI_COMMAND_IO
;
118 pci_write_config_word(devbusfn
, PCI_COMMAND
, reg16
);
121 * Initialise ISA interrupt controller
126 * Initialise DMA controller
131 void initialise_pic(void)
133 out8(W83C553F_PIC1_ICW1
, 0x11);
134 out8(W83C553F_PIC1_ICW2
, 0x08);
135 out8(W83C553F_PIC1_ICW3
, 0x04);
136 out8(W83C553F_PIC1_ICW4
, 0x01);
137 out8(W83C553F_PIC1_OCW1
, 0xfb);
138 out8(W83C553F_PIC1_ELC
, 0x20);
140 out8(W83C553F_PIC2_ICW1
, 0x11);
141 out8(W83C553F_PIC2_ICW2
, 0x08);
142 out8(W83C553F_PIC2_ICW3
, 0x02);
143 out8(W83C553F_PIC2_ICW4
, 0x01);
144 out8(W83C553F_PIC2_OCW1
, 0xff);
145 out8(W83C553F_PIC2_ELC
, 0xce);
147 out8(W83C553F_TMR1_CMOD
, 0x74);
149 out8(W83C553F_PIC2_OCW1
, 0x20);
150 out8(W83C553F_PIC1_OCW1
, 0x20);
152 out8(W83C553F_PIC2_OCW1
, 0x2b);
153 out8(W83C553F_PIC1_OCW1
, 0x2b);
156 void initialise_dma(void)
158 unsigned int channel
;
159 unsigned int rvalue1
, rvalue2
;
161 /* perform a H/W reset of the devices */
163 out8(W83C553F_DMA1
+ W83C553F_DMA1_MC
, 0x00);
164 out16(W83C553F_DMA2
+ W83C553F_DMA2_MC
, 0x0000);
166 /* initialise all channels to a sane state */
168 for (channel
= 0; channel
< 4; channel
++) {
170 * dependent upon the channel, setup the specifics:
174 * autoinitialize-disable
180 rvalue1
= (W83C553F_MODE_TM_DEMAND
|W83C553F_MODE_CH0SEL
|W83C553F_MODE_TT_VERIFY
);
181 rvalue2
= (W83C553F_MODE_TM_CASCADE
|W83C553F_MODE_CH0SEL
);
184 rvalue1
= (W83C553F_MODE_TM_DEMAND
|W83C553F_MODE_CH1SEL
|W83C553F_MODE_TT_VERIFY
);
185 rvalue2
= (W83C553F_MODE_TM_DEMAND
|W83C553F_MODE_CH1SEL
|W83C553F_MODE_TT_VERIFY
);
188 rvalue1
= (W83C553F_MODE_TM_DEMAND
|W83C553F_MODE_CH2SEL
|W83C553F_MODE_TT_VERIFY
);
189 rvalue2
= (W83C553F_MODE_TM_DEMAND
|W83C553F_MODE_CH2SEL
|W83C553F_MODE_TT_VERIFY
);
192 rvalue1
= (W83C553F_MODE_TM_DEMAND
|W83C553F_MODE_CH3SEL
|W83C553F_MODE_TT_VERIFY
);
193 rvalue2
= (W83C553F_MODE_TM_DEMAND
|W83C553F_MODE_CH3SEL
|W83C553F_MODE_TT_VERIFY
);
201 /* write to write mode registers */
203 out8(W83C553F_DMA1
+ W83C553F_DMA1_WM
, rvalue1
& 0xFF);
204 out16(W83C553F_DMA2
+ W83C553F_DMA2_WM
, rvalue2
& 0x00FF);
207 /* enable all channels */
209 out8(W83C553F_DMA1
+ W83C553F_DMA1_CM
, 0x00);
210 out16(W83C553F_DMA2
+ W83C553F_DMA2_CM
, 0x0000);
212 * initialize the global DMA configuration
217 * channel group enable
220 out8(W83C553F_DMA1
+ W83C553F_DMA1_CS
, 0x00);
221 out16(W83C553F_DMA2
+ W83C553F_DMA2_CS
, 0x0000);