2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
5 * (C) Copyright 2002, 2003
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #include <asm/processor.h>
40 #define PCI_HOSE_OP(rw, size, type) \
41 int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
43 int offset, type value) \
45 return hose->rw##_##size(hose, dev, offset, value); \
48 PCI_HOSE_OP(read
, byte
, u8
*)
49 PCI_HOSE_OP(read
, word
, u16
*)
50 PCI_HOSE_OP(read
, dword
, u32
*)
51 PCI_HOSE_OP(write
, byte
, u8
)
52 PCI_HOSE_OP(write
, word
, u16
)
53 PCI_HOSE_OP(write
, dword
, u32
)
56 #define PCI_OP(rw, size, type, error_code) \
57 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
59 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
67 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
70 PCI_OP(read
, byte
, u8
*, *value
= 0xff)
71 PCI_OP(read
, word
, u16
*, *value
= 0xffff)
72 PCI_OP(read
, dword
, u32
*, *value
= 0xffffffff)
73 PCI_OP(write
, byte
, u8
, )
74 PCI_OP(write
, word
, u16
, )
75 PCI_OP(write
, dword
, u32
, )
76 #endif /* CONFIG_IXP425 */
78 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
79 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
81 int offset, type val) \
85 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
88 *val = (val32 >> ((offset & (int)off_mask) * 8)); \
93 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
94 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
96 int offset, type val) \
98 u32 val32, mask, ldata, shift; \
100 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
103 shift = ((offset & (int)off_mask) * 8); \
104 ldata = (((unsigned long)val) & val_mask) << shift; \
105 mask = val_mask << shift; \
106 val32 = (val32 & ~mask) | ldata; \
108 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
114 PCI_READ_VIA_DWORD_OP(byte
, u8
*, 0x03)
115 PCI_READ_VIA_DWORD_OP(word
, u16
*, 0x02)
116 PCI_WRITE_VIA_DWORD_OP(byte
, u8
, 0x03, 0x000000ff)
117 PCI_WRITE_VIA_DWORD_OP(word
, u16
, 0x02, 0x0000ffff)
123 static struct pci_controller
* hose_head
= NULL
;
125 void pci_register_hose(struct pci_controller
* hose
)
127 struct pci_controller
**phose
= &hose_head
;
130 phose
= &(*phose
)->next
;
137 struct pci_controller
*pci_bus_to_hose (int bus
)
139 struct pci_controller
*hose
;
141 for (hose
= hose_head
; hose
; hose
= hose
->next
)
142 if (bus
>= hose
->first_busno
&& bus
<= hose
->last_busno
)
145 printf("pci_bus_to_hose() failed\n");
149 #ifndef CONFIG_IXP425
150 pci_dev_t
pci_find_devices(struct pci_device_id
*ids
, int index
)
152 struct pci_controller
* hose
;
156 int i
, bus
, found_multi
= 0;
158 for (hose
= hose_head
; hose
; hose
= hose
->next
)
160 #ifdef CFG_SCSI_SCAN_BUS_REVERSE
161 for (bus
= hose
->last_busno
; bus
>= hose
->first_busno
; bus
--)
163 for (bus
= hose
->first_busno
; bus
<= hose
->last_busno
; bus
++)
165 for (bdf
= PCI_BDF(bus
,0,0);
166 #if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
167 bdf
< PCI_BDF(bus
,PCI_MAX_PCI_DEVICES
-1,PCI_MAX_PCI_FUNCTIONS
-1);
169 bdf
< PCI_BDF(bus
+1,0,0);
171 bdf
+= PCI_BDF(0,0,1))
173 if (!PCI_FUNC(bdf
)) {
174 pci_read_config_byte(bdf
,
178 found_multi
= header_type
& 0x80;
184 pci_read_config_word(bdf
,
187 pci_read_config_word(bdf
,
191 for (i
=0; ids
[i
].vendor
!= 0; i
++)
192 if (vendor
== ids
[i
].vendor
&&
193 device
== ids
[i
].device
)
205 #endif /* CONFIG_IXP425 */
207 pci_dev_t
pci_find_device(unsigned int vendor
, unsigned int device
, int index
)
209 static struct pci_device_id ids
[2] = {{}, {0, 0}};
211 ids
[0].vendor
= vendor
;
212 ids
[0].device
= device
;
214 return pci_find_devices(ids
, index
);
221 unsigned long pci_hose_phys_to_bus (struct pci_controller
*hose
,
222 unsigned long phys_addr
,
225 struct pci_region
*res
;
226 unsigned long bus_addr
;
230 printf ("pci_hose_phys_to_bus: %s\n", "invalid hose");
234 for (i
= 0; i
< hose
->region_count
; i
++) {
235 res
= &hose
->regions
[i
];
237 if (((res
->flags
^ flags
) & PCI_REGION_TYPE
) != 0)
240 bus_addr
= phys_addr
- res
->phys_start
+ res
->bus_start
;
242 if (bus_addr
>= res
->bus_start
&&
243 bus_addr
< res
->bus_start
+ res
->size
) {
248 printf ("pci_hose_phys_to_bus: %s\n", "invalid physical address");
254 unsigned long pci_hose_bus_to_phys(struct pci_controller
* hose
,
255 unsigned long bus_addr
,
258 struct pci_region
*res
;
262 printf ("pci_hose_bus_to_phys: %s\n", "invalid hose");
266 for (i
= 0; i
< hose
->region_count
; i
++) {
267 res
= &hose
->regions
[i
];
269 if (((res
->flags
^ flags
) & PCI_REGION_TYPE
) != 0)
272 if (bus_addr
>= res
->bus_start
&&
273 bus_addr
< res
->bus_start
+ res
->size
) {
274 return bus_addr
- res
->bus_start
+ res
->phys_start
;
278 printf ("pci_hose_bus_to_phys: %s\n", "invalid physical address");
288 int pci_hose_config_device(struct pci_controller
*hose
,
292 unsigned long command
)
294 unsigned int bar_response
, bar_size
, bar_value
, old_command
;
296 int bar
, found_mem64
;
298 debug ("PCI Config: I/O=0x%lx, Memory=0x%lx, Command=0x%lx\n",
301 pci_hose_write_config_dword (hose
, dev
, PCI_COMMAND
, 0);
303 for (bar
= PCI_BASE_ADDRESS_0
; bar
< PCI_BASE_ADDRESS_5
; bar
+= 4) {
304 pci_hose_write_config_dword (hose
, dev
, bar
, 0xffffffff);
305 pci_hose_read_config_dword (hose
, dev
, bar
, &bar_response
);
312 /* Check the BAR type and set our address mask */
313 if (bar_response
& PCI_BASE_ADDRESS_SPACE
) {
314 bar_size
= ~(bar_response
& PCI_BASE_ADDRESS_IO_MASK
) + 1;
315 /* round up region base address to a multiple of size */
316 io
= ((io
- 1) | (bar_size
- 1)) + 1;
318 /* compute new region base address */
321 if ((bar_response
& PCI_BASE_ADDRESS_MEM_TYPE_MASK
) ==
322 PCI_BASE_ADDRESS_MEM_TYPE_64
)
325 bar_size
= ~(bar_response
& PCI_BASE_ADDRESS_MEM_MASK
) + 1;
327 /* round up region base address to multiple of size */
328 mem
= ((mem
- 1) | (bar_size
- 1)) + 1;
330 /* compute new region base address */
331 mem
= mem
+ bar_size
;
334 /* Write it out and update our limit */
335 pci_hose_write_config_dword (hose
, dev
, bar
, bar_value
);
339 pci_hose_write_config_dword (hose
, dev
, bar
, 0x00000000);
343 /* Configure Cache Line Size Register */
344 pci_hose_write_config_byte (hose
, dev
, PCI_CACHE_LINE_SIZE
, 0x08);
346 /* Configure Latency Timer */
347 pci_hose_write_config_byte (hose
, dev
, PCI_LATENCY_TIMER
, 0x80);
349 /* Disable interrupt line, if device says it wants to use interrupts */
350 pci_hose_read_config_byte (hose
, dev
, PCI_INTERRUPT_PIN
, &pin
);
352 pci_hose_write_config_byte (hose
, dev
, PCI_INTERRUPT_LINE
, 0xff);
355 pci_hose_read_config_dword (hose
, dev
, PCI_COMMAND
, &old_command
);
356 pci_hose_write_config_dword (hose
, dev
, PCI_COMMAND
,
357 (old_command
& 0xffff0000) | command
);
366 struct pci_config_table
*pci_find_config(struct pci_controller
*hose
,
367 unsigned short class,
374 struct pci_config_table
*table
;
376 for (table
= hose
->config_table
; table
&& table
->vendor
; table
++) {
377 if ((table
->vendor
== PCI_ANY_ID
|| table
->vendor
== vendor
) &&
378 (table
->device
== PCI_ANY_ID
|| table
->device
== device
) &&
379 (table
->class == PCI_ANY_ID
|| table
->class == class) &&
380 (table
->bus
== PCI_ANY_ID
|| table
->bus
== bus
) &&
381 (table
->dev
== PCI_ANY_ID
|| table
->dev
== dev
) &&
382 (table
->func
== PCI_ANY_ID
|| table
->func
== func
)) {
390 void pci_cfgfunc_config_device(struct pci_controller
*hose
,
392 struct pci_config_table
*entry
)
394 pci_hose_config_device(hose
, dev
, entry
->priv
[0], entry
->priv
[1], entry
->priv
[2]);
397 void pci_cfgfunc_do_nothing(struct pci_controller
*hose
,
398 pci_dev_t dev
, struct pci_config_table
*entry
)
406 /* HJF: Changed this to return int. I think this is required
407 * to get the correct result when scanning bridges
409 extern int pciauto_config_device(struct pci_controller
*hose
, pci_dev_t dev
);
410 extern void pciauto_config_init(struct pci_controller
*hose
);
412 int pci_hose_scan_bus(struct pci_controller
*hose
, int bus
)
414 unsigned int sub_bus
, found_multi
=0;
415 unsigned short vendor
, device
, class;
416 unsigned char header_type
;
417 struct pci_config_table
*cfg
;
422 for (dev
= PCI_BDF(bus
,0,0);
423 dev
< PCI_BDF(bus
,PCI_MAX_PCI_DEVICES
-1,PCI_MAX_PCI_FUNCTIONS
-1);
424 dev
+= PCI_BDF(0,0,1))
426 /* Skip our host bridge */
427 if ( dev
== PCI_BDF(hose
->first_busno
,0,0) ) {
428 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
430 * Only skip hostbridge configuration if "pciconfighost" is not set
432 if (getenv("pciconfighost") == NULL
) {
433 continue; /* Skip our host bridge */
436 continue; /* Skip our host bridge */
440 if (PCI_FUNC(dev
) && !found_multi
)
443 pci_hose_read_config_byte(hose
, dev
, PCI_HEADER_TYPE
, &header_type
);
445 pci_hose_read_config_word(hose
, dev
, PCI_VENDOR_ID
, &vendor
);
447 if (vendor
!= 0xffff && vendor
!= 0x0000) {
450 found_multi
= header_type
& 0x80;
452 debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n",
453 PCI_BUS(dev
), PCI_DEV(dev
), PCI_FUNC(dev
) );
455 pci_hose_read_config_word(hose
, dev
, PCI_DEVICE_ID
, &device
);
456 pci_hose_read_config_word(hose
, dev
, PCI_CLASS_DEVICE
, &class);
458 cfg
= pci_find_config(hose
, class, vendor
, device
,
459 PCI_BUS(dev
), PCI_DEV(dev
), PCI_FUNC(dev
));
461 cfg
->config_device(hose
, dev
, cfg
);
462 sub_bus
= max(sub_bus
, hose
->current_busno
);
463 #ifdef CONFIG_PCI_PNP
465 int n
= pciauto_config_device(hose
, dev
);
467 sub_bus
= max(sub_bus
, n
);
471 hose
->fixup_irq(hose
, dev
);
473 #ifdef CONFIG_PCI_SCAN_SHOW
474 /* Skip our host bridge */
475 if ( dev
!= PCI_BDF(hose
->first_busno
,0,0) ) {
476 unsigned char int_line
;
478 pci_hose_read_config_byte(hose
, dev
, PCI_INTERRUPT_LINE
,
480 printf(" %02x %02x %04x %04x %04x %02x\n",
481 PCI_BUS(dev
), PCI_DEV(dev
), vendor
, device
, class,
491 int pci_hose_scan(struct pci_controller
*hose
)
493 /* Start scan at current_busno.
494 * PCIe will start scan at first_busno+1.
496 /* For legacy support, ensure current>=first */
497 if (hose
->first_busno
> hose
->current_busno
)
498 hose
->current_busno
= hose
->first_busno
;
499 #ifdef CONFIG_PCI_PNP
500 pciauto_config_init(hose
);
502 return pci_hose_scan_bus(hose
, hose
->current_busno
);
507 #if defined(CONFIG_PCI_BOOTDELAY)
511 /* wait "pcidelay" ms (if defined)... */
512 s
= getenv ("pcidelay");
514 int val
= simple_strtoul (s
, NULL
, 10);
515 for (i
=0; i
<val
; i
++)
518 #endif /* CONFIG_PCI_BOOTDELAY */
520 /* now call board specific pci_init()... */
524 #endif /* CONFIG_PCI */