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rockchip: pinctrl: rk3368: add pinctrl for SDMMC0
[people/ms/u-boot.git] / drivers / pinctrl / rockchip / pinctrl_rk3368.c
1 /*
2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
3 * Author: Andy Yan <andy.yan@rock-chips.com>
4 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #include <common.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <syscon.h>
13 #include <asm/io.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/grf_rk3368.h>
17 #include <asm/arch/periph.h>
18 #include <dm/pinctrl.h>
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 /* PMUGRF_GPIO0B_IOMUX */
23 enum {
24 GPIO0B5_SHIFT = 10,
25 GPIO0B5_MASK = GENMASK(GPIO0B5_SHIFT + 1, GPIO0B5_SHIFT),
26 GPIO0B5_GPIO = 0,
27 GPIO0B5_SPI2_CSN0 = (2 << GPIO0B5_SHIFT),
28
29 GPIO0B4_SHIFT = 8,
30 GPIO0B4_MASK = GENMASK(GPIO0B4_SHIFT + 1, GPIO0B4_SHIFT),
31 GPIO0B4_GPIO = 0,
32 GPIO0B4_SPI2_CLK = (2 << GPIO0B4_SHIFT),
33
34 GPIO0B3_SHIFT = 6,
35 GPIO0B3_MASK = GENMASK(GPIO0B3_SHIFT + 1, GPIO0B3_SHIFT),
36 GPIO0B3_GPIO = 0,
37 GPIO0B3_SPI2_TXD = (2 << GPIO0B3_SHIFT),
38
39 GPIO0B2_SHIFT = 4,
40 GPIO0B2_MASK = GENMASK(GPIO0B2_SHIFT + 1, GPIO0B2_SHIFT),
41 GPIO0B2_GPIO = 0,
42 GPIO0B2_SPI2_RXD = (2 << GPIO0B2_SHIFT),
43 };
44
45 /*GRF_GPIO0C_IOMUX*/
46 enum {
47 GPIO0C7_SHIFT = 14,
48 GPIO0C7_MASK = GENMASK(GPIO0C7_SHIFT + 1, GPIO0C7_SHIFT),
49 GPIO0C7_GPIO = 0,
50 GPIO0C7_LCDC_D19 = (1 << GPIO0C7_SHIFT),
51 GPIO0C7_TRACE_D9 = (2 << GPIO0C7_SHIFT),
52 GPIO0C7_UART1_RTSN = (3 << GPIO0C7_SHIFT),
53
54 GPIO0C6_SHIFT = 12,
55 GPIO0C6_MASK = GENMASK(GPIO0C6_SHIFT + 1, GPIO0C6_SHIFT),
56 GPIO0C6_GPIO = 0,
57 GPIO0C6_LCDC_D18 = (1 << GPIO0C6_SHIFT),
58 GPIO0C6_TRACE_D8 = (2 << GPIO0C6_SHIFT),
59 GPIO0C6_UART1_CTSN = (3 << GPIO0C6_SHIFT),
60
61 GPIO0C5_SHIFT = 10,
62 GPIO0C5_MASK = GENMASK(GPIO0C5_SHIFT + 1, GPIO0C5_SHIFT),
63 GPIO0C5_GPIO = 0,
64 GPIO0C5_LCDC_D17 = (1 << GPIO0C5_SHIFT),
65 GPIO0C5_TRACE_D7 = (2 << GPIO0C5_SHIFT),
66 GPIO0C5_UART1_SOUT = (3 << GPIO0C5_SHIFT),
67
68 GPIO0C4_SHIFT = 8,
69 GPIO0C4_MASK = GENMASK(GPIO0C4_SHIFT + 1, GPIO0C4_SHIFT),
70 GPIO0C4_GPIO = 0,
71 GPIO0C4_LCDC_D16 = (1 << GPIO0C4_SHIFT),
72 GPIO0C4_TRACE_D6 = (2 << GPIO0C4_SHIFT),
73 GPIO0C4_UART1_SIN = (3 << GPIO0C4_SHIFT),
74
75 GPIO0C3_SHIFT = 6,
76 GPIO0C3_MASK = GENMASK(GPIO0C3_SHIFT + 1, GPIO0C3_SHIFT),
77 GPIO0C3_GPIO = 0,
78 GPIO0C3_LCDC_D15 = (1 << GPIO0C3_SHIFT),
79 GPIO0C3_TRACE_D5 = (2 << GPIO0C3_SHIFT),
80 GPIO0C3_MCU_JTAG_TDO = (3 << GPIO0C3_SHIFT),
81
82 GPIO0C2_SHIFT = 4,
83 GPIO0C2_MASK = GENMASK(GPIO0C2_SHIFT + 1, GPIO0C2_SHIFT),
84 GPIO0C2_GPIO = 0,
85 GPIO0C2_LCDC_D14 = (1 << GPIO0C2_SHIFT),
86 GPIO0C2_TRACE_D4 = (2 << GPIO0C2_SHIFT),
87 GPIO0C2_MCU_JTAG_TDI = (3 << GPIO0C2_SHIFT),
88
89 GPIO0C1_SHIFT = 2,
90 GPIO0C1_MASK = GENMASK(GPIO0C1_SHIFT + 1, GPIO0C1_SHIFT),
91 GPIO0C1_GPIO = 0,
92 GPIO0C1_LCDC_D13 = (1 << GPIO0C1_SHIFT),
93 GPIO0C1_TRACE_D3 = (2 << GPIO0C1_SHIFT),
94 GPIO0C1_MCU_JTAG_TRTSN = (3 << GPIO0C1_SHIFT),
95
96 GPIO0C0_SHIFT = 0,
97 GPIO0C0_MASK = GENMASK(GPIO0C0_SHIFT + 1, GPIO0C0_SHIFT),
98 GPIO0C0_GPIO = 0,
99 GPIO0C0_LCDC_D12 = (1 << GPIO0C0_SHIFT),
100 GPIO0C0_TRACE_D2 = (2 << GPIO0C0_SHIFT),
101 GPIO0C0_MCU_JTAG_TDO = (3 << GPIO0C0_SHIFT),
102 };
103
104 /*GRF_GPIO0D_IOMUX*/
105 enum {
106 GPIO0D7_SHIFT = 14,
107 GPIO0D7_MASK = GENMASK(GPIO0D7_SHIFT + 1, GPIO0D7_SHIFT),
108 GPIO0D7_GPIO = 0,
109 GPIO0D7_LCDC_DCLK = (1 << GPIO0D7_SHIFT),
110 GPIO0D7_TRACE_CTL = (2 << GPIO0D7_SHIFT),
111 GPIO0D7_PMU_DEBUG5 = (3 << GPIO0D7_SHIFT),
112
113 GPIO0D6_SHIFT = 12,
114 GPIO0D6_MASK = GENMASK(GPIO0D6_SHIFT + 1, GPIO0D6_SHIFT),
115 GPIO0D6_GPIO = 0,
116 GPIO0D6_LCDC_DEN = (1 << GPIO0D6_SHIFT),
117 GPIO0D6_TRACE_CLK = (2 << GPIO0D6_SHIFT),
118 GPIO0D6_PMU_DEBUG4 = (3 << GPIO0D6_SHIFT),
119
120 GPIO0D5_SHIFT = 10,
121 GPIO0D5_MASK = GENMASK(GPIO0D5_SHIFT + 1, GPIO0D5_SHIFT),
122 GPIO0D5_GPIO = 0,
123 GPIO0D5_LCDC_VSYNC = (1 << GPIO0D5_SHIFT),
124 GPIO0D5_TRACE_D15 = (2 << GPIO0D5_SHIFT),
125 GPIO0D5_PMU_DEBUG3 = (3 << GPIO0D5_SHIFT),
126
127 GPIO0D4_SHIFT = 8,
128 GPIO0D4_MASK = GENMASK(GPIO0D4_SHIFT + 1, GPIO0D4_SHIFT),
129 GPIO0D4_GPIO = 0,
130 GPIO0D4_LCDC_HSYNC = (1 << GPIO0D4_SHIFT),
131 GPIO0D4_TRACE_D14 = (2 << GPIO0D4_SHIFT),
132 GPIO0D4_PMU_DEBUG2 = (3 << GPIO0D4_SHIFT),
133
134 GPIO0D3_SHIFT = 6,
135 GPIO0D3_MASK = GENMASK(GPIO0D3_SHIFT + 1, GPIO0D3_SHIFT),
136 GPIO0D3_GPIO = 0,
137 GPIO0D3_LCDC_D23 = (1 << GPIO0D3_SHIFT),
138 GPIO0D3_TRACE_D13 = (2 << GPIO0D3_SHIFT),
139 GPIO0D3_UART4_SIN = (3 << GPIO0D3_SHIFT),
140
141 GPIO0D2_SHIFT = 4,
142 GPIO0D2_MASK = GENMASK(GPIO0D2_SHIFT + 1, GPIO0D2_SHIFT),
143 GPIO0D2_GPIO = 0,
144 GPIO0D2_LCDC_D22 = (1 << GPIO0D2_SHIFT),
145 GPIO0D2_TRACE_D12 = (2 << GPIO0D2_SHIFT),
146 GPIO0D2_UART4_SOUT = (3 << GPIO0D2_SHIFT),
147
148 GPIO0D1_SHIFT = 2,
149 GPIO0D1_MASK = GENMASK(GPIO0D1_SHIFT + 1, GPIO0D1_SHIFT),
150 GPIO0D1_GPIO = 0,
151 GPIO0D1_LCDC_D21 = (1 << GPIO0D1_SHIFT),
152 GPIO0D1_TRACE_D11 = (2 << GPIO0D1_SHIFT),
153 GPIO0D1_UART4_RTSN = (3 << GPIO0D1_SHIFT),
154
155 GPIO0D0_SHIFT = 0,
156 GPIO0D0_MASK = GENMASK(GPIO0D0_SHIFT + 1, GPIO0D0_SHIFT),
157 GPIO0D0_GPIO = 0,
158 GPIO0D0_LCDC_D20 = (1 << GPIO0D0_SHIFT),
159 GPIO0D0_TRACE_D10 = (2 << GPIO0D0_SHIFT),
160 GPIO0D0_UART4_CTSN = (3 << GPIO0D0_SHIFT),
161 };
162
163 /*GRF_GPIO2A_IOMUX*/
164 enum {
165 GPIO2A7_SHIFT = 14,
166 GPIO2A7_MASK = GENMASK(GPIO2A7_SHIFT + 1, GPIO2A7_SHIFT),
167 GPIO2A7_GPIO = 0,
168 GPIO2A7_SDMMC0_D2 = (1 << GPIO2A7_SHIFT),
169 GPIO2A7_JTAG_TCK = (2 << GPIO2A7_SHIFT),
170
171 GPIO2A6_SHIFT = 12,
172 GPIO2A6_MASK = GENMASK(GPIO2A6_SHIFT + 1, GPIO2A6_SHIFT),
173 GPIO2A6_GPIO = 0,
174 GPIO2A6_SDMMC0_D1 = (1 << GPIO2A6_SHIFT),
175 GPIO2A6_UART2_SIN = (2 << GPIO2A6_SHIFT),
176
177 GPIO2A5_SHIFT = 10,
178 GPIO2A5_MASK = GENMASK(GPIO2A5_SHIFT + 1, GPIO2A5_SHIFT),
179 GPIO2A5_GPIO = 0,
180 GPIO2A5_SDMMC0_D0 = (1 << GPIO2A5_SHIFT),
181 GPIO2A5_UART2_SOUT = (2 << GPIO2A5_SHIFT),
182
183 GPIO2A4_SHIFT = 8,
184 GPIO2A4_MASK = GENMASK(GPIO2A4_SHIFT + 1, GPIO2A4_SHIFT),
185 GPIO2A4_GPIO = 0,
186 GPIO2A4_FLASH_DQS = (1 << GPIO2A4_SHIFT),
187 GPIO2A4_EMMC_CLKOUT = (2 << GPIO2A4_SHIFT),
188
189 GPIO2A3_SHIFT = 6,
190 GPIO2A3_MASK = GENMASK(GPIO2A3_SHIFT + 1, GPIO2A3_SHIFT),
191 GPIO2A3_GPIO = 0,
192 GPIO2A3_FLASH_CSN3 = (1 << GPIO2A3_SHIFT),
193 GPIO2A3_EMMC_RSTNOUT = (2 << GPIO2A3_SHIFT),
194
195 GPIO2A2_SHIFT = 4,
196 GPIO2A2_MASK = GENMASK(GPIO2A2_SHIFT + 1, GPIO2A2_SHIFT),
197 GPIO2A2_GPIO = 0,
198 GPIO2A2_FLASH_CSN2 = (1 << GPIO2A2_SHIFT),
199
200 GPIO2A1_SHIFT = 2,
201 GPIO2A1_MASK = GENMASK(GPIO2A1_SHIFT + 1, GPIO2A1_SHIFT),
202 GPIO2A1_GPIO = 0,
203 GPIO2A1_FLASH_CSN1 = (1 << GPIO2A1_SHIFT),
204
205 GPIO2A0_SHIFT = 0,
206 GPIO2A0_MASK = GENMASK(GPIO2A0_SHIFT + 1, GPIO2A0_SHIFT),
207 GPIO2A0_GPIO = 0,
208 GPIO2A0_FLASH_CSN0 = (1 << GPIO2A0_SHIFT),
209 };
210
211 /*GRF_GPIO2B_IOMUX*/
212 enum {
213 GPIO2B3_SHIFT = 6,
214 GPIO2B3_MASK = GENMASK(GPIO2B3_SHIFT + 1, GPIO2B3_SHIFT),
215 GPIO2B3_GPIO = 0,
216 GPIO2B3_SDMMC0_DTECTN = (1 << GPIO2B3_SHIFT),
217
218 GPIO2B2_SHIFT = 4,
219 GPIO2B2_MASK = GENMASK(GPIO2B2_SHIFT + 1, GPIO2B2_SHIFT),
220 GPIO2B2_GPIO = 0,
221 GPIO2B2_SDMMC0_CMD = (1 << GPIO2B2_SHIFT),
222
223 GPIO2B1_SHIFT = 2,
224 GPIO2B1_MASK = GENMASK(GPIO2B1_SHIFT + 1, GPIO2B1_SHIFT),
225 GPIO2B1_GPIO = 0,
226 GPIO2B1_SDMMC0_CLKOUT = (1 << GPIO2B1_SHIFT),
227
228 GPIO2B0_SHIFT = 0,
229 GPIO2B0_MASK = GENMASK(GPIO2B0_SHIFT + 1, GPIO2B0_SHIFT),
230 GPIO2B0_GPIO = 0,
231 GPIO2B0_SDMMC0_D3 = (1 << GPIO2B0_SHIFT),
232 };
233
234 /*GRF_GPIO2D_IOMUX*/
235 enum {
236 GPIO2D7_SHIFT = 14,
237 GPIO2D7_MASK = GENMASK(GPIO2D7_SHIFT + 1, GPIO2D7_SHIFT),
238 GPIO2D7_GPIO = 0,
239 GPIO2D7_SDIO0_D3 = (1 << GPIO2D7_SHIFT),
240
241 GPIO2D6_SHIFT = 12,
242 GPIO2D6_MASK = GENMASK(GPIO2D6_SHIFT + 1, GPIO2D6_SHIFT),
243 GPIO2D6_GPIO = 0,
244 GPIO2D6_SDIO0_D2 = (1 << GPIO2D6_SHIFT),
245
246 GPIO2D5_SHIFT = 10,
247 GPIO2D5_MASK = GENMASK(GPIO2D5_SHIFT + 1, GPIO2D5_SHIFT),
248 GPIO2D5_GPIO = 0,
249 GPIO2D5_SDIO0_D1 = (1 << GPIO2D5_SHIFT),
250
251 GPIO2D4_SHIFT = 8,
252 GPIO2D4_MASK = GENMASK(GPIO2D4_SHIFT + 1, GPIO2D4_SHIFT),
253 GPIO2D4_GPIO = 0,
254 GPIO2D4_SDIO0_D0 = (1 << GPIO2D4_SHIFT),
255
256 GPIO2D3_SHIFT = 6,
257 GPIO2D3_MASK = GENMASK(GPIO2D3_SHIFT + 1, GPIO2D3_SHIFT),
258 GPIO2D3_GPIO = 0,
259 GPIO2D3_UART0_RTS0 = (1 << GPIO2D3_SHIFT),
260
261 GPIO2D2_SHIFT = 4,
262 GPIO2D2_MASK = GENMASK(GPIO2D2_SHIFT + 1, GPIO2D2_SHIFT),
263 GPIO2D2_GPIO = 0,
264 GPIO2D2_UART0_CTS0 = (1 << GPIO2D2_SHIFT),
265
266 GPIO2D1_SHIFT = 2,
267 GPIO2D1_MASK = GENMASK(GPIO2D1_SHIFT + 1, GPIO2D1_SHIFT),
268 GPIO2D1_GPIO = 0,
269 GPIO2D1_UART0_SOUT = (1 << GPIO2D1_SHIFT),
270
271 GPIO2D0_SHIFT = 0,
272 GPIO2D0_MASK = GENMASK(GPIO2D0_SHIFT + 1, GPIO2D0_SHIFT),
273 GPIO2D0_GPIO = 0,
274 GPIO2D0_UART0_SIN = (1 << GPIO2D0_SHIFT),
275 };
276
277 /* GRF_GPIO1B_IOMUX */
278 enum {
279 GPIO1B7_SHIFT = 14,
280 GPIO1B7_MASK = GENMASK(GPIO1B7_SHIFT + 1, GPIO1B7_SHIFT),
281 GPIO1B7_GPIO = 0,
282 GPIO1B7_SPI1_CSN0 = (2 << GPIO1B7_SHIFT),
283
284 GPIO1B6_SHIFT = 12,
285 GPIO1B6_MASK = GENMASK(GPIO1B6_SHIFT + 1, GPIO1B6_SHIFT),
286 GPIO1B6_GPIO = 0,
287 GPIO1B6_SPI1_CLK = (2 << GPIO1B6_SHIFT),
288 };
289
290 /* GRF_GPIO1C_IOMUX */
291 enum {
292 GPIO1C7_SHIFT = 14,
293 GPIO1C7_MASK = GENMASK(GPIO1C7_SHIFT + 1, GPIO1C7_SHIFT),
294 GPIO1C7_GPIO = 0,
295 GPIO1C7_EMMC_DATA5 = (2 << GPIO1C7_SHIFT),
296 GPIO1C7_SPI0_TXD = (3 << GPIO1C7_SHIFT),
297
298 GPIO1C6_SHIFT = 12,
299 GPIO1C6_MASK = GENMASK(GPIO1C6_SHIFT + 1, GPIO1C6_SHIFT),
300 GPIO1C6_GPIO = 0,
301 GPIO1C6_EMMC_DATA4 = (2 << GPIO1C6_SHIFT),
302 GPIO1C6_SPI0_RXD = (3 << GPIO1C6_SHIFT),
303
304 GPIO1C5_SHIFT = 10,
305 GPIO1C5_MASK = GENMASK(GPIO1C5_SHIFT + 1, GPIO1C5_SHIFT),
306 GPIO1C5_GPIO = 0,
307 GPIO1C5_EMMC_DATA3 = (2 << GPIO1C5_SHIFT),
308
309 GPIO1C4_SHIFT = 8,
310 GPIO1C4_MASK = GENMASK(GPIO1C4_SHIFT + 1, GPIO1C4_SHIFT),
311 GPIO1C4_GPIO = 0,
312 GPIO1C4_EMMC_DATA2 = (2 << GPIO1C4_SHIFT),
313
314 GPIO1C3_SHIFT = 6,
315 GPIO1C3_MASK = GENMASK(GPIO1C3_SHIFT + 1, GPIO1C3_SHIFT),
316 GPIO1C3_GPIO = 0,
317 GPIO1C3_EMMC_DATA1 = (2 << GPIO1C3_SHIFT),
318
319 GPIO1C2_SHIFT = 4,
320 GPIO1C2_MASK = GENMASK(GPIO1C2_SHIFT + 1, GPIO1C2_SHIFT),
321 GPIO1C2_GPIO = 0,
322 GPIO1C2_EMMC_DATA0 = (2 << GPIO1C2_SHIFT),
323
324 GPIO1C1_SHIFT = 2,
325 GPIO1C1_MASK = GENMASK(GPIO1C1_SHIFT + 1, GPIO1C1_SHIFT),
326 GPIO1C1_GPIO = 0,
327 GPIO1C1_SPI1_RXD = (2 << GPIO1C1_SHIFT),
328
329 GPIO1C0_SHIFT = 0,
330 GPIO1C0_MASK = GENMASK(GPIO1C0_SHIFT + 1, GPIO1C0_SHIFT),
331 GPIO1C0_GPIO = 0,
332 GPIO1C0_SPI1_TXD = (2 << GPIO1C0_SHIFT),
333 };
334
335 /* GRF_GPIO1D_IOMUX*/
336 enum {
337 GPIO1D5_SHIFT = 10,
338 GPIO1D5_MASK = GENMASK(GPIO1D5_SHIFT + 1, GPIO1D5_SHIFT),
339 GPIO1D5_GPIO = 0,
340 GPIO1D5_SPI0_CLK = (2 << GPIO1D5_SHIFT),
341
342 GPIO1D3_SHIFT = 6,
343 GPIO1D3_MASK = GENMASK(GPIO1D3_SHIFT + 1, GPIO1D3_SHIFT),
344 GPIO1D3_GPIO = 0,
345 GPIO1D3_EMMC_PWREN = (2 << GPIO1D3_SHIFT),
346
347 GPIO1D2_SHIFT = 4,
348 GPIO1D2_MASK = GENMASK(GPIO1D2_SHIFT + 1, GPIO1D2_SHIFT),
349 GPIO1D2_GPIO = 0,
350 GPIO1D2_EMMC_CMD = (2 << GPIO1D2_SHIFT),
351
352 GPIO1D1_SHIFT = 2,
353 GPIO1D1_MASK = GENMASK(GPIO1D1_SHIFT + 1, GPIO1D1_SHIFT),
354 GPIO1D1_GPIO = 0,
355 GPIO1D1_EMMC_DATA7 = (2 << GPIO1D1_SHIFT),
356 GPIO1D1_SPI0_CSN1 = (3 << GPIO1D1_SHIFT),
357
358 GPIO1D0_SHIFT = 0,
359 GPIO1D0_MASK = GENMASK(GPIO1D0_SHIFT + 1, GPIO1D0_SHIFT),
360 GPIO1D0_GPIO = 0,
361 GPIO1D0_EMMC_DATA6 = (2 << GPIO1D0_SHIFT),
362 GPIO1D0_SPI0_CSN0 = (3 << GPIO1D0_SHIFT),
363 };
364
365
366 /*GRF_GPIO3B_IOMUX*/
367 enum {
368 GPIO3B7_SHIFT = 14,
369 GPIO3B7_MASK = GENMASK(GPIO3B7_SHIFT + 1, GPIO3B7_SHIFT),
370 GPIO3B7_GPIO = 0,
371 GPIO3B7_MAC_RXD0 = (1 << GPIO3B7_SHIFT),
372
373 GPIO3B6_SHIFT = 12,
374 GPIO3B6_MASK = GENMASK(GPIO3B6_SHIFT + 1, GPIO3B6_SHIFT),
375 GPIO3B6_GPIO = 0,
376 GPIO3B6_MAC_TXD3 = (1 << GPIO3B6_SHIFT),
377
378 GPIO3B5_SHIFT = 10,
379 GPIO3B5_MASK = GENMASK(GPIO3B5_SHIFT + 1, GPIO3B5_SHIFT),
380 GPIO3B5_GPIO = 0,
381 GPIO3B5_MAC_TXEN = (1 << GPIO3B5_SHIFT),
382
383 GPIO3B4_SHIFT = 8,
384 GPIO3B4_MASK = GENMASK(GPIO3B4_SHIFT + 1, GPIO3B4_SHIFT),
385 GPIO3B4_GPIO = 0,
386 GPIO3B4_MAC_COL = (1 << GPIO3B4_SHIFT),
387
388 GPIO3B3_SHIFT = 6,
389 GPIO3B3_MASK = GENMASK(GPIO3B3_SHIFT + 1, GPIO3B3_SHIFT),
390 GPIO3B3_GPIO = 0,
391 GPIO3B3_MAC_CRS = (1 << GPIO3B3_SHIFT),
392
393 GPIO3B2_SHIFT = 4,
394 GPIO3B2_MASK = GENMASK(GPIO3B2_SHIFT + 1, GPIO3B2_SHIFT),
395 GPIO3B2_GPIO = 0,
396 GPIO3B2_MAC_TXD2 = (1 << GPIO3B2_SHIFT),
397
398 GPIO3B1_SHIFT = 2,
399 GPIO3B1_MASK = GENMASK(GPIO3B1_SHIFT + 1, GPIO3B1_SHIFT),
400 GPIO3B1_GPIO = 0,
401 GPIO3B1_MAC_TXD1 = (1 << GPIO3B1_SHIFT),
402
403 GPIO3B0_SHIFT = 0,
404 GPIO3B0_MASK = GENMASK(GPIO3B0_SHIFT + 1, GPIO3B0_SHIFT),
405 GPIO3B0_GPIO = 0,
406 GPIO3B0_MAC_TXD0 = (1 << GPIO3B0_SHIFT),
407 GPIO3B0_PWM0 = (2 << GPIO3B0_SHIFT),
408 };
409
410 /*GRF_GPIO3C_IOMUX*/
411 enum {
412 GPIO3C6_SHIFT = 12,
413 GPIO3C6_MASK = GENMASK(GPIO3C6_SHIFT + 1, GPIO3C6_SHIFT),
414 GPIO3C6_GPIO = 0,
415 GPIO3C6_MAC_CLK = (1 << GPIO3C6_SHIFT),
416
417 GPIO3C5_SHIFT = 10,
418 GPIO3C5_MASK = GENMASK(GPIO3C5_SHIFT + 1, GPIO3C5_SHIFT),
419 GPIO3C5_GPIO = 0,
420 GPIO3C5_MAC_RXEN = (1 << GPIO3C5_SHIFT),
421
422 GPIO3C4_SHIFT = 8,
423 GPIO3C4_MASK = GENMASK(GPIO3C4_SHIFT + 1, GPIO3C4_SHIFT),
424 GPIO3C4_GPIO = 0,
425 GPIO3C4_MAC_RXDV = (1 << GPIO3C4_SHIFT),
426
427 GPIO3C3_SHIFT = 6,
428 GPIO3C3_MASK = GENMASK(GPIO3C3_SHIFT + 1, GPIO3C3_SHIFT),
429 GPIO3C3_GPIO = 0,
430 GPIO3C3_MAC_MDC = (1 << GPIO3C3_SHIFT),
431
432 GPIO3C2_SHIFT = 4,
433 GPIO3C2_MASK = GENMASK(GPIO3C2_SHIFT + 1, GPIO3C2_SHIFT),
434 GPIO3C2_GPIO = 0,
435 GPIO3C2_MAC_RXD3 = (1 << GPIO3C2_SHIFT),
436
437 GPIO3C1_SHIFT = 2,
438 GPIO3C1_MASK = GENMASK(GPIO3C1_SHIFT + 1, GPIO3C1_SHIFT),
439 GPIO3C1_GPIO = 0,
440 GPIO3C1_MAC_RXD2 = (1 << GPIO3C1_SHIFT),
441
442 GPIO3C0_SHIFT = 0,
443 GPIO3C0_MASK = GENMASK(GPIO3C0_SHIFT + 1, GPIO3C0_SHIFT),
444 GPIO3C0_GPIO = 0,
445 GPIO3C0_MAC_RXD1 = (1 << GPIO3C0_SHIFT),
446 };
447
448 /*GRF_GPIO3D_IOMUX*/
449 enum {
450 GPIO3D4_SHIFT = 8,
451 GPIO3D4_MASK = GENMASK(GPIO3D4_SHIFT + 1, GPIO3D4_SHIFT),
452 GPIO3D4_GPIO = 0,
453 GPIO3D4_MAC_TXCLK = (1 << GPIO3D4_SHIFT),
454 GPIO3D4_SPI1_CNS1 = (2 << GPIO3D4_SHIFT),
455
456 GPIO3D1_SHIFT = 2,
457 GPIO3D1_MASK = GENMASK(GPIO3D1_SHIFT + 1, GPIO3D1_SHIFT),
458 GPIO3D1_GPIO = 0,
459 GPIO3D1_MAC_RXCLK = (1 << GPIO3D1_SHIFT),
460
461 GPIO3D0_SHIFT = 0,
462 GPIO3D0_MASK = GENMASK(GPIO3D0_SHIFT + 1, GPIO3D0_SHIFT),
463 GPIO3D0_GPIO = 0,
464 GPIO3D0_MAC_MDIO = (1 << GPIO3D0_SHIFT),
465 };
466
467 struct rk3368_pinctrl_priv {
468 struct rk3368_grf *grf;
469 struct rk3368_pmu_grf *pmugrf;
470 };
471
472 static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,
473 int uart_id)
474 {
475 struct rk3368_grf *grf = priv->grf;
476 struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
477
478 switch (uart_id) {
479 case PERIPH_ID_UART2:
480 rk_clrsetreg(&grf->gpio2a_iomux,
481 GPIO2A6_MASK | GPIO2A5_MASK,
482 GPIO2A6_UART2_SIN | GPIO2A5_UART2_SOUT);
483 break;
484 case PERIPH_ID_UART0:
485 break;
486 case PERIPH_ID_UART1:
487 break;
488 case PERIPH_ID_UART3:
489 break;
490 case PERIPH_ID_UART4:
491 rk_clrsetreg(&pmugrf->gpio0d_iomux,
492 GPIO0D0_MASK | GPIO0D1_MASK |
493 GPIO0D2_MASK | GPIO0D3_MASK,
494 GPIO0D0_GPIO | GPIO0D1_GPIO |
495 GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
496 break;
497 default:
498 debug("uart id = %d iomux error!\n", uart_id);
499 break;
500 }
501 }
502
503 static void pinctrl_rk3368_spi_config(struct rk3368_pinctrl_priv *priv,
504 int spi_id)
505 {
506 struct rk3368_grf *grf = priv->grf;
507 struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
508
509 switch (spi_id) {
510 case PERIPH_ID_SPI0:
511 /*
512 * eMMC can only be connected with 4 bits, when SPI0 is used.
513 * This is all-or-nothing, so we assume that if someone asks us
514 * to configure SPI0, that their eMMC interface is unused or
515 * configured appropriately.
516 */
517 rk_clrsetreg(&grf->gpio1d_iomux,
518 GPIO1D0_MASK | GPIO1D1_MASK |
519 GPIO1D5_MASK,
520 GPIO1D0_SPI0_CSN0 | GPIO1D1_SPI0_CSN1 |
521 GPIO1D5_SPI0_CLK);
522 rk_clrsetreg(&grf->gpio1c_iomux,
523 GPIO1C6_MASK | GPIO1C7_MASK,
524 GPIO1C6_SPI0_RXD | GPIO1C7_SPI0_TXD);
525 break;
526 case PERIPH_ID_SPI1:
527 /*
528 * We don't implement support for configuring SPI1_CSN#1, as it
529 * conflicts with the GMAC (MAC TX clk-out).
530 */
531 rk_clrsetreg(&grf->gpio1b_iomux,
532 GPIO1B6_MASK | GPIO1B7_MASK,
533 GPIO1B6_SPI1_CLK | GPIO1B7_SPI1_CSN0);
534 rk_clrsetreg(&grf->gpio1c_iomux,
535 GPIO1C0_MASK | GPIO1C1_MASK,
536 GPIO1C0_SPI1_TXD | GPIO1C1_SPI1_RXD);
537 break;
538 case PERIPH_ID_SPI2:
539 rk_clrsetreg(&pmugrf->gpio0b_iomux,
540 GPIO0B2_MASK | GPIO0B3_MASK |
541 GPIO0B4_MASK | GPIO0B5_MASK,
542 GPIO0B2_SPI2_RXD | GPIO0B3_SPI2_TXD |
543 GPIO0B4_SPI2_CLK | GPIO0B5_SPI2_CSN0);
544 break;
545 default:
546 debug("%s: spi id = %d iomux error!\n", __func__, spi_id);
547 break;
548 }
549 }
550
551 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
552 static void pinctrl_rk3368_gmac_config(struct rk3368_grf *grf, int gmac_id)
553 {
554 rk_clrsetreg(&grf->gpio3b_iomux,
555 GPIO3B0_MASK | GPIO3B1_MASK |
556 GPIO3B2_MASK | GPIO3B5_MASK |
557 GPIO3B6_MASK | GPIO3B7_MASK,
558 GPIO3B0_MAC_TXD0 | GPIO3B1_MAC_TXD1 |
559 GPIO3B2_MAC_TXD2 | GPIO3B5_MAC_TXEN |
560 GPIO3B6_MAC_TXD3 | GPIO3B7_MAC_RXD0);
561 rk_clrsetreg(&grf->gpio3c_iomux,
562 GPIO3C0_MASK | GPIO3C1_MASK |
563 GPIO3C2_MASK | GPIO3C3_MASK |
564 GPIO3C4_MASK | GPIO3C5_MASK |
565 GPIO3C6_MASK,
566 GPIO3C0_MAC_RXD1 | GPIO3C1_MAC_RXD2 |
567 GPIO3C2_MAC_RXD3 | GPIO3C3_MAC_MDC |
568 GPIO3C4_MAC_RXDV | GPIO3C5_MAC_RXEN |
569 GPIO3C6_MAC_CLK);
570 rk_clrsetreg(&grf->gpio3d_iomux,
571 GPIO3D0_MASK | GPIO3D1_MASK |
572 GPIO3D4_MASK,
573 GPIO3D0_MAC_MDIO | GPIO3D1_MAC_RXCLK |
574 GPIO3D4_MAC_TXCLK);
575 }
576 #endif
577
578 static void pinctrl_rk3368_sdmmc_config(struct rk3368_grf *grf, int mmc_id)
579 {
580 switch (mmc_id) {
581 case PERIPH_ID_EMMC:
582 debug("mmc id = %d setting registers!\n", mmc_id);
583 rk_clrsetreg(&grf->gpio1c_iomux,
584 GPIO1C2_MASK | GPIO1C3_MASK |
585 GPIO1C4_MASK | GPIO1C5_MASK |
586 GPIO1C6_MASK | GPIO1C7_MASK,
587 GPIO1C2_EMMC_DATA0 |
588 GPIO1C3_EMMC_DATA1 |
589 GPIO1C4_EMMC_DATA2 |
590 GPIO1C5_EMMC_DATA3 |
591 GPIO1C6_EMMC_DATA4 |
592 GPIO1C7_EMMC_DATA5);
593 rk_clrsetreg(&grf->gpio1d_iomux,
594 GPIO1D0_MASK | GPIO1D1_MASK |
595 GPIO1D2_MASK | GPIO1D3_MASK,
596 GPIO1D0_EMMC_DATA6 |
597 GPIO1D1_EMMC_DATA7 |
598 GPIO1D2_EMMC_CMD |
599 GPIO1D3_EMMC_PWREN);
600 rk_clrsetreg(&grf->gpio2a_iomux,
601 GPIO2A3_MASK | GPIO2A4_MASK,
602 GPIO2A3_EMMC_RSTNOUT |
603 GPIO2A4_EMMC_CLKOUT);
604 break;
605 case PERIPH_ID_SDCARD:
606 debug("mmc id = %d setting registers!\n", mmc_id);
607 rk_clrsetreg(&grf->gpio2a_iomux,
608 GPIO2A5_MASK | GPIO2A7_MASK |
609 GPIO2A7_MASK,
610 GPIO2A5_SDMMC0_D0 | GPIO2A6_SDMMC0_D1 |
611 GPIO2A7_SDMMC0_D2);
612 rk_clrsetreg(&grf->gpio2b_iomux,
613 GPIO2B0_MASK | GPIO2B1_MASK |
614 GPIO2B2_MASK | GPIO2B3_MASK,
615 GPIO2B0_SDMMC0_D3 | GPIO2B1_SDMMC0_CLKOUT |
616 GPIO2B2_SDMMC0_CMD | GPIO2B3_SDMMC0_DTECTN);
617 break;
618 default:
619 debug("mmc id = %d iomux error!\n", mmc_id);
620 break;
621 }
622 }
623
624 static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)
625 {
626 struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
627
628 debug("%s: func=%d, flags=%x\n", __func__, func, flags);
629 switch (func) {
630 case PERIPH_ID_UART0:
631 case PERIPH_ID_UART1:
632 case PERIPH_ID_UART2:
633 case PERIPH_ID_UART3:
634 case PERIPH_ID_UART4:
635 pinctrl_rk3368_uart_config(priv, func);
636 break;
637 case PERIPH_ID_SPI0:
638 case PERIPH_ID_SPI1:
639 case PERIPH_ID_SPI2:
640 pinctrl_rk3368_spi_config(priv, func);
641 break;
642 case PERIPH_ID_EMMC:
643 case PERIPH_ID_SDCARD:
644 pinctrl_rk3368_sdmmc_config(priv->grf, func);
645 break;
646 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
647 case PERIPH_ID_GMAC:
648 pinctrl_rk3368_gmac_config(priv->grf, func);
649 break;
650 #endif
651 default:
652 return -EINVAL;
653 }
654
655 return 0;
656 }
657
658 static int rk3368_pinctrl_get_periph_id(struct udevice *dev,
659 struct udevice *periph)
660 {
661 u32 cell[3];
662 int ret;
663
664 ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
665 if (ret < 0)
666 return -EINVAL;
667
668 switch (cell[1]) {
669 case 59:
670 return PERIPH_ID_UART4;
671 case 58:
672 return PERIPH_ID_UART3;
673 case 57:
674 return PERIPH_ID_UART2;
675 case 56:
676 return PERIPH_ID_UART1;
677 case 55:
678 return PERIPH_ID_UART0;
679 case 44:
680 return PERIPH_ID_SPI0;
681 case 45:
682 return PERIPH_ID_SPI1;
683 case 41:
684 return PERIPH_ID_SPI2;
685 case 35:
686 return PERIPH_ID_EMMC;
687 case 32:
688 return PERIPH_ID_SDCARD;
689 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
690 case 27:
691 return PERIPH_ID_GMAC;
692 #endif
693 }
694
695 return -ENOENT;
696 }
697
698 static int rk3368_pinctrl_set_state_simple(struct udevice *dev,
699 struct udevice *periph)
700 {
701 int func;
702
703 func = rk3368_pinctrl_get_periph_id(dev, periph);
704 if (func < 0)
705 return func;
706
707 return rk3368_pinctrl_request(dev, func, 0);
708 }
709
710 static struct pinctrl_ops rk3368_pinctrl_ops = {
711 .set_state_simple = rk3368_pinctrl_set_state_simple,
712 .request = rk3368_pinctrl_request,
713 .get_periph_id = rk3368_pinctrl_get_periph_id,
714 };
715
716 static int rk3368_pinctrl_probe(struct udevice *dev)
717 {
718 struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
719 int ret = 0;
720
721 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
722 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
723
724 debug("%s: grf=%p pmugrf:%p\n", __func__, priv->grf, priv->pmugrf);
725
726 return ret;
727 }
728
729 static const struct udevice_id rk3368_pinctrl_ids[] = {
730 { .compatible = "rockchip,rk3368-pinctrl" },
731 { }
732 };
733
734 U_BOOT_DRIVER(pinctrl_rk3368) = {
735 .name = "rockchip_rk3368_pinctrl",
736 .id = UCLASS_PINCTRL,
737 .of_match = rk3368_pinctrl_ids,
738 .priv_auto_alloc_size = sizeof(struct rk3368_pinctrl_priv),
739 .ops = &rk3368_pinctrl_ops,
740 .bind = dm_scan_fdt_dev,
741 .probe = rk3368_pinctrl_probe,
742 };
"Das U-Boot" Source Tree