2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/grf_rk3399.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/periph.h>
15 #include <asm/arch/clock.h>
16 #include <dm/pinctrl.h>
18 DECLARE_GLOBAL_DATA_PTR
;
20 struct rk3399_pinctrl_priv
{
21 struct rk3399_grf_regs
*grf
;
22 struct rk3399_pmugrf_regs
*pmugrf
;
26 /* GRF_GPIO2B_IOMUX */
27 GRF_GPIO2B1_SEL_SHIFT
= 0,
28 GRF_GPIO2B1_SEL_MASK
= 3 << GRF_GPIO2B1_SEL_SHIFT
,
30 GRF_GPIO2B2_SEL_SHIFT
= 2,
31 GRF_GPIO2B2_SEL_MASK
= 3 << GRF_GPIO2B2_SEL_SHIFT
,
33 GRF_GPIO2B3_SEL_SHIFT
= 6,
34 GRF_GPIO2B3_SEL_MASK
= 3 << GRF_GPIO2B3_SEL_SHIFT
,
36 GRF_GPIO2B4_SEL_SHIFT
= 8,
37 GRF_GPIO2B4_SEL_MASK
= 3 << GRF_GPIO2B4_SEL_SHIFT
,
40 /* GRF_GPIO3A_IOMUX */
41 GRF_GPIO3A4_SEL_SHIFT
= 8,
42 GRF_GPIO3A4_SEL_MASK
= 3 << GRF_GPIO3A4_SEL_SHIFT
,
43 GRF_SPI0NORCODEC_RXD
= 2,
44 GRF_GPIO3A5_SEL_SHIFT
= 10,
45 GRF_GPIO3A5_SEL_MASK
= 3 << GRF_GPIO3A5_SEL_SHIFT
,
46 GRF_SPI0NORCODEC_TXD
= 2,
47 GRF_GPIO3A6_SEL_SHIFT
= 12,
48 GRF_GPIO3A6_SEL_MASK
= 3 << GRF_GPIO3A6_SEL_SHIFT
,
49 GRF_SPI0NORCODEC_CLK
= 2,
50 GRF_GPIO3A7_SEL_SHIFT
= 14,
51 GRF_GPIO3A7_SEL_MASK
= 3 << GRF_GPIO3A7_SEL_SHIFT
,
52 GRF_SPI0NORCODEC_CSN0
= 2,
54 /* GRF_GPIO3B_IOMUX */
55 GRF_GPIO3B0_SEL_SHIFT
= 0,
56 GRF_GPIO3B0_SEL_MASK
= 3 << GRF_GPIO3B0_SEL_SHIFT
,
57 GRF_SPI0NORCODEC_CSN1
= 2,
59 /* GRF_GPIO4B_IOMUX */
60 GRF_GPIO4B0_SEL_SHIFT
= 0,
61 GRF_GPIO4B0_SEL_MASK
= 3 << GRF_GPIO4B0_SEL_SHIFT
,
63 GRF_UART2DBGA_SIN
= 2,
64 GRF_GPIO4B1_SEL_SHIFT
= 2,
65 GRF_GPIO4B1_SEL_MASK
= 3 << GRF_GPIO4B1_SEL_SHIFT
,
67 GRF_UART2DBGA_SOUT
= 2,
68 GRF_GPIO4B2_SEL_SHIFT
= 4,
69 GRF_GPIO4B2_SEL_MASK
= 3 << GRF_GPIO4B2_SEL_SHIFT
,
71 GRF_GPIO4B3_SEL_SHIFT
= 6,
72 GRF_GPIO4B3_SEL_MASK
= 3 << GRF_GPIO4B3_SEL_SHIFT
,
74 GRF_GPIO4B4_SEL_SHIFT
= 8,
75 GRF_GPIO4B4_SEL_MASK
= 3 << GRF_GPIO4B4_SEL_SHIFT
,
77 GRF_GPIO4B5_SEL_SHIFT
= 10,
78 GRF_GPIO4B5_SEL_MASK
= 3 << GRF_GPIO4B5_SEL_SHIFT
,
81 /* GRF_GPIO4C_IOMUX */
82 GRF_GPIO4C2_SEL_SHIFT
= 4,
83 GRF_GPIO4C2_SEL_MASK
= 3 << GRF_GPIO4C2_SEL_SHIFT
,
85 GRF_GPIO4C3_SEL_SHIFT
= 6,
86 GRF_GPIO4C3_SEL_MASK
= 3 << GRF_GPIO4C3_SEL_SHIFT
,
87 GRF_UART2DGBC_SIN
= 1,
88 GRF_GPIO4C4_SEL_SHIFT
= 8,
89 GRF_GPIO4C4_SEL_MASK
= 3 << GRF_GPIO4C4_SEL_SHIFT
,
90 GRF_UART2DBGC_SOUT
= 1,
91 GRF_GPIO4C6_SEL_SHIFT
= 12,
92 GRF_GPIO4C6_SEL_MASK
= 3 << GRF_GPIO4C6_SEL_SHIFT
,
95 /* PMUGRF_GPIO0A_IOMUX */
96 PMUGRF_GPIO0A6_SEL_SHIFT
= 12,
97 PMUGRF_GPIO0A6_SEL_MASK
= 3 << PMUGRF_GPIO0A6_SEL_SHIFT
,
100 /* PMUGRF_GPIO1A_IOMUX */
101 PMUGRF_GPIO1A7_SEL_SHIFT
= 14,
102 PMUGRF_GPIO1A7_SEL_MASK
= 3 << PMUGRF_GPIO1A7_SEL_SHIFT
,
103 PMUGRF_SPI1EC_RXD
= 2,
105 /* PMUGRF_GPIO1B_IOMUX */
106 PMUGRF_GPIO1B0_SEL_SHIFT
= 0,
107 PMUGRF_GPIO1B0_SEL_MASK
= 3 << PMUGRF_GPIO1B0_SEL_SHIFT
,
108 PMUGRF_SPI1EC_TXD
= 2,
109 PMUGRF_GPIO1B1_SEL_SHIFT
= 2,
110 PMUGRF_GPIO1B1_SEL_MASK
= 3 << PMUGRF_GPIO1B1_SEL_SHIFT
,
111 PMUGRF_SPI1EC_CLK
= 2,
112 PMUGRF_GPIO1B2_SEL_SHIFT
= 4,
113 PMUGRF_GPIO1B2_SEL_MASK
= 3 << PMUGRF_GPIO1B2_SEL_SHIFT
,
114 PMUGRF_SPI1EC_CSN0
= 2,
115 PMUGRF_GPIO1B6_SEL_SHIFT
= 12,
116 PMUGRF_GPIO1B6_SEL_MASK
= 3 << PMUGRF_GPIO1B6_SEL_SHIFT
,
118 PMUGRF_GPIO1B7_SEL_SHIFT
= 14,
119 PMUGRF_GPIO1B7_SEL_MASK
= 3 << PMUGRF_GPIO1B7_SEL_SHIFT
,
120 PMUGRF_I2C0PMU_SDA
= 2,
122 /* PMUGRF_GPIO1C_IOMUX */
123 PMUGRF_GPIO1C0_SEL_SHIFT
= 0,
124 PMUGRF_GPIO1C0_SEL_MASK
= 3 << PMUGRF_GPIO1C0_SEL_SHIFT
,
125 PMUGRF_I2C0PMU_SCL
= 2,
126 PMUGRF_GPIO1C3_SEL_SHIFT
= 6,
127 PMUGRF_GPIO1C3_SEL_MASK
= 3 << PMUGRF_GPIO1C3_SEL_SHIFT
,
131 static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs
*grf
,
132 struct rk3399_pmugrf_regs
*pmugrf
, int pwm_id
)
136 rk_clrsetreg(&grf
->gpio4c_iomux
,
137 GRF_GPIO4C2_SEL_MASK
,
138 GRF_PWM_0
<< GRF_GPIO4C2_SEL_SHIFT
);
141 rk_clrsetreg(&grf
->gpio4c_iomux
,
142 GRF_GPIO4C6_SEL_MASK
,
143 GRF_PWM_1
<< GRF_GPIO4C6_SEL_SHIFT
);
146 rk_clrsetreg(&pmugrf
->gpio1c_iomux
,
147 PMUGRF_GPIO1C3_SEL_MASK
,
148 PMUGRF_PWM_2
<< PMUGRF_GPIO1C3_SEL_SHIFT
);
151 if (readl(&pmugrf
->soc_con0
) & (1 << 5))
152 rk_clrsetreg(&pmugrf
->gpio1b_iomux
,
153 PMUGRF_GPIO1B6_SEL_MASK
,
154 PMUGRF_PWM_3B
<< PMUGRF_GPIO1B6_SEL_SHIFT
);
156 rk_clrsetreg(&pmugrf
->gpio0a_iomux
,
157 PMUGRF_GPIO0A6_SEL_MASK
,
158 PMUGRF_PWM_3A
<< PMUGRF_GPIO0A6_SEL_SHIFT
);
161 debug("pwm id = %d iomux error!\n", pwm_id
);
166 static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs
*grf
,
167 struct rk3399_pmugrf_regs
*pmugrf
,
172 rk_clrsetreg(&pmugrf
->gpio1b_iomux
,
173 PMUGRF_GPIO1B7_SEL_MASK
,
174 PMUGRF_I2C0PMU_SDA
<< PMUGRF_GPIO1B7_SEL_SHIFT
);
175 rk_clrsetreg(&pmugrf
->gpio1c_iomux
,
176 PMUGRF_GPIO1C0_SEL_MASK
,
177 PMUGRF_I2C0PMU_SCL
<< PMUGRF_GPIO1C0_SEL_SHIFT
);
185 debug("i2c id = %d iomux error!\n", i2c_id
);
190 static void pinctrl_rk3399_lcdc_config(struct rk3399_grf_regs
*grf
, int lcd_id
)
193 case PERIPH_ID_LCDC0
:
196 debug("lcdc id = %d iomux error!\n", lcd_id
);
201 static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs
*grf
,
202 struct rk3399_pmugrf_regs
*pmugrf
,
203 enum periph_id spi_id
, int cs
)
209 rk_clrsetreg(&grf
->gpio3a_iomux
,
210 GRF_GPIO3A7_SEL_MASK
,
211 GRF_SPI0NORCODEC_CSN0
212 << GRF_GPIO3A7_SEL_SHIFT
);
215 rk_clrsetreg(&grf
->gpio3b_iomux
,
216 GRF_GPIO3B0_SEL_MASK
,
217 GRF_SPI0NORCODEC_CSN1
218 << GRF_GPIO3B0_SEL_SHIFT
);
223 rk_clrsetreg(&grf
->gpio3a_iomux
,
224 GRF_GPIO3A4_SEL_MASK
| GRF_GPIO3A5_SEL_SHIFT
225 | GRF_GPIO3A6_SEL_SHIFT
,
226 GRF_SPI0NORCODEC_RXD
<< GRF_GPIO3A4_SEL_SHIFT
227 | GRF_SPI0NORCODEC_RXD
<< GRF_GPIO3A5_SEL_SHIFT
228 | GRF_SPI0NORCODEC_RXD
<< GRF_GPIO3A6_SEL_SHIFT
);
233 rk_clrsetreg(&pmugrf
->gpio1a_iomux
,
234 PMUGRF_GPIO1A7_SEL_MASK
,
235 PMUGRF_SPI1EC_RXD
<< PMUGRF_GPIO1A7_SEL_SHIFT
);
236 rk_clrsetreg(&pmugrf
->gpio1b_iomux
,
237 PMUGRF_GPIO1B0_SEL_MASK
| PMUGRF_GPIO1B1_SEL_MASK
238 | PMUGRF_GPIO1B2_SEL_MASK
,
239 PMUGRF_SPI1EC_TXD
<< PMUGRF_GPIO1B0_SEL_SHIFT
240 | PMUGRF_SPI1EC_CLK
<< PMUGRF_GPIO1B1_SEL_SHIFT
241 | PMUGRF_SPI1EC_CSN0
<< PMUGRF_GPIO1B2_SEL_SHIFT
);
246 rk_clrsetreg(&grf
->gpio2b_iomux
,
247 GRF_GPIO2B1_SEL_MASK
| GRF_GPIO2B2_SEL_MASK
248 | GRF_GPIO2B3_SEL_MASK
| GRF_GPIO2B4_SEL_MASK
,
249 GRF_SPI2TPM_RXD
<< GRF_GPIO2B1_SEL_SHIFT
250 | GRF_SPI2TPM_TXD
<< GRF_GPIO2B2_SEL_SHIFT
251 | GRF_SPI2TPM_CLK
<< GRF_GPIO2B3_SEL_SHIFT
252 | GRF_SPI2TPM_CSN0
<< GRF_GPIO2B4_SEL_SHIFT
);
260 debug("rkspi: periph%d cs=%d not supported", spi_id
, cs
);
264 static void pinctrl_rk3399_uart_config(struct rk3399_grf_regs
*grf
,
265 struct rk3399_pmugrf_regs
*pmugrf
,
269 case PERIPH_ID_UART2
:
270 /* Using channel-C by default */
271 rk_clrsetreg(&grf
->gpio4c_iomux
,
272 GRF_GPIO4C3_SEL_MASK
,
273 GRF_UART2DGBC_SIN
<< GRF_GPIO4C3_SEL_SHIFT
);
274 rk_clrsetreg(&grf
->gpio4c_iomux
,
275 GRF_GPIO4C4_SEL_MASK
,
276 GRF_UART2DBGC_SOUT
<< GRF_GPIO4C4_SEL_SHIFT
);
278 case PERIPH_ID_UART0
:
279 case PERIPH_ID_UART1
:
280 case PERIPH_ID_UART3
:
281 case PERIPH_ID_UART4
:
283 debug("uart id = %d iomux error!\n", uart_id
);
288 static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs
*grf
, int mmc_id
)
293 case PERIPH_ID_SDCARD
:
294 rk_clrsetreg(&grf
->gpio4b_iomux
,
295 GRF_GPIO4B0_SEL_MASK
| GRF_GPIO4B1_SEL_MASK
296 | GRF_GPIO4B2_SEL_MASK
| GRF_GPIO4B3_SEL_MASK
297 | GRF_GPIO4B4_SEL_MASK
| GRF_GPIO4B5_SEL_MASK
,
298 GRF_SDMMC_DATA0
<< GRF_GPIO4B0_SEL_SHIFT
299 | GRF_SDMMC_DATA1
<< GRF_GPIO4B1_SEL_SHIFT
300 | GRF_SDMMC_DATA2
<< GRF_GPIO4B2_SEL_SHIFT
301 | GRF_SDMMC_DATA3
<< GRF_GPIO4B3_SEL_SHIFT
302 | GRF_SDMMC_CLKOUT
<< GRF_GPIO4B4_SEL_SHIFT
303 | GRF_SDMMC_CMD
<< GRF_GPIO4B5_SEL_SHIFT
);
306 debug("mmc id = %d iomux error!\n", mmc_id
);
311 static int rk3399_pinctrl_request(struct udevice
*dev
, int func
, int flags
)
313 struct rk3399_pinctrl_priv
*priv
= dev_get_priv(dev
);
315 debug("%s: func=%x, flags=%x\n", __func__
, func
, flags
);
322 pinctrl_rk3399_pwm_config(priv
->grf
, priv
->pmugrf
, func
);
330 pinctrl_rk3399_i2c_config(priv
->grf
, priv
->pmugrf
, func
);
335 pinctrl_rk3399_spi_config(priv
->grf
, priv
->pmugrf
, func
, flags
);
337 case PERIPH_ID_UART0
:
338 case PERIPH_ID_UART1
:
339 case PERIPH_ID_UART2
:
340 case PERIPH_ID_UART3
:
341 case PERIPH_ID_UART4
:
342 pinctrl_rk3399_uart_config(priv
->grf
, priv
->pmugrf
, func
);
344 case PERIPH_ID_LCDC0
:
345 case PERIPH_ID_LCDC1
:
346 pinctrl_rk3399_lcdc_config(priv
->grf
, func
);
348 case PERIPH_ID_SDMMC0
:
349 case PERIPH_ID_SDMMC1
:
350 pinctrl_rk3399_sdmmc_config(priv
->grf
, func
);
359 static int rk3399_pinctrl_get_periph_id(struct udevice
*dev
,
360 struct udevice
*periph
)
365 ret
= fdtdec_get_int_array(gd
->fdt_blob
, dev_of_offset(periph
),
366 "interrupts", cell
, ARRAY_SIZE(cell
));
372 return PERIPH_ID_SPI0
;
374 return PERIPH_ID_SPI1
;
376 return PERIPH_ID_SPI2
;
378 return PERIPH_ID_I2C0
;
379 case 59: /* Note strange order */
380 return PERIPH_ID_I2C1
;
382 return PERIPH_ID_I2C2
;
384 return PERIPH_ID_I2C3
;
386 return PERIPH_ID_I2C4
;
388 return PERIPH_ID_I2C5
;
390 return PERIPH_ID_SDMMC1
;
396 static int rk3399_pinctrl_set_state_simple(struct udevice
*dev
,
397 struct udevice
*periph
)
401 func
= rk3399_pinctrl_get_periph_id(dev
, periph
);
405 return rk3399_pinctrl_request(dev
, func
, 0);
408 static struct pinctrl_ops rk3399_pinctrl_ops
= {
409 .set_state_simple
= rk3399_pinctrl_set_state_simple
,
410 .request
= rk3399_pinctrl_request
,
411 .get_periph_id
= rk3399_pinctrl_get_periph_id
,
414 static int rk3399_pinctrl_probe(struct udevice
*dev
)
416 struct rk3399_pinctrl_priv
*priv
= dev_get_priv(dev
);
419 priv
->grf
= syscon_get_first_range(ROCKCHIP_SYSCON_GRF
);
420 priv
->pmugrf
= syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF
);
421 debug("%s: grf=%p, pmugrf=%p\n", __func__
, priv
->grf
, priv
->pmugrf
);
426 static const struct udevice_id rk3399_pinctrl_ids
[] = {
427 { .compatible
= "rockchip,rk3399-pinctrl" },
431 U_BOOT_DRIVER(pinctrl_rk3399
) = {
432 .name
= "rockchip_rk3399_pinctrl",
433 .id
= UCLASS_PINCTRL
,
434 .of_match
= rk3399_pinctrl_ids
,
435 .priv_auto_alloc_size
= sizeof(struct rk3399_pinctrl_priv
),
436 .ops
= &rk3399_pinctrl_ops
,
437 .bind
= dm_scan_fdt_dev
,
438 .probe
= rk3399_pinctrl_probe
,