drivers/serial/serial_pl01x.c

   1 /*
   2  * (C) Copyright 2000
   3  * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
   4  *
   5  * (C) Copyright 2004
   6  * ARM Ltd.
   7  * Philippe Robin, <philippe.robin@arm.com>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
  13
  14 #include <common.h>
  15 #include <dm.h>
  16 #include <errno.h>
  17 #include <watchdog.h>
  18 #include <asm/io.h>
  19 #include <serial.h>
  20 #include <serial_pl01x.h>
  21 #include <linux/compiler.h>
  22 #include "serial_pl01x_internal.h"
  23
  24 #ifndef CONFIG_DM_SERIAL
  25
  26 static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
  27 static enum pl01x_type pl01x_type __attribute__ ((section(".data")));
  28 static struct pl01x_regs *base_regs __attribute__ ((section(".data")));
  29 #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32 #endif
  33
  34 static int pl01x_putc(struct pl01x_regs *regs, char c)
  35 {
  36         /* Wait until there is space in the FIFO */
  37         if (readl(&regs->fr) & UART_PL01x_FR_TXFF)
  38                 return -EAGAIN;
  39
  40         /* Send the character */
  41         writel(c, &regs->dr);
  42
  43         return 0;
  44 }
  45
  46 static int pl01x_getc(struct pl01x_regs *regs)
  47 {
  48         unsigned int data;
  49
  50         /* Wait until there is data in the FIFO */
  51         if (readl(&regs->fr) & UART_PL01x_FR_RXFE)
  52                 return -EAGAIN;
  53
  54         data = readl(&regs->dr);
  55
  56         /* Check for an error flag */
  57         if (data & 0xFFFFFF00) {
  58                 /* Clear the error */
  59                 writel(0xFFFFFFFF, &regs->ecr);
  60                 return -1;
  61         }
  62
  63         return (int) data;
  64 }
  65
  66 static int pl01x_tstc(struct pl01x_regs *regs)
  67 {
  68         WATCHDOG_RESET();
  69         return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
  70 }
  71
  72 static int pl01x_generic_serial_init(struct pl01x_regs *regs,
  73                                      enum pl01x_type type)
  74 {
  75         unsigned int lcr;
  76
  77 #ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
  78         if (type == TYPE_PL011) {
  79                 /* Empty RX fifo if necessary */
  80                 if (readl(&regs->pl011_cr) & UART_PL011_CR_UARTEN) {
  81                         while (!(readl(&regs->fr) & UART_PL01x_FR_RXFE))
  82                                 readl(&regs->dr);
  83                 }
  84         }
  85 #endif
  86
  87         /* First, disable everything */
  88         writel(0, &regs->pl010_cr);
  89
  90         /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
  91         lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
  92         writel(lcr, &regs->pl011_lcrh);
  93
  94         switch (type) {
  95         case TYPE_PL010:
  96                 break;
  97         case TYPE_PL011: {
  98 #ifdef CONFIG_PL011_SERIAL_RLCR
  99                 int i;
 100
 101                 /*
 102                  * Program receive line control register after waiting
 103                  * 10 bus cycles.  Delay be writing to readonly register
 104                  * 10 times
 105                  */
 106                 for (i = 0; i < 10; i++)
 107                         writel(lcr, &regs->fr);
 108
 109                 writel(lcr, &regs->pl011_rlcr);
 110                 /* lcrh needs to be set again for change to be effective */
 111                 writel(lcr, &regs->pl011_lcrh);
 112 #endif
 113                 break;
 114         }
 115         default:
 116                 return -EINVAL;
 117         }
 118
 119         return 0;
 120 }
 121
 122 static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
 123                                 int clock, int baudrate)
 124 {
 125         switch (type) {
 126         case TYPE_PL010: {
 127                 unsigned int divisor;
 128
 129                 switch (baudrate) {
 130                 case 9600:
 131                         divisor = UART_PL010_BAUD_9600;
 132                         break;
 133                 case 19200:
 134                         divisor = UART_PL010_BAUD_9600;
 135                         break;
 136                 case 38400:
 137                         divisor = UART_PL010_BAUD_38400;
 138                         break;
 139                 case 57600:
 140                         divisor = UART_PL010_BAUD_57600;
 141                         break;
 142                 case 115200:
 143                         divisor = UART_PL010_BAUD_115200;
 144                         break;
 145                 default:
 146                         divisor = UART_PL010_BAUD_38400;
 147                 }
 148
 149                 writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
 150                 writel(divisor & 0xff, &regs->pl010_lcrl);
 151
 152                 /* Finally, enable the UART */
 153                 writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
 154                 break;
 155         }
 156         case TYPE_PL011: {
 157                 unsigned int temp;
 158                 unsigned int divider;
 159                 unsigned int remainder;
 160                 unsigned int fraction;
 161
 162                 /*
 163                 * Set baud rate
 164                 *
 165                 * IBRD = UART_CLK / (16 * BAUD_RATE)
 166                 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
 167                 *               / (16 * BAUD_RATE))
 168                 */
 169                 temp = 16 * baudrate;
 170                 divider = clock / temp;
 171                 remainder = clock % temp;
 172                 temp = (8 * remainder) / baudrate;
 173                 fraction = (temp >> 1) + (temp & 1);
 174
 175                 writel(divider, &regs->pl011_ibrd);
 176                 writel(fraction, &regs->pl011_fbrd);
 177
 178                 /* Finally, enable the UART */
 179                 writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
 180                        UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);
 181                 break;
 182         }
 183         default:
 184                 return -EINVAL;
 185         }
 186
 187         return 0;
 188 }
 189
 190 #ifndef CONFIG_DM_SERIAL
 191 static void pl01x_serial_init_baud(int baudrate)
 192 {
 193         int clock = 0;
 194
 195 #if defined(CONFIG_PL010_SERIAL)
 196         pl01x_type = TYPE_PL010;
 197 #elif defined(CONFIG_PL011_SERIAL)
 198         pl01x_type = TYPE_PL011;
 199         clock = CONFIG_PL011_CLOCK;
 200 #endif
 201         base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
 202
 203         pl01x_generic_serial_init(base_regs, pl01x_type);
 204         pl01x_generic_setbrg(base_regs, TYPE_PL010, clock, baudrate);
 205 }
 206
 207 /*
 208  * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
 209  * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
 210  * Versatile PB has four UARTs.
 211  */
 212 int pl01x_serial_init(void)
 213 {
 214         pl01x_serial_init_baud(CONFIG_BAUDRATE);
 215
 216         return 0;
 217 }
 218
 219 static void pl01x_serial_putc(const char c)
 220 {
 221         if (c == '\n')
 222                 while (pl01x_putc(base_regs, '\r') == -EAGAIN);
 223
 224         while (pl01x_putc(base_regs, c) == -EAGAIN);
 225 }
 226
 227 static int pl01x_serial_getc(void)
 228 {
 229         while (1) {
 230                 int ch = pl01x_getc(base_regs);
 231
 232                 if (ch == -EAGAIN) {
 233                         WATCHDOG_RESET();
 234                         continue;
 235                 }
 236
 237                 return ch;
 238         }
 239 }
 240
 241 static int pl01x_serial_tstc(void)
 242 {
 243         return pl01x_tstc(base_regs);
 244 }
 245
 246 static void pl01x_serial_setbrg(void)
 247 {
 248         /*
 249          * Flush FIFO and wait for non-busy before changing baudrate to avoid
 250          * crap in console
 251          */
 252         while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
 253                 WATCHDOG_RESET();
 254         while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
 255                 WATCHDOG_RESET();
 256         pl01x_serial_init_baud(gd->baudrate);
 257 }
 258
 259 static struct serial_device pl01x_serial_drv = {
 260         .name   = "pl01x_serial",
 261         .start  = pl01x_serial_init,
 262         .stop   = NULL,
 263         .setbrg = pl01x_serial_setbrg,
 264         .putc   = pl01x_serial_putc,
 265         .puts   = default_serial_puts,
 266         .getc   = pl01x_serial_getc,
 267         .tstc   = pl01x_serial_tstc,
 268 };
 269
 270 void pl01x_serial_initialize(void)
 271 {
 272         serial_register(&pl01x_serial_drv);
 273 }
 274
 275 __weak struct serial_device *default_serial_console(void)
 276 {
 277         return &pl01x_serial_drv;
 278 }
 279
 280 #endif /* nCONFIG_DM_SERIAL */
 281
 282 #ifdef CONFIG_DM_SERIAL
 283
 284 struct pl01x_priv {
 285         struct pl01x_regs *regs;
 286         enum pl01x_type type;
 287 };
 288
 289 static int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
 290 {
 291         struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
 292         struct pl01x_priv *priv = dev_get_priv(dev);
 293
 294         pl01x_generic_setbrg(priv->regs, priv->type, plat->clock, baudrate);
 295
 296         return 0;
 297 }
 298
 299 static int pl01x_serial_probe(struct udevice *dev)
 300 {
 301         struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
 302         struct pl01x_priv *priv = dev_get_priv(dev);
 303
 304         priv->regs = (struct pl01x_regs *)plat->base;
 305         priv->type = plat->type;
 306         return pl01x_generic_serial_init(priv->regs, priv->type);
 307 }
 308
 309 static int pl01x_serial_getc(struct udevice *dev)
 310 {
 311         struct pl01x_priv *priv = dev_get_priv(dev);
 312
 313         return pl01x_getc(priv->regs);
 314 }
 315
 316 static int pl01x_serial_putc(struct udevice *dev, const char ch)
 317 {
 318         struct pl01x_priv *priv = dev_get_priv(dev);
 319
 320         return pl01x_putc(priv->regs, ch);
 321 }
 322
 323 static int pl01x_serial_pending(struct udevice *dev, bool input)
 324 {
 325         struct pl01x_priv *priv = dev_get_priv(dev);
 326         unsigned int fr = readl(&priv->regs->fr);
 327
 328         if (input)
 329                 return pl01x_tstc(priv->regs);
 330         else
 331                 return fr & UART_PL01x_FR_TXFF ? 0 : 1;
 332 }
 333
 334 static const struct dm_serial_ops pl01x_serial_ops = {
 335         .putc = pl01x_serial_putc,
 336         .pending = pl01x_serial_pending,
 337         .getc = pl01x_serial_getc,
 338         .setbrg = pl01x_serial_setbrg,
 339 };
 340
 341 U_BOOT_DRIVER(serial_pl01x) = {
 342         .name   = "serial_pl01x",
 343         .id     = UCLASS_SERIAL,
 344         .probe = pl01x_serial_probe,
 345         .ops    = &pl01x_serial_ops,
 346         .flags = DM_FLAG_PRE_RELOC,
 347 };
 348
 349 #endif