3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
7 * Philippe Robin, <philippe.robin@arm.com>
9 * SPDX-License-Identifier: GPL-2.0+
12 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
20 #include <dm/platform_data/serial_pl01x.h>
21 #include <linux/compiler.h>
22 #include "serial_pl01x_internal.h"
25 DECLARE_GLOBAL_DATA_PTR
;
27 #ifndef CONFIG_DM_SERIAL
29 static volatile unsigned char *const port
[] = CONFIG_PL01x_PORTS
;
30 static enum pl01x_type pl01x_type
__attribute__ ((section(".data")));
31 static struct pl01x_regs
*base_regs
__attribute__ ((section(".data")));
32 #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
36 static int pl01x_putc(struct pl01x_regs
*regs
, char c
)
38 /* Wait until there is space in the FIFO */
39 if (readl(®s
->fr
) & UART_PL01x_FR_TXFF
)
42 /* Send the character */
48 static int pl01x_getc(struct pl01x_regs
*regs
)
52 /* Wait until there is data in the FIFO */
53 if (readl(®s
->fr
) & UART_PL01x_FR_RXFE
)
56 data
= readl(®s
->dr
);
58 /* Check for an error flag */
59 if (data
& 0xFFFFFF00) {
61 writel(0xFFFFFFFF, ®s
->ecr
);
68 static int pl01x_tstc(struct pl01x_regs
*regs
)
71 return !(readl(®s
->fr
) & UART_PL01x_FR_RXFE
);
74 static int pl01x_generic_serial_init(struct pl01x_regs
*regs
,
79 /* disable everything */
80 writel(0, ®s
->pl010_cr
);
83 /* disable everything */
84 writel(0, ®s
->pl011_cr
);
93 static int pl011_set_line_control(struct pl01x_regs
*regs
)
97 * Internal update of baud rate register require line
98 * control register write
100 lcr
= UART_PL011_LCRH_WLEN_8
| UART_PL011_LCRH_FEN
;
101 writel(lcr
, ®s
->pl011_lcrh
);
105 static int pl01x_generic_setbrg(struct pl01x_regs
*regs
, enum pl01x_type type
,
106 int clock
, int baudrate
)
110 unsigned int divisor
;
112 /* disable everything */
113 writel(0, ®s
->pl010_cr
);
117 divisor
= UART_PL010_BAUD_9600
;
120 divisor
= UART_PL010_BAUD_19200
;
123 divisor
= UART_PL010_BAUD_38400
;
126 divisor
= UART_PL010_BAUD_57600
;
129 divisor
= UART_PL010_BAUD_115200
;
132 divisor
= UART_PL010_BAUD_38400
;
135 writel((divisor
& 0xf00) >> 8, ®s
->pl010_lcrm
);
136 writel(divisor
& 0xff, ®s
->pl010_lcrl
);
139 * Set line control for the PL010 to be 8 bits, 1 stop bit,
140 * no parity, fifo enabled
142 writel(UART_PL010_LCRH_WLEN_8
| UART_PL010_LCRH_FEN
,
144 /* Finally, enable the UART */
145 writel(UART_PL010_CR_UARTEN
, ®s
->pl010_cr
);
150 unsigned int divider
;
151 unsigned int remainder
;
152 unsigned int fraction
;
157 * IBRD = UART_CLK / (16 * BAUD_RATE)
158 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
159 * / (16 * BAUD_RATE))
161 temp
= 16 * baudrate
;
162 divider
= clock
/ temp
;
163 remainder
= clock
% temp
;
164 temp
= (8 * remainder
) / baudrate
;
165 fraction
= (temp
>> 1) + (temp
& 1);
167 writel(divider
, ®s
->pl011_ibrd
);
168 writel(fraction
, ®s
->pl011_fbrd
);
170 pl011_set_line_control(regs
);
171 /* Finally, enable the UART */
172 writel(UART_PL011_CR_UARTEN
| UART_PL011_CR_TXE
|
173 UART_PL011_CR_RXE
| UART_PL011_CR_RTS
, ®s
->pl011_cr
);
183 #ifndef CONFIG_DM_SERIAL
184 static void pl01x_serial_init_baud(int baudrate
)
188 #if defined(CONFIG_PL010_SERIAL)
189 pl01x_type
= TYPE_PL010
;
190 #elif defined(CONFIG_PL011_SERIAL)
191 pl01x_type
= TYPE_PL011
;
192 clock
= CONFIG_PL011_CLOCK
;
194 base_regs
= (struct pl01x_regs
*)port
[CONFIG_CONS_INDEX
];
196 pl01x_generic_serial_init(base_regs
, pl01x_type
);
197 pl01x_generic_setbrg(base_regs
, pl01x_type
, clock
, baudrate
);
201 * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
202 * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
203 * Versatile PB has four UARTs.
205 int pl01x_serial_init(void)
207 pl01x_serial_init_baud(CONFIG_BAUDRATE
);
212 static void pl01x_serial_putc(const char c
)
215 while (pl01x_putc(base_regs
, '\r') == -EAGAIN
);
217 while (pl01x_putc(base_regs
, c
) == -EAGAIN
);
220 static int pl01x_serial_getc(void)
223 int ch
= pl01x_getc(base_regs
);
234 static int pl01x_serial_tstc(void)
236 return pl01x_tstc(base_regs
);
239 static void pl01x_serial_setbrg(void)
242 * Flush FIFO and wait for non-busy before changing baudrate to avoid
245 while (!(readl(&base_regs
->fr
) & UART_PL01x_FR_TXFE
))
247 while (readl(&base_regs
->fr
) & UART_PL01x_FR_BUSY
)
249 pl01x_serial_init_baud(gd
->baudrate
);
252 static struct serial_device pl01x_serial_drv
= {
253 .name
= "pl01x_serial",
254 .start
= pl01x_serial_init
,
256 .setbrg
= pl01x_serial_setbrg
,
257 .putc
= pl01x_serial_putc
,
258 .puts
= default_serial_puts
,
259 .getc
= pl01x_serial_getc
,
260 .tstc
= pl01x_serial_tstc
,
263 void pl01x_serial_initialize(void)
265 serial_register(&pl01x_serial_drv
);
268 __weak
struct serial_device
*default_serial_console(void)
270 return &pl01x_serial_drv
;
273 #endif /* nCONFIG_DM_SERIAL */
275 #ifdef CONFIG_DM_SERIAL
278 struct pl01x_regs
*regs
;
279 enum pl01x_type type
;
282 static int pl01x_serial_setbrg(struct udevice
*dev
, int baudrate
)
284 struct pl01x_serial_platdata
*plat
= dev_get_platdata(dev
);
285 struct pl01x_priv
*priv
= dev_get_priv(dev
);
287 if (!plat
->skip_init
) {
288 pl01x_generic_setbrg(priv
->regs
, priv
->type
, plat
->clock
,
295 static int pl01x_serial_probe(struct udevice
*dev
)
297 struct pl01x_serial_platdata
*plat
= dev_get_platdata(dev
);
298 struct pl01x_priv
*priv
= dev_get_priv(dev
);
300 priv
->regs
= (struct pl01x_regs
*)plat
->base
;
301 priv
->type
= plat
->type
;
302 if (!plat
->skip_init
)
303 return pl01x_generic_serial_init(priv
->regs
, priv
->type
);
308 static int pl01x_serial_getc(struct udevice
*dev
)
310 struct pl01x_priv
*priv
= dev_get_priv(dev
);
312 return pl01x_getc(priv
->regs
);
315 static int pl01x_serial_putc(struct udevice
*dev
, const char ch
)
317 struct pl01x_priv
*priv
= dev_get_priv(dev
);
319 return pl01x_putc(priv
->regs
, ch
);
322 static int pl01x_serial_pending(struct udevice
*dev
, bool input
)
324 struct pl01x_priv
*priv
= dev_get_priv(dev
);
325 unsigned int fr
= readl(&priv
->regs
->fr
);
328 return pl01x_tstc(priv
->regs
);
330 return fr
& UART_PL01x_FR_TXFF
? 0 : 1;
333 static const struct dm_serial_ops pl01x_serial_ops
= {
334 .putc
= pl01x_serial_putc
,
335 .pending
= pl01x_serial_pending
,
336 .getc
= pl01x_serial_getc
,
337 .setbrg
= pl01x_serial_setbrg
,
340 #if CONFIG_IS_ENABLED(OF_CONTROL)
341 static const struct udevice_id pl01x_serial_id
[] ={
342 {.compatible
= "arm,pl011", .data
= TYPE_PL011
},
343 {.compatible
= "arm,pl010", .data
= TYPE_PL010
},
347 static int pl01x_serial_ofdata_to_platdata(struct udevice
*dev
)
349 struct pl01x_serial_platdata
*plat
= dev_get_platdata(dev
);
352 addr
= dev_get_addr(dev
);
353 if (addr
== FDT_ADDR_T_NONE
)
357 plat
->clock
= fdtdec_get_int(gd
->fdt_blob
, dev_of_offset(dev
), "clock",
359 plat
->type
= dev_get_driver_data(dev
);
360 plat
->skip_init
= fdtdec_get_bool(gd
->fdt_blob
, dev_of_offset(dev
),
366 U_BOOT_DRIVER(serial_pl01x
) = {
367 .name
= "serial_pl01x",
369 .of_match
= of_match_ptr(pl01x_serial_id
),
370 .ofdata_to_platdata
= of_match_ptr(pl01x_serial_ofdata_to_platdata
),
371 .platdata_auto_alloc_size
= sizeof(struct pl01x_serial_platdata
),
372 .probe
= pl01x_serial_probe
,
373 .ops
= &pl01x_serial_ops
,
374 .flags
= DM_FLAG_PRE_RELOC
,
375 .priv_auto_alloc_size
= sizeof(struct pl01x_priv
),
380 #if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011)
382 #include <debug_uart.h>
384 static void _debug_uart_init(void)
386 #ifndef CONFIG_DEBUG_UART_SKIP_INIT
387 struct pl01x_regs
*regs
= (struct pl01x_regs
*)CONFIG_DEBUG_UART_BASE
;
388 enum pl01x_type type
= CONFIG_IS_ENABLED(DEBUG_UART_PL011
) ?
389 TYPE_PL011
: TYPE_PL010
;
391 pl01x_generic_serial_init(regs
, type
);
392 pl01x_generic_setbrg(regs
, type
,
393 CONFIG_DEBUG_UART_CLOCK
, CONFIG_BAUDRATE
);
397 static inline void _debug_uart_putc(int ch
)
399 struct pl01x_regs
*regs
= (struct pl01x_regs
*)CONFIG_DEBUG_UART_BASE
;
401 pl01x_putc(regs
, ch
);