drivers/spi/davinci_spi.c

   1 /*
   2  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * Driver for SPI controller on DaVinci. Based on atmel_spi.c
   5  * by Atmel Corporation
   6  *
   7  * Copyright (C) 2007 Atmel Corporation
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11 #include <common.h>
  12 #include <spi.h>
  13 #include <malloc.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/hardware.h>
  16 #include "davinci_spi.h"
  17
  18 void spi_init()
  19 {
  20         /* do nothing */
  21 }
  22
  23 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  24                         unsigned int max_hz, unsigned int mode)
  25 {
  26         struct davinci_spi_slave        *ds;
  27
  28         if (!spi_cs_is_valid(bus, cs))
  29                 return NULL;
  30
  31         ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs);
  32         if (!ds)
  33                 return NULL;
  34
  35         switch (bus) {
  36         case SPI0_BUS:
  37                 ds->regs = (struct davinci_spi_regs *)SPI0_BASE;
  38                 break;
  39 #ifdef CONFIG_SYS_SPI1
  40         case SPI1_BUS:
  41                 ds->regs = (struct davinci_spi_regs *)SPI1_BASE;
  42                 break;
  43 #endif
  44 #ifdef CONFIG_SYS_SPI2
  45         case SPI2_BUS:
  46                 ds->regs = (struct davinci_spi_regs *)SPI2_BASE;
  47                 break;
  48 #endif
  49         default: /* Invalid bus number */
  50                 return NULL;
  51         }
  52
  53         ds->freq = max_hz;
  54
  55         return &ds->slave;
  56 }
  57
  58 void spi_free_slave(struct spi_slave *slave)
  59 {
  60         struct davinci_spi_slave *ds = to_davinci_spi(slave);
  61
  62         free(ds);
  63 }
  64
  65 int spi_claim_bus(struct spi_slave *slave)
  66 {
  67         struct davinci_spi_slave *ds = to_davinci_spi(slave);
  68         unsigned int scalar;
  69
  70         /* Enable the SPI hardware */
  71         writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
  72         udelay(1000);
  73         writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0);
  74
  75         /* Set master mode, powered up and not activated */
  76         writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
  77
  78         /* CS, CLK, SIMO and SOMI are functional pins */
  79         writel(((1 << slave->cs) | SPIPC0_CLKFUN_MASK |
  80                 SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
  81
  82         /* setup format */
  83         scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
  84
  85         /*
  86          * Use following format:
  87          *   character length = 8,
  88          *   clock signal delayed by half clk cycle,
  89          *   clock low in idle state - Mode 0,
  90          *   MSB shifted out first
  91          */
  92         writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
  93                 (1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
  94
  95         /*
  96          * Including a minor delay. No science here. Should be good even with
  97          * no delay
  98          */
  99         writel((50 << SPI_C2TDELAY_SHIFT) |
 100                 (50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
 101
 102         /* default chip select register */
 103         writel(SPIDEF_CSDEF0_MASK, &ds->regs->def);
 104
 105         /* no interrupts */
 106         writel(0, &ds->regs->int0);
 107         writel(0, &ds->regs->lvl);
 108
 109         /* enable SPI */
 110         writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
 111
 112         return 0;
 113 }
 114
 115 void spi_release_bus(struct spi_slave *slave)
 116 {
 117         struct davinci_spi_slave *ds = to_davinci_spi(slave);
 118
 119         /* Disable the SPI hardware */
 120         writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
 121 }
 122
 123 /*
 124  * This functions needs to act like a macro to avoid pipeline reloads in the
 125  * loops below. Use always_inline. This gains us about 160KiB/s and the bloat
 126  * appears to be zero bytes (da830).
 127  */
 128 __attribute__((always_inline))
 129 static inline u32 davinci_spi_xfer_data(struct davinci_spi_slave *ds, u32 data)
 130 {
 131         u32     buf_reg_val;
 132
 133         /* send out data */
 134         writel(data, &ds->regs->dat1);
 135
 136         /* wait for the data to clock in/out */
 137         while ((buf_reg_val = readl(&ds->regs->buf)) & SPIBUF_RXEMPTY_MASK)
 138                 ;
 139
 140         return buf_reg_val;
 141 }
 142
 143 static int davinci_spi_read(struct spi_slave *slave, unsigned int len,
 144                             u8 *rxp, unsigned long flags)
 145 {
 146         struct davinci_spi_slave *ds = to_davinci_spi(slave);
 147         unsigned int data1_reg_val;
 148
 149         /* enable CS hold, CS[n] and clear the data bits */
 150         data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
 151                          (slave->cs << SPIDAT1_CSNR_SHIFT));
 152
 153         /* wait till TXFULL is deasserted */
 154         while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
 155                 ;
 156
 157         /* preload the TX buffer to avoid clock starvation */
 158         writel(data1_reg_val, &ds->regs->dat1);
 159
 160         /* keep reading 1 byte until only 1 byte left */
 161         while ((len--) > 1)
 162                 *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val);
 163
 164         /* clear CS hold when we reach the end */
 165         if (flags & SPI_XFER_END)
 166                 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
 167
 168         /* read the last byte */
 169         *rxp = davinci_spi_xfer_data(ds, data1_reg_val);
 170
 171         return 0;
 172 }
 173
 174 static int davinci_spi_write(struct spi_slave *slave, unsigned int len,
 175                              const u8 *txp, unsigned long flags)
 176 {
 177         struct davinci_spi_slave *ds = to_davinci_spi(slave);
 178         unsigned int data1_reg_val;
 179
 180         /* enable CS hold and clear the data bits */
 181         data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
 182                          (slave->cs << SPIDAT1_CSNR_SHIFT));
 183
 184         /* wait till TXFULL is deasserted */
 185         while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
 186                 ;
 187
 188         /* preload the TX buffer to avoid clock starvation */
 189         if (len > 2) {
 190                 writel(data1_reg_val | *txp++, &ds->regs->dat1);
 191                 len--;
 192         }
 193
 194         /* keep writing 1 byte until only 1 byte left */
 195         while ((len--) > 1)
 196                 davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
 197
 198         /* clear CS hold when we reach the end */
 199         if (flags & SPI_XFER_END)
 200                 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
 201
 202         /* write the last byte */
 203         davinci_spi_xfer_data(ds, data1_reg_val | *txp);
 204
 205         return 0;
 206 }
 207
 208 #ifndef CONFIG_SPI_HALF_DUPLEX
 209 static int davinci_spi_read_write(struct spi_slave *slave, unsigned int len,
 210                                   u8 *rxp, const u8 *txp, unsigned long flags)
 211 {
 212         struct davinci_spi_slave *ds = to_davinci_spi(slave);
 213         unsigned int data1_reg_val;
 214
 215         /* enable CS hold and clear the data bits */
 216         data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
 217                          (slave->cs << SPIDAT1_CSNR_SHIFT));
 218
 219         /* wait till TXFULL is deasserted */
 220         while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
 221                 ;
 222
 223         /* keep reading and writing 1 byte until only 1 byte left */
 224         while ((len--) > 1)
 225                 *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
 226
 227         /* clear CS hold when we reach the end */
 228         if (flags & SPI_XFER_END)
 229                 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
 230
 231         /* read and write the last byte */
 232         *rxp = davinci_spi_xfer_data(ds, data1_reg_val | *txp);
 233
 234         return 0;
 235 }
 236 #endif
 237
 238 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 239              const void *dout, void *din, unsigned long flags)
 240 {
 241         unsigned int len;
 242
 243         if (bitlen == 0)
 244                 /* Finish any previously submitted transfers */
 245                 goto out;
 246
 247         /*
 248          * It's not clear how non-8-bit-aligned transfers are supposed to be
 249          * represented as a stream of bytes...this is a limitation of
 250          * the current SPI interface - here we terminate on receiving such a
 251          * transfer request.
 252          */
 253         if (bitlen % 8) {
 254                 /* Errors always terminate an ongoing transfer */
 255                 flags |= SPI_XFER_END;
 256                 goto out;
 257         }
 258
 259         len = bitlen / 8;
 260
 261         if (!dout)
 262                 return davinci_spi_read(slave, len, din, flags);
 263         else if (!din)
 264                 return davinci_spi_write(slave, len, dout, flags);
 265 #ifndef CONFIG_SPI_HALF_DUPLEX
 266         else
 267                 return davinci_spi_read_write(slave, len, din, dout, flags);
 268 #else
 269         printf("SPI full duplex transaction requested with "
 270                "CONFIG_SPI_HALF_DUPLEX defined.\n");
 271         flags |= SPI_XFER_END;
 272 #endif
 273
 274 out:
 275         if (flags & SPI_XFER_END) {
 276                 u8 dummy = 0;
 277                 davinci_spi_write(slave, 1, &dummy, flags);
 278         }
 279         return 0;
 280 }
 281
 282 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 283 {
 284         int ret = 0;
 285
 286         switch (bus) {
 287         case SPI0_BUS:
 288                 if (cs < SPI0_NUM_CS)
 289                         ret = 1;
 290                 break;
 291 #ifdef CONFIG_SYS_SPI1
 292         case SPI1_BUS:
 293                 if (cs < SPI1_NUM_CS)
 294                         ret = 1;
 295                 break;
 296 #endif
 297 #ifdef CONFIG_SYS_SPI2
 298         case SPI2_BUS:
 299                 if (cs < SPI2_NUM_CS)
 300                         ret = 1;
 301                 break;
 302 #endif
 303         default:
 304                 /* Invalid bus number. Do nothing */
 305                 break;
 306         }
 307         return ret;
 308 }
 309
 310 void spi_cs_activate(struct spi_slave *slave)
 311 {
 312         /* do nothing */
 313 }
 314
 315 void spi_cs_deactivate(struct spi_slave *slave)
 316 {
 317         /* do nothing */
 318 }