drivers/spi/davinci_spi.c

   1 /*
   2  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * Driver for SPI controller on DaVinci. Based on atmel_spi.c
   5  * by Atmel Corporation
   6  *
   7  * Copyright (C) 2007 Atmel Corporation
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27 #include <common.h>
  28 #include <spi.h>
  29 #include <malloc.h>
  30 #include <asm/io.h>
  31 #include <asm/arch/hardware.h>
  32 #include "davinci_spi.h"
  33
  34 void spi_init()
  35 {
  36         /* do nothing */
  37 }
  38
  39 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  40                         unsigned int max_hz, unsigned int mode)
  41 {
  42         struct davinci_spi_slave        *ds;
  43
  44         if (!spi_cs_is_valid(bus, cs))
  45                 return NULL;
  46
  47         ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs);
  48         if (!ds)
  49                 return NULL;
  50
  51         ds->regs = (struct davinci_spi_regs *)CONFIG_SYS_SPI_BASE;
  52         ds->freq = max_hz;
  53
  54         return &ds->slave;
  55 }
  56
  57 void spi_free_slave(struct spi_slave *slave)
  58 {
  59         struct davinci_spi_slave *ds = to_davinci_spi(slave);
  60
  61         free(ds);
  62 }
  63
  64 int spi_claim_bus(struct spi_slave *slave)
  65 {
  66         struct davinci_spi_slave *ds = to_davinci_spi(slave);
  67         unsigned int scalar;
  68
  69         /* Enable the SPI hardware */
  70         writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
  71         udelay(1000);
  72         writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0);
  73
  74         /* Set master mode, powered up and not activated */
  75         writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
  76
  77         /* CS, CLK, SIMO and SOMI are functional pins */
  78         writel((SPIPC0_EN0FUN_MASK | SPIPC0_CLKFUN_MASK |
  79                 SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
  80
  81         /* setup format */
  82         scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
  83
  84         /*
  85          * Use following format:
  86          *   character length = 8,
  87          *   clock signal delayed by half clk cycle,
  88          *   clock low in idle state - Mode 0,
  89          *   MSB shifted out first
  90          */
  91         writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
  92                 (1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
  93
  94         /*
  95          * Including a minor delay. No science here. Should be good even with
  96          * no delay
  97          */
  98         writel((50 << SPI_C2TDELAY_SHIFT) |
  99                 (50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
 100
 101         /* default chip select register */
 102         writel(SPIDEF_CSDEF0_MASK, &ds->regs->def);
 103
 104         /* no interrupts */
 105         writel(0, &ds->regs->int0);
 106         writel(0, &ds->regs->lvl);
 107
 108         /* enable SPI */
 109         writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
 110
 111         return 0;
 112 }
 113
 114 void spi_release_bus(struct spi_slave *slave)
 115 {
 116         struct davinci_spi_slave *ds = to_davinci_spi(slave);
 117
 118         /* Disable the SPI hardware */
 119         writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
 120 }
 121
 122 /*
 123  * This functions needs to act like a macro to avoid pipeline reloads in the
 124  * loops below. Use always_inline. This gains us about 160KiB/s and the bloat
 125  * appears to be zero bytes (da830).
 126  */
 127 __attribute__((always_inline))
 128 static inline u32 davinci_spi_xfer_data(struct davinci_spi_slave *ds, u32 data)
 129 {
 130         u32     buf_reg_val;
 131
 132         /* send out data */
 133         writel(data, &ds->regs->dat1);
 134
 135         /* wait for the data to clock in/out */
 136         while ((buf_reg_val = readl(&ds->regs->buf)) & SPIBUF_RXEMPTY_MASK)
 137                 ;
 138
 139         return buf_reg_val;
 140 }
 141
 142 static int davinci_spi_read(struct spi_slave *slave, unsigned int len,
 143                             u8 *rxp, unsigned long flags)
 144 {
 145         struct davinci_spi_slave *ds = to_davinci_spi(slave);
 146         unsigned int data1_reg_val;
 147
 148         /* enable CS hold, CS[n] and clear the data bits */
 149         data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
 150                          (slave->cs << SPIDAT1_CSNR_SHIFT));
 151
 152         /* wait till TXFULL is deasserted */
 153         while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
 154                 ;
 155
 156         /* preload the TX buffer to avoid clock starvation */
 157         writel(data1_reg_val, &ds->regs->dat1);
 158
 159         /* keep reading 1 byte until only 1 byte left */
 160         while ((len--) > 1)
 161                 *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val);
 162
 163         /* clear CS hold when we reach the end */
 164         if (flags & SPI_XFER_END)
 165                 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
 166
 167         /* read the last byte */
 168         *rxp = davinci_spi_xfer_data(ds, data1_reg_val);
 169
 170         return 0;
 171 }
 172
 173 static int davinci_spi_write(struct spi_slave *slave, unsigned int len,
 174                              const u8 *txp, unsigned long flags)
 175 {
 176         struct davinci_spi_slave *ds = to_davinci_spi(slave);
 177         unsigned int data1_reg_val;
 178
 179         /* enable CS hold and clear the data bits */
 180         data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
 181                          (slave->cs << SPIDAT1_CSNR_SHIFT));
 182
 183         /* wait till TXFULL is deasserted */
 184         while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
 185                 ;
 186
 187         /* preload the TX buffer to avoid clock starvation */
 188         if (len > 2) {
 189                 writel(data1_reg_val | *txp++, &ds->regs->dat1);
 190                 len--;
 191         }
 192
 193         /* keep writing 1 byte until only 1 byte left */
 194         while ((len--) > 1)
 195                 davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
 196
 197         /* clear CS hold when we reach the end */
 198         if (flags & SPI_XFER_END)
 199                 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
 200
 201         /* write the last byte */
 202         davinci_spi_xfer_data(ds, data1_reg_val | *txp);
 203
 204         return 0;
 205 }
 206
 207 #ifndef CONFIG_SPI_HALF_DUPLEX
 208 static int davinci_spi_read_write(struct spi_slave *slave, unsigned int len,
 209                                   u8 *rxp, const u8 *txp, unsigned long flags)
 210 {
 211         struct davinci_spi_slave *ds = to_davinci_spi(slave);
 212         unsigned int data1_reg_val;
 213
 214         /* enable CS hold and clear the data bits */
 215         data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
 216                          (slave->cs << SPIDAT1_CSNR_SHIFT));
 217
 218         /* wait till TXFULL is deasserted */
 219         while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
 220                 ;
 221
 222         /* keep reading and writing 1 byte until only 1 byte left */
 223         while ((len--) > 1)
 224                 *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
 225
 226         /* clear CS hold when we reach the end */
 227         if (flags & SPI_XFER_END)
 228                 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
 229
 230         /* read and write the last byte */
 231         *rxp = davinci_spi_xfer_data(ds, data1_reg_val | *txp);
 232
 233         return 0;
 234 }
 235 #endif
 236
 237 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 238              const void *dout, void *din, unsigned long flags)
 239 {
 240         unsigned int len;
 241
 242         if (bitlen == 0)
 243                 /* Finish any previously submitted transfers */
 244                 goto out;
 245
 246         /*
 247          * It's not clear how non-8-bit-aligned transfers are supposed to be
 248          * represented as a stream of bytes...this is a limitation of
 249          * the current SPI interface - here we terminate on receiving such a
 250          * transfer request.
 251          */
 252         if (bitlen % 8) {
 253                 /* Errors always terminate an ongoing transfer */
 254                 flags |= SPI_XFER_END;
 255                 goto out;
 256         }
 257
 258         len = bitlen / 8;
 259
 260         if (!dout)
 261                 return davinci_spi_read(slave, len, din, flags);
 262         else if (!din)
 263                 return davinci_spi_write(slave, len, dout, flags);
 264 #ifndef CONFIG_SPI_HALF_DUPLEX
 265         else
 266                 return davinci_spi_read_write(slave, len, din, dout, flags);
 267 #else
 268         printf("SPI full duplex transaction requested with "
 269                "CONFIG_SPI_HALF_DUPLEX defined.\n");
 270         flags |= SPI_XFER_END;
 271 #endif
 272
 273 out:
 274         if (flags & SPI_XFER_END) {
 275                 u8 dummy = 0;
 276                 davinci_spi_write(slave, 1, &dummy, flags);
 277         }
 278         return 0;
 279 }
 280
 281 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 282 {
 283         return bus == 0 && cs == 0;
 284 }
 285
 286 void spi_cs_activate(struct spi_slave *slave)
 287 {
 288         /* do nothing */
 289 }
 290
 291 void spi_cs_deactivate(struct spi_slave *slave)
 292 {
 293         /* do nothing */
 294 }