2 * Copyright (C) 2016 Jagan Teki <jteki@openedev.com>
3 * Christophe Ricard <christophe.ricard@gmail.com>
5 * Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
7 * Driver for McSPI controller on OMAP3. Based on davinci_spi.c
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
10 * Copyright (C) 2007 Atmel Corporation
12 * Parts taken from linux/drivers/spi/omap2_mcspi.c
13 * Copyright (C) 2005, 2006 Nokia Corporation
15 * Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
17 * SPDX-License-Identifier: GPL-2.0+
26 DECLARE_GLOBAL_DATA_PTR
;
28 #if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
29 #define OMAP3_MCSPI1_BASE 0x48030100
30 #define OMAP3_MCSPI2_BASE 0x481A0100
32 #define OMAP3_MCSPI1_BASE 0x48098000
33 #define OMAP3_MCSPI2_BASE 0x4809A000
34 #define OMAP3_MCSPI3_BASE 0x480B8000
35 #define OMAP3_MCSPI4_BASE 0x480BA000
38 #define OMAP4_MCSPI_REG_OFFSET 0x100
40 struct omap2_mcspi_platform_config
{
41 unsigned int regs_offset
;
44 /* per-register bitmasks */
45 #define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
46 #define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
47 #define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
48 #define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
50 #define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
52 #define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0)
53 #define OMAP3_MCSPI_MODULCTRL_MS BIT(2)
54 #define OMAP3_MCSPI_MODULCTRL_STEST BIT(3)
56 #define OMAP3_MCSPI_CHCONF_PHA BIT(0)
57 #define OMAP3_MCSPI_CHCONF_POL BIT(1)
58 #define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2)
59 #define OMAP3_MCSPI_CHCONF_EPOL BIT(6)
60 #define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7)
61 #define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
62 #define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
63 #define OMAP3_MCSPI_CHCONF_TRM_MASK GENMASK(13, 12)
64 #define OMAP3_MCSPI_CHCONF_DMAW BIT(14)
65 #define OMAP3_MCSPI_CHCONF_DMAR BIT(15)
66 #define OMAP3_MCSPI_CHCONF_DPE0 BIT(16)
67 #define OMAP3_MCSPI_CHCONF_DPE1 BIT(17)
68 #define OMAP3_MCSPI_CHCONF_IS BIT(18)
69 #define OMAP3_MCSPI_CHCONF_TURBO BIT(19)
70 #define OMAP3_MCSPI_CHCONF_FORCE BIT(20)
72 #define OMAP3_MCSPI_CHSTAT_RXS BIT(0)
73 #define OMAP3_MCSPI_CHSTAT_TXS BIT(1)
74 #define OMAP3_MCSPI_CHSTAT_EOT BIT(2)
76 #define OMAP3_MCSPI_CHCTRL_EN BIT(0)
77 #define OMAP3_MCSPI_CHCTRL_DIS (0 << 0)
79 #define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0)
80 #define MCSPI_PINDIR_D0_IN_D1_OUT 0
81 #define MCSPI_PINDIR_D0_OUT_D1_IN 1
83 #define OMAP3_MCSPI_MAX_FREQ 48000000
84 #define SPI_WAIT_TIMEOUT 10
86 /* OMAP3 McSPI registers */
87 struct mcspi_channel
{
88 unsigned int chconf
; /* 0x2C, 0x40, 0x54, 0x68 */
89 unsigned int chstat
; /* 0x30, 0x44, 0x58, 0x6C */
90 unsigned int chctrl
; /* 0x34, 0x48, 0x5C, 0x70 */
91 unsigned int tx
; /* 0x38, 0x4C, 0x60, 0x74 */
92 unsigned int rx
; /* 0x3C, 0x50, 0x64, 0x78 */
96 unsigned char res1
[0x10];
97 unsigned int sysconfig
; /* 0x10 */
98 unsigned int sysstatus
; /* 0x14 */
99 unsigned int irqstatus
; /* 0x18 */
100 unsigned int irqenable
; /* 0x1C */
101 unsigned int wakeupenable
; /* 0x20 */
102 unsigned int syst
; /* 0x24 */
103 unsigned int modulctrl
; /* 0x28 */
104 struct mcspi_channel channel
[4];
105 /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
106 /* channel1: 0x40 - 0x50, bus 0 & 1 */
107 /* channel2: 0x54 - 0x64, bus 0 & 1 */
108 /* channel3: 0x68 - 0x78, bus 0 */
111 struct omap3_spi_priv
{
112 #ifndef CONFIG_DM_SPI
113 struct spi_slave slave
;
119 unsigned int wordlen
;
120 unsigned int pin_dir
:1;
123 static void omap3_spi_write_chconf(struct omap3_spi_priv
*priv
, int val
)
125 writel(val
, &priv
->regs
->channel
[priv
->cs
].chconf
);
126 /* Flash post writes to make immediate effect */
127 readl(&priv
->regs
->channel
[priv
->cs
].chconf
);
130 static void omap3_spi_set_enable(struct omap3_spi_priv
*priv
, int enable
)
132 writel(enable
, &priv
->regs
->channel
[priv
->cs
].chctrl
);
133 /* Flash post writes to make immediate effect */
134 readl(&priv
->regs
->channel
[priv
->cs
].chctrl
);
137 static int omap3_spi_write(struct omap3_spi_priv
*priv
, unsigned int len
,
138 const void *txp
, unsigned long flags
)
143 chconf
= readl(&priv
->regs
->channel
[priv
->cs
].chconf
);
145 /* Enable the channel */
146 omap3_spi_set_enable(priv
, OMAP3_MCSPI_CHCTRL_EN
);
148 chconf
&= ~(OMAP3_MCSPI_CHCONF_TRM_MASK
| OMAP3_MCSPI_CHCONF_WL_MASK
);
149 chconf
|= (priv
->wordlen
- 1) << 7;
150 chconf
|= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY
;
151 chconf
|= OMAP3_MCSPI_CHCONF_FORCE
;
152 omap3_spi_write_chconf(priv
, chconf
);
154 for (i
= 0; i
< len
; i
++) {
155 /* wait till TX register is empty (TXS == 1) */
156 start
= get_timer(0);
157 while (!(readl(&priv
->regs
->channel
[priv
->cs
].chstat
) &
158 OMAP3_MCSPI_CHSTAT_TXS
)) {
159 if (get_timer(start
) > SPI_WAIT_TIMEOUT
) {
160 printf("SPI TXS timed out, status=0x%08x\n",
161 readl(&priv
->regs
->channel
[priv
->cs
].chstat
));
166 unsigned int *tx
= &priv
->regs
->channel
[priv
->cs
].tx
;
167 if (priv
->wordlen
> 16)
168 writel(((u32
*)txp
)[i
], tx
);
169 else if (priv
->wordlen
> 8)
170 writel(((u16
*)txp
)[i
], tx
);
172 writel(((u8
*)txp
)[i
], tx
);
175 /* wait to finish of transfer */
176 while ((readl(&priv
->regs
->channel
[priv
->cs
].chstat
) &
177 (OMAP3_MCSPI_CHSTAT_EOT
| OMAP3_MCSPI_CHSTAT_TXS
)) !=
178 (OMAP3_MCSPI_CHSTAT_EOT
| OMAP3_MCSPI_CHSTAT_TXS
))
181 /* Disable the channel otherwise the next immediate RX will get affected */
182 omap3_spi_set_enable(priv
, OMAP3_MCSPI_CHCTRL_DIS
);
184 if (flags
& SPI_XFER_END
) {
186 chconf
&= ~OMAP3_MCSPI_CHCONF_FORCE
;
187 omap3_spi_write_chconf(priv
, chconf
);
192 static int omap3_spi_read(struct omap3_spi_priv
*priv
, unsigned int len
,
193 void *rxp
, unsigned long flags
)
198 chconf
= readl(&priv
->regs
->channel
[priv
->cs
].chconf
);
200 /* Enable the channel */
201 omap3_spi_set_enable(priv
, OMAP3_MCSPI_CHCTRL_EN
);
203 chconf
&= ~(OMAP3_MCSPI_CHCONF_TRM_MASK
| OMAP3_MCSPI_CHCONF_WL_MASK
);
204 chconf
|= (priv
->wordlen
- 1) << 7;
205 chconf
|= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY
;
206 chconf
|= OMAP3_MCSPI_CHCONF_FORCE
;
207 omap3_spi_write_chconf(priv
, chconf
);
209 writel(0, &priv
->regs
->channel
[priv
->cs
].tx
);
211 for (i
= 0; i
< len
; i
++) {
212 start
= get_timer(0);
213 /* Wait till RX register contains data (RXS == 1) */
214 while (!(readl(&priv
->regs
->channel
[priv
->cs
].chstat
) &
215 OMAP3_MCSPI_CHSTAT_RXS
)) {
216 if (get_timer(start
) > SPI_WAIT_TIMEOUT
) {
217 printf("SPI RXS timed out, status=0x%08x\n",
218 readl(&priv
->regs
->channel
[priv
->cs
].chstat
));
223 /* Disable the channel to prevent furher receiving */
225 omap3_spi_set_enable(priv
, OMAP3_MCSPI_CHCTRL_DIS
);
228 unsigned int *rx
= &priv
->regs
->channel
[priv
->cs
].rx
;
229 if (priv
->wordlen
> 16)
230 ((u32
*)rxp
)[i
] = readl(rx
);
231 else if (priv
->wordlen
> 8)
232 ((u16
*)rxp
)[i
] = (u16
)readl(rx
);
234 ((u8
*)rxp
)[i
] = (u8
)readl(rx
);
237 if (flags
& SPI_XFER_END
) {
238 chconf
&= ~OMAP3_MCSPI_CHCONF_FORCE
;
239 omap3_spi_write_chconf(priv
, chconf
);
245 /*McSPI Transmit Receive Mode*/
246 static int omap3_spi_txrx(struct omap3_spi_priv
*priv
, unsigned int len
,
247 const void *txp
, void *rxp
, unsigned long flags
)
252 chconf
= readl(&priv
->regs
->channel
[priv
->cs
].chconf
);
254 /*Enable SPI channel*/
255 omap3_spi_set_enable(priv
, OMAP3_MCSPI_CHCTRL_EN
);
257 /*set TRANSMIT-RECEIVE Mode*/
258 chconf
&= ~(OMAP3_MCSPI_CHCONF_TRM_MASK
| OMAP3_MCSPI_CHCONF_WL_MASK
);
259 chconf
|= (priv
->wordlen
- 1) << 7;
260 chconf
|= OMAP3_MCSPI_CHCONF_FORCE
;
261 omap3_spi_write_chconf(priv
, chconf
);
263 /*Shift in and out 1 byte at time*/
264 for (i
=0; i
< len
; i
++){
265 /* Write: wait for TX empty (TXS == 1)*/
266 start
= get_timer(0);
267 while (!(readl(&priv
->regs
->channel
[priv
->cs
].chstat
) &
268 OMAP3_MCSPI_CHSTAT_TXS
)) {
269 if (get_timer(start
) > SPI_WAIT_TIMEOUT
) {
270 printf("SPI TXS timed out, status=0x%08x\n",
271 readl(&priv
->regs
->channel
[priv
->cs
].chstat
));
276 unsigned int *tx
= &priv
->regs
->channel
[priv
->cs
].tx
;
277 if (priv
->wordlen
> 16)
278 writel(((u32
*)txp
)[i
], tx
);
279 else if (priv
->wordlen
> 8)
280 writel(((u16
*)txp
)[i
], tx
);
282 writel(((u8
*)txp
)[i
], tx
);
284 /*Read: wait for RX containing data (RXS == 1)*/
285 start
= get_timer(0);
286 while (!(readl(&priv
->regs
->channel
[priv
->cs
].chstat
) &
287 OMAP3_MCSPI_CHSTAT_RXS
)) {
288 if (get_timer(start
) > SPI_WAIT_TIMEOUT
) {
289 printf("SPI RXS timed out, status=0x%08x\n",
290 readl(&priv
->regs
->channel
[priv
->cs
].chstat
));
295 unsigned int *rx
= &priv
->regs
->channel
[priv
->cs
].rx
;
296 if (priv
->wordlen
> 16)
297 ((u32
*)rxp
)[i
] = readl(rx
);
298 else if (priv
->wordlen
> 8)
299 ((u16
*)rxp
)[i
] = (u16
)readl(rx
);
301 ((u8
*)rxp
)[i
] = (u8
)readl(rx
);
303 /* Disable the channel */
304 omap3_spi_set_enable(priv
, OMAP3_MCSPI_CHCTRL_DIS
);
306 /*if transfer must be terminated disable the channel*/
307 if (flags
& SPI_XFER_END
) {
308 chconf
&= ~OMAP3_MCSPI_CHCONF_FORCE
;
309 omap3_spi_write_chconf(priv
, chconf
);
315 static int _spi_xfer(struct omap3_spi_priv
*priv
, unsigned int bitlen
,
316 const void *dout
, void *din
, unsigned long flags
)
321 if (priv
->wordlen
< 4 || priv
->wordlen
> 32) {
322 printf("omap3_spi: invalid wordlen %d\n", priv
->wordlen
);
326 if (bitlen
% priv
->wordlen
)
329 len
= bitlen
/ priv
->wordlen
;
331 if (bitlen
== 0) { /* only change CS */
332 int chconf
= readl(&priv
->regs
->channel
[priv
->cs
].chconf
);
334 if (flags
& SPI_XFER_BEGIN
) {
335 omap3_spi_set_enable(priv
, OMAP3_MCSPI_CHCTRL_EN
);
336 chconf
|= OMAP3_MCSPI_CHCONF_FORCE
;
337 omap3_spi_write_chconf(priv
, chconf
);
339 if (flags
& SPI_XFER_END
) {
340 chconf
&= ~OMAP3_MCSPI_CHCONF_FORCE
;
341 omap3_spi_write_chconf(priv
, chconf
);
342 omap3_spi_set_enable(priv
, OMAP3_MCSPI_CHCTRL_DIS
);
346 if (dout
!= NULL
&& din
!= NULL
)
347 ret
= omap3_spi_txrx(priv
, len
, dout
, din
, flags
);
348 else if (dout
!= NULL
)
349 ret
= omap3_spi_write(priv
, len
, dout
, flags
);
350 else if (din
!= NULL
)
351 ret
= omap3_spi_read(priv
, len
, din
, flags
);
356 static void _omap3_spi_set_speed(struct omap3_spi_priv
*priv
)
358 uint32_t confr
, div
= 0;
360 confr
= readl(&priv
->regs
->channel
[priv
->cs
].chconf
);
362 /* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */
364 while (div
<= 0xC && (OMAP3_MCSPI_MAX_FREQ
/ (1 << div
))
371 /* set clock divisor */
372 confr
&= ~OMAP3_MCSPI_CHCONF_CLKD_MASK
;
375 omap3_spi_write_chconf(priv
, confr
);
378 static void _omap3_spi_set_mode(struct omap3_spi_priv
*priv
)
382 confr
= readl(&priv
->regs
->channel
[priv
->cs
].chconf
);
384 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
385 * REVISIT: this controller could support SPI_3WIRE mode.
387 if (priv
->pin_dir
== MCSPI_PINDIR_D0_IN_D1_OUT
) {
388 confr
&= ~(OMAP3_MCSPI_CHCONF_IS
|OMAP3_MCSPI_CHCONF_DPE1
);
389 confr
|= OMAP3_MCSPI_CHCONF_DPE0
;
391 confr
&= ~OMAP3_MCSPI_CHCONF_DPE0
;
392 confr
|= OMAP3_MCSPI_CHCONF_IS
|OMAP3_MCSPI_CHCONF_DPE1
;
395 /* set SPI mode 0..3 */
396 confr
&= ~(OMAP3_MCSPI_CHCONF_POL
| OMAP3_MCSPI_CHCONF_PHA
);
397 if (priv
->mode
& SPI_CPHA
)
398 confr
|= OMAP3_MCSPI_CHCONF_PHA
;
399 if (priv
->mode
& SPI_CPOL
)
400 confr
|= OMAP3_MCSPI_CHCONF_POL
;
402 /* set chipselect polarity; manage with FORCE */
403 if (!(priv
->mode
& SPI_CS_HIGH
))
404 confr
|= OMAP3_MCSPI_CHCONF_EPOL
; /* active-low; normal */
406 confr
&= ~OMAP3_MCSPI_CHCONF_EPOL
;
408 /* Transmit & receive mode */
409 confr
&= ~OMAP3_MCSPI_CHCONF_TRM_MASK
;
411 omap3_spi_write_chconf(priv
, confr
);
414 static void _omap3_spi_set_wordlen(struct omap3_spi_priv
*priv
)
418 /* McSPI individual channel configuration */
419 confr
= readl(&priv
->regs
->channel
[priv
->wordlen
].chconf
);
422 confr
&= ~OMAP3_MCSPI_CHCONF_WL_MASK
;
423 confr
|= (priv
->wordlen
- 1) << 7;
425 omap3_spi_write_chconf(priv
, confr
);
428 static void spi_reset(struct mcspi
*regs
)
432 writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET
, ®s
->sysconfig
);
434 tmp
= readl(®s
->sysstatus
);
435 } while (!(tmp
& OMAP3_MCSPI_SYSSTATUS_RESETDONE
));
437 writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE
|
438 OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP
|
439 OMAP3_MCSPI_SYSCONFIG_SMARTIDLE
, ®s
->sysconfig
);
441 writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN
, ®s
->wakeupenable
);
444 static void _omap3_spi_claim_bus(struct omap3_spi_priv
*priv
)
448 spi_reset(priv
->regs
);
451 * setup when switching from (reset default) slave mode
452 * to single-channel master mode
454 conf
= readl(&priv
->regs
->modulctrl
);
455 conf
&= ~(OMAP3_MCSPI_MODULCTRL_STEST
| OMAP3_MCSPI_MODULCTRL_MS
);
456 conf
|= OMAP3_MCSPI_MODULCTRL_SINGLE
;
458 writel(conf
, &priv
->regs
->modulctrl
);
460 _omap3_spi_set_mode(priv
);
461 _omap3_spi_set_speed(priv
);
464 #ifndef CONFIG_DM_SPI
466 static inline struct omap3_spi_priv
*to_omap3_spi(struct spi_slave
*slave
)
468 return container_of(slave
, struct omap3_spi_priv
, slave
);
476 void spi_free_slave(struct spi_slave
*slave
)
478 struct omap3_spi_priv
*priv
= to_omap3_spi(slave
);
483 int spi_claim_bus(struct spi_slave
*slave
)
485 struct omap3_spi_priv
*priv
= to_omap3_spi(slave
);
487 _omap3_spi_claim_bus(priv
);
488 _omap3_spi_set_wordlen(priv
);
489 _omap3_spi_set_mode(priv
);
490 _omap3_spi_set_speed(priv
);
495 void spi_release_bus(struct spi_slave
*slave
)
497 struct omap3_spi_priv
*priv
= to_omap3_spi(slave
);
499 /* Reset the SPI hardware */
500 spi_reset(priv
->regs
);
503 struct spi_slave
*spi_setup_slave(unsigned int bus
, unsigned int cs
,
504 unsigned int max_hz
, unsigned int mode
)
506 struct omap3_spi_priv
*priv
;
510 * OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules)
511 * with different number of chip selects (CS, channels):
512 * McSPI1 has 4 CS (bus 0, cs 0 - 3)
513 * McSPI2 has 2 CS (bus 1, cs 0 - 1)
514 * McSPI3 has 2 CS (bus 2, cs 0 - 1)
515 * McSPI4 has 1 CS (bus 3, cs 0)
520 regs
= (struct mcspi
*)OMAP3_MCSPI1_BASE
;
522 #ifdef OMAP3_MCSPI2_BASE
524 regs
= (struct mcspi
*)OMAP3_MCSPI2_BASE
;
527 #ifdef OMAP3_MCSPI3_BASE
529 regs
= (struct mcspi
*)OMAP3_MCSPI3_BASE
;
532 #ifdef OMAP3_MCSPI4_BASE
534 regs
= (struct mcspi
*)OMAP3_MCSPI4_BASE
;
538 printf("SPI error: unsupported bus %i. Supported busses 0 - 3\n", bus
);
542 if (((bus
== 0) && (cs
> 3)) ||
543 ((bus
== 1) && (cs
> 1)) ||
544 ((bus
== 2) && (cs
> 1)) ||
545 ((bus
== 3) && (cs
> 0))) {
546 printf("SPI error: unsupported chip select %i on bus %i\n", cs
, bus
);
550 if (max_hz
> OMAP3_MCSPI_MAX_FREQ
) {
551 printf("SPI error: unsupported frequency %i Hz. Max frequency is 48 Mhz\n", max_hz
);
555 if (mode
> SPI_MODE_3
) {
556 printf("SPI error: unsupported SPI mode %i\n", mode
);
560 priv
= spi_alloc_slave(struct omap3_spi_priv
, bus
, cs
);
562 printf("SPI error: malloc of SPI structure failed\n");
570 priv
->wordlen
= priv
->slave
.wordlen
;
572 /* Please migrate to DM_SPI support for this feature. */
573 priv
->pin_dir
= MCSPI_PINDIR_D0_OUT_D1_IN
;
579 int spi_xfer(struct spi_slave
*slave
, unsigned int bitlen
,
580 const void *dout
, void *din
, unsigned long flags
)
582 struct omap3_spi_priv
*priv
= to_omap3_spi(slave
);
584 return _spi_xfer(priv
, bitlen
, dout
, din
, flags
);
589 static int omap3_spi_claim_bus(struct udevice
*dev
)
591 struct udevice
*bus
= dev
->parent
;
592 struct omap3_spi_priv
*priv
= dev_get_priv(bus
);
593 struct dm_spi_slave_platdata
*slave_plat
= dev_get_parent_platdata(dev
);
595 priv
->cs
= slave_plat
->cs
;
596 priv
->mode
= slave_plat
->mode
;
597 priv
->freq
= slave_plat
->max_hz
;
598 _omap3_spi_claim_bus(priv
);
603 static int omap3_spi_release_bus(struct udevice
*dev
)
605 struct udevice
*bus
= dev
->parent
;
606 struct omap3_spi_priv
*priv
= dev_get_priv(bus
);
608 /* Reset the SPI hardware */
609 spi_reset(priv
->regs
);
614 static int omap3_spi_set_wordlen(struct udevice
*dev
, unsigned int wordlen
)
616 struct udevice
*bus
= dev
->parent
;
617 struct omap3_spi_priv
*priv
= dev_get_priv(bus
);
618 struct dm_spi_slave_platdata
*slave_plat
= dev_get_parent_platdata(dev
);
620 priv
->cs
= slave_plat
->cs
;
621 priv
->wordlen
= wordlen
;
622 _omap3_spi_set_wordlen(priv
);
627 static int omap3_spi_probe(struct udevice
*dev
)
629 struct omap3_spi_priv
*priv
= dev_get_priv(dev
);
630 const void *blob
= gd
->fdt_blob
;
631 int node
= dev_of_offset(dev
);
633 struct omap2_mcspi_platform_config
* data
=
634 (struct omap2_mcspi_platform_config
*)dev_get_driver_data(dev
);
636 priv
->regs
= (struct mcspi
*)(dev_get_addr(dev
) + data
->regs_offset
);
637 priv
->pin_dir
= fdtdec_get_uint(blob
, node
, "ti,pindir-d0-out-d1-in",
638 MCSPI_PINDIR_D0_IN_D1_OUT
);
639 priv
->wordlen
= SPI_DEFAULT_WORDLEN
;
643 static int omap3_spi_xfer(struct udevice
*dev
, unsigned int bitlen
,
644 const void *dout
, void *din
, unsigned long flags
)
646 struct udevice
*bus
= dev
->parent
;
647 struct omap3_spi_priv
*priv
= dev_get_priv(bus
);
649 return _spi_xfer(priv
, bitlen
, dout
, din
, flags
);
652 static int omap3_spi_set_speed(struct udevice
*bus
, unsigned int speed
)
657 static int omap3_spi_set_mode(struct udevice
*bus
, uint mode
)
662 static const struct dm_spi_ops omap3_spi_ops
= {
663 .claim_bus
= omap3_spi_claim_bus
,
664 .release_bus
= omap3_spi_release_bus
,
665 .set_wordlen
= omap3_spi_set_wordlen
,
666 .xfer
= omap3_spi_xfer
,
667 .set_speed
= omap3_spi_set_speed
,
668 .set_mode
= omap3_spi_set_mode
,
670 * cs_info is not needed, since we require all chip selects to be
671 * in the device tree explicitly
675 static struct omap2_mcspi_platform_config omap2_pdata
= {
679 static struct omap2_mcspi_platform_config omap4_pdata
= {
680 .regs_offset
= OMAP4_MCSPI_REG_OFFSET
,
683 static const struct udevice_id omap3_spi_ids
[] = {
684 { .compatible
= "ti,omap2-mcspi", .data
= (ulong
)&omap2_pdata
},
685 { .compatible
= "ti,omap4-mcspi", .data
= (ulong
)&omap4_pdata
},
689 U_BOOT_DRIVER(omap3_spi
) = {
692 .of_match
= omap3_spi_ids
,
693 .probe
= omap3_spi_probe
,
694 .ops
= &omap3_spi_ops
,
695 .priv_auto_alloc_size
= sizeof(struct omap3_spi_priv
),