drivers/spi/tegra20_sflash.c

   1 /*
   2  * Copyright (c) 2010-2013 NVIDIA Corporation
   3  * With help from the mpc8xxx SPI driver
   4  * With more help from omap3_spi SPI driver
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <malloc.h>
  11 #include <asm/io.h>
  12 #include <asm/gpio.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/pinmux.h>
  15 #include <asm/arch-tegra/clk_rst.h>
  16 #include <asm/arch-tegra20/tegra20_sflash.h>
  17 #include <spi.h>
  18 #include <fdtdec.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 #define SPI_CMD_GO                      (1 << 30)
  23 #define SPI_CMD_ACTIVE_SCLK_SHIFT       26
  24 #define SPI_CMD_ACTIVE_SCLK_MASK        (3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
  25 #define SPI_CMD_CK_SDA                  (1 << 21)
  26 #define SPI_CMD_ACTIVE_SDA_SHIFT        18
  27 #define SPI_CMD_ACTIVE_SDA_MASK         (3 << SPI_CMD_ACTIVE_SDA_SHIFT)
  28 #define SPI_CMD_CS_POL                  (1 << 16)
  29 #define SPI_CMD_TXEN                    (1 << 15)
  30 #define SPI_CMD_RXEN                    (1 << 14)
  31 #define SPI_CMD_CS_VAL                  (1 << 13)
  32 #define SPI_CMD_CS_SOFT                 (1 << 12)
  33 #define SPI_CMD_CS_DELAY                (1 << 9)
  34 #define SPI_CMD_CS3_EN                  (1 << 8)
  35 #define SPI_CMD_CS2_EN                  (1 << 7)
  36 #define SPI_CMD_CS1_EN                  (1 << 6)
  37 #define SPI_CMD_CS0_EN                  (1 << 5)
  38 #define SPI_CMD_BIT_LENGTH              (1 << 4)
  39 #define SPI_CMD_BIT_LENGTH_MASK         0x0000001F
  40
  41 #define SPI_STAT_BSY                    (1 << 31)
  42 #define SPI_STAT_RDY                    (1 << 30)
  43 #define SPI_STAT_RXF_FLUSH              (1 << 29)
  44 #define SPI_STAT_TXF_FLUSH              (1 << 28)
  45 #define SPI_STAT_RXF_UNR                (1 << 27)
  46 #define SPI_STAT_TXF_OVF                (1 << 26)
  47 #define SPI_STAT_RXF_EMPTY              (1 << 25)
  48 #define SPI_STAT_RXF_FULL               (1 << 24)
  49 #define SPI_STAT_TXF_EMPTY              (1 << 23)
  50 #define SPI_STAT_TXF_FULL               (1 << 22)
  51 #define SPI_STAT_SEL_TXRX_N             (1 << 16)
  52 #define SPI_STAT_CUR_BLKCNT             (1 << 15)
  53
  54 #define SPI_TIMEOUT             1000
  55 #define TEGRA_SPI_MAX_FREQ      52000000
  56
  57 struct spi_regs {
  58         u32 command;    /* SPI_COMMAND_0 register  */
  59         u32 status;     /* SPI_STATUS_0 register */
  60         u32 rx_cmp;     /* SPI_RX_CMP_0 register  */
  61         u32 dma_ctl;    /* SPI_DMA_CTL_0 register */
  62         u32 tx_fifo;    /* SPI_TX_FIFO_0 register */
  63         u32 rsvd[3];    /* offsets 0x14 to 0x1F reserved */
  64         u32 rx_fifo;    /* SPI_RX_FIFO_0 register */
  65 };
  66
  67 struct tegra_spi_ctrl {
  68         struct spi_regs *regs;
  69         unsigned int freq;
  70         unsigned int mode;
  71         int periph_id;
  72         int valid;
  73 };
  74
  75 struct tegra_spi_slave {
  76         struct spi_slave slave;
  77         struct tegra_spi_ctrl *ctrl;
  78 };
  79
  80 /* tegra20 only supports one SFLASH controller */
  81 static struct tegra_spi_ctrl spi_ctrls[1];
  82
  83 static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
  84 {
  85         return container_of(slave, struct tegra_spi_slave, slave);
  86 }
  87
  88 int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs)
  89 {
  90         /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
  91         if (bus != 0 || cs != 0)
  92                 return 0;
  93         else
  94                 return 1;
  95 }
  96
  97 struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs,
  98                                   unsigned int max_hz, unsigned int mode)
  99 {
 100         struct tegra_spi_slave *spi;
 101
 102         if (!spi_cs_is_valid(bus, cs)) {
 103                 printf("SPI error: unsupported bus %d / chip select %d\n",
 104                        bus, cs);
 105                 return NULL;
 106         }
 107
 108         if (max_hz > TEGRA_SPI_MAX_FREQ) {
 109                 printf("SPI error: unsupported frequency %d Hz. Max frequency"
 110                         " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
 111                 return NULL;
 112         }
 113
 114         spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs);
 115         if (!spi) {
 116                 printf("SPI error: malloc of SPI structure failed\n");
 117                 return NULL;
 118         }
 119         spi->ctrl = &spi_ctrls[bus];
 120         if (!spi->ctrl) {
 121                 printf("SPI error: could not find controller for bus %d\n",
 122                        bus);
 123                 return NULL;
 124         }
 125
 126         if (max_hz < spi->ctrl->freq) {
 127                 debug("%s: limiting frequency from %u to %u\n", __func__,
 128                       spi->ctrl->freq, max_hz);
 129                 spi->ctrl->freq = max_hz;
 130         }
 131         spi->ctrl->mode = mode;
 132
 133         return &spi->slave;
 134 }
 135
 136 void tegra20_spi_free_slave(struct spi_slave *slave)
 137 {
 138         struct tegra_spi_slave *spi = to_tegra_spi(slave);
 139
 140         free(spi);
 141 }
 142
 143 int tegra20_spi_init(int *node_list, int count)
 144 {
 145         struct tegra_spi_ctrl *ctrl;
 146         int i;
 147         int node = 0;
 148         int found = 0;
 149
 150         for (i = 0; i < count; i++) {
 151                 ctrl = &spi_ctrls[i];
 152                 node = node_list[i];
 153
 154                 ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
 155                                                                 node, "reg");
 156                 if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
 157                         debug("%s: no slink register found\n", __func__);
 158                         continue;
 159                 }
 160                 ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
 161                                             "spi-max-frequency", 0);
 162                 if (!ctrl->freq) {
 163                         debug("%s: no slink max frequency found\n", __func__);
 164                         continue;
 165                 }
 166
 167                 ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
 168                 if (ctrl->periph_id == PERIPH_ID_NONE) {
 169                         debug("%s: could not decode periph id\n", __func__);
 170                         continue;
 171                 }
 172                 ctrl->valid = 1;
 173                 found = 1;
 174
 175                 debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
 176                       __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
 177         }
 178         return !found;
 179 }
 180
 181 int tegra20_spi_claim_bus(struct spi_slave *slave)
 182 {
 183         struct tegra_spi_slave *spi = to_tegra_spi(slave);
 184         struct spi_regs *regs = spi->ctrl->regs;
 185         u32 reg;
 186
 187         /* Change SPI clock to correct frequency, PLLP_OUT0 source */
 188         clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
 189                                spi->ctrl->freq);
 190
 191         /* Clear stale status here */
 192         reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
 193                 SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
 194         writel(reg, &regs->status);
 195         debug("%s: STATUS = %08x\n", __func__, readl(&regs->status));
 196
 197         /*
 198          * Use sw-controlled CS, so we can clock in data after ReadID, etc.
 199          */
 200         reg = (spi->ctrl->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
 201         if (spi->ctrl->mode & 2)
 202                 reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
 203         clrsetbits_le32(&regs->command, SPI_CMD_ACTIVE_SCLK_MASK |
 204                 SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
 205         debug("%s: COMMAND = %08x\n", __func__, readl(&regs->command));
 206
 207         /*
 208          * SPI pins on Tegra20 are muxed - change pinmux later due to UART
 209          * issue.
 210          */
 211         pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
 212         pinmux_tristate_disable(PINGRP_LSPI);
 213         pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH);
 214
 215         return 0;
 216 }
 217
 218 void tegra20_spi_cs_activate(struct spi_slave *slave)
 219 {
 220         struct tegra_spi_slave *spi = to_tegra_spi(slave);
 221         struct spi_regs *regs = spi->ctrl->regs;
 222
 223         /* CS is negated on Tegra, so drive a 1 to get a 0 */
 224         setbits_le32(&regs->command, SPI_CMD_CS_VAL);
 225 }
 226
 227 void tegra20_spi_cs_deactivate(struct spi_slave *slave)
 228 {
 229         struct tegra_spi_slave *spi = to_tegra_spi(slave);
 230         struct spi_regs *regs = spi->ctrl->regs;
 231
 232         /* CS is negated on Tegra, so drive a 0 to get a 1 */
 233         clrbits_le32(&regs->command, SPI_CMD_CS_VAL);
 234 }
 235
 236 int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 237                 const void *data_out, void *data_in, unsigned long flags)
 238 {
 239         struct tegra_spi_slave *spi = to_tegra_spi(slave);
 240         struct spi_regs *regs = spi->ctrl->regs;
 241         u32 reg, tmpdout, tmpdin = 0;
 242         const u8 *dout = data_out;
 243         u8 *din = data_in;
 244         int num_bytes;
 245         int ret;
 246
 247         debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
 248               slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen);
 249         if (bitlen % 8)
 250                 return -1;
 251         num_bytes = bitlen / 8;
 252
 253         ret = 0;
 254
 255         reg = readl(&regs->status);
 256         writel(reg, &regs->status);     /* Clear all SPI events via R/W */
 257         debug("spi_xfer entry: STATUS = %08x\n", reg);
 258
 259         reg = readl(&regs->command);
 260         reg |= SPI_CMD_TXEN | SPI_CMD_RXEN;
 261         writel(reg, &regs->command);
 262         debug("spi_xfer: COMMAND = %08x\n", readl(&regs->command));
 263
 264         if (flags & SPI_XFER_BEGIN)
 265                 spi_cs_activate(slave);
 266
 267         /* handle data in 32-bit chunks */
 268         while (num_bytes > 0) {
 269                 int bytes;
 270                 int is_read = 0;
 271                 int tm, i;
 272
 273                 tmpdout = 0;
 274                 bytes = (num_bytes > 4) ?  4 : num_bytes;
 275
 276                 if (dout != NULL) {
 277                         for (i = 0; i < bytes; ++i)
 278                                 tmpdout = (tmpdout << 8) | dout[i];
 279                 }
 280
 281                 num_bytes -= bytes;
 282                 if (dout)
 283                         dout += bytes;
 284
 285                 clrsetbits_le32(&regs->command, SPI_CMD_BIT_LENGTH_MASK,
 286                                 bytes * 8 - 1);
 287                 writel(tmpdout, &regs->tx_fifo);
 288                 setbits_le32(&regs->command, SPI_CMD_GO);
 289
 290                 /*
 291                  * Wait for SPI transmit FIFO to empty, or to time out.
 292                  * The RX FIFO status will be read and cleared last
 293                  */
 294                 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
 295                         u32 status;
 296
 297                         status = readl(&regs->status);
 298
 299                         /* We can exit when we've had both RX and TX activity */
 300                         if (is_read && (status & SPI_STAT_TXF_EMPTY))
 301                                 break;
 302
 303                         if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) !=
 304                                         SPI_STAT_RDY)
 305                                 tm++;
 306
 307                         else if (!(status & SPI_STAT_RXF_EMPTY)) {
 308                                 tmpdin = readl(&regs->rx_fifo);
 309                                 is_read = 1;
 310
 311                                 /* swap bytes read in */
 312                                 if (din != NULL) {
 313                                         for (i = bytes - 1; i >= 0; --i) {
 314                                                 din[i] = tmpdin & 0xff;
 315                                                 tmpdin >>= 8;
 316                                         }
 317                                         din += bytes;
 318                                 }
 319                         }
 320                 }
 321
 322                 if (tm >= SPI_TIMEOUT)
 323                         ret = tm;
 324
 325                 /* clear ACK RDY, etc. bits */
 326                 writel(readl(&regs->status), &regs->status);
 327         }
 328
 329         if (flags & SPI_XFER_END)
 330                 spi_cs_deactivate(slave);
 331
 332         debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
 333                 tmpdin, readl(&regs->status));
 334
 335         if (ret) {
 336                 printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret);
 337                 return -1;
 338         }
 339
 340         return 0;
 341 }