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Merge branch 'master' of git://git.denx.de/u-boot-imx
[people/ms/u-boot.git] / drivers / usb / host / dwc2.c
1 /*
2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <usb.h>
12 #include <malloc.h>
13 #include <memalign.h>
14 #include <phys2bus.h>
15 #include <usbroothubdes.h>
16 #include <wait_bit.h>
17 #include <asm/io.h>
18
19 #include "dwc2.h"
20
21 /* Use only HC channel 0. */
22 #define DWC2_HC_CHANNEL 0
23
24 #define DWC2_STATUS_BUF_SIZE 64
25 #define DWC2_DATA_BUF_SIZE (64 * 1024)
26
27 #define MAX_DEVICE 16
28 #define MAX_ENDPOINT 16
29
30 struct dwc2_priv {
31 #ifdef CONFIG_DM_USB
32 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
33 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
34 #else
35 uint8_t *aligned_buffer;
36 uint8_t *status_buffer;
37 #endif
38 int bulk_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
39 struct dwc2_core_regs *regs;
40 int root_hub_devnum;
41 };
42
43 #ifndef CONFIG_DM_USB
44 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
45 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
46 ARCH_DMA_MINALIGN);
47 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
48 ARCH_DMA_MINALIGN);
49
50 static struct dwc2_priv local;
51 #endif
52
53 /*
54 * DWC2 IP interface
55 */
56
57 /*
58 * Initializes the FSLSPClkSel field of the HCFG register
59 * depending on the PHY type.
60 */
61 static void init_fslspclksel(struct dwc2_core_regs *regs)
62 {
63 uint32_t phyclk;
64
65 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
66 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
67 #else
68 /* High speed PHY running at full speed or high speed */
69 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
70 #endif
71
72 #ifdef CONFIG_DWC2_ULPI_FS_LS
73 uint32_t hwcfg2 = readl(&regs->ghwcfg2);
74 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
75 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
76 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
77 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
78
79 if (hval == 2 && fval == 1)
80 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
81 #endif
82
83 clrsetbits_le32(&regs->host_regs.hcfg,
84 DWC2_HCFG_FSLSPCLKSEL_MASK,
85 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
86 }
87
88 /*
89 * Flush a Tx FIFO.
90 *
91 * @param regs Programming view of DWC_otg controller.
92 * @param num Tx FIFO to flush.
93 */
94 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
95 {
96 int ret;
97
98 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
99 &regs->grstctl);
100 ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_TXFFLSH,
101 false, 1000, false);
102 if (ret)
103 printf("%s: Timeout!\n", __func__);
104
105 /* Wait for 3 PHY Clocks */
106 udelay(1);
107 }
108
109 /*
110 * Flush Rx FIFO.
111 *
112 * @param regs Programming view of DWC_otg controller.
113 */
114 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
115 {
116 int ret;
117
118 writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
119 ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_RXFFLSH,
120 false, 1000, false);
121 if (ret)
122 printf("%s: Timeout!\n", __func__);
123
124 /* Wait for 3 PHY Clocks */
125 udelay(1);
126 }
127
128 /*
129 * Do core a soft reset of the core. Be careful with this because it
130 * resets all the internal state machines of the core.
131 */
132 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
133 {
134 int ret;
135
136 /* Wait for AHB master IDLE state. */
137 ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_AHBIDLE,
138 true, 1000, false);
139 if (ret)
140 printf("%s: Timeout!\n", __func__);
141
142 /* Core Soft Reset */
143 writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
144 ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_CSFTRST,
145 false, 1000, false);
146 if (ret)
147 printf("%s: Timeout!\n", __func__);
148
149 /*
150 * Wait for core to come out of reset.
151 * NOTE: This long sleep is _very_ important, otherwise the core will
152 * not stay in host mode after a connector ID change!
153 */
154 mdelay(100);
155 }
156
157 /*
158 * This function initializes the DWC_otg controller registers for
159 * host mode.
160 *
161 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
162 * request queues. Host channels are reset to ensure that they are ready for
163 * performing transfers.
164 *
165 * @param regs Programming view of DWC_otg controller
166 *
167 */
168 static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
169 {
170 uint32_t nptxfifosize = 0;
171 uint32_t ptxfifosize = 0;
172 uint32_t hprt0 = 0;
173 int i, ret, num_channels;
174
175 /* Restart the Phy Clock */
176 writel(0, &regs->pcgcctl);
177
178 /* Initialize Host Configuration Register */
179 init_fslspclksel(regs);
180 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
181 setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
182 #endif
183
184 /* Configure data FIFO sizes */
185 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
186 if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
187 /* Rx FIFO */
188 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
189
190 /* Non-periodic Tx FIFO */
191 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
192 DWC2_FIFOSIZE_DEPTH_OFFSET;
193 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
194 DWC2_FIFOSIZE_STARTADDR_OFFSET;
195 writel(nptxfifosize, &regs->gnptxfsiz);
196
197 /* Periodic Tx FIFO */
198 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
199 DWC2_FIFOSIZE_DEPTH_OFFSET;
200 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
201 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
202 DWC2_FIFOSIZE_STARTADDR_OFFSET;
203 writel(ptxfifosize, &regs->hptxfsiz);
204 }
205 #endif
206
207 /* Clear Host Set HNP Enable in the OTG Control Register */
208 clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
209
210 /* Make sure the FIFOs are flushed. */
211 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
212 dwc_otg_flush_rx_fifo(regs);
213
214 /* Flush out any leftover queued requests. */
215 num_channels = readl(&regs->ghwcfg2);
216 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
217 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
218 num_channels += 1;
219
220 for (i = 0; i < num_channels; i++)
221 clrsetbits_le32(&regs->hc_regs[i].hcchar,
222 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
223 DWC2_HCCHAR_CHDIS);
224
225 /* Halt all channels to put them into a known state. */
226 for (i = 0; i < num_channels; i++) {
227 clrsetbits_le32(&regs->hc_regs[i].hcchar,
228 DWC2_HCCHAR_EPDIR,
229 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
230 ret = wait_for_bit(__func__, &regs->hc_regs[i].hcchar,
231 DWC2_HCCHAR_CHEN, false, 1000, false);
232 if (ret)
233 printf("%s: Timeout!\n", __func__);
234 }
235
236 /* Turn on the vbus power. */
237 if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
238 hprt0 = readl(&regs->hprt0);
239 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
240 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
241 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
242 hprt0 |= DWC2_HPRT0_PRTPWR;
243 writel(hprt0, &regs->hprt0);
244 }
245 }
246 }
247
248 /*
249 * This function initializes the DWC_otg controller registers and
250 * prepares the core for device mode or host mode operation.
251 *
252 * @param regs Programming view of the DWC_otg controller
253 */
254 static void dwc_otg_core_init(struct dwc2_core_regs *regs)
255 {
256 uint32_t ahbcfg = 0;
257 uint32_t usbcfg = 0;
258 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
259
260 /* Common Initialization */
261 usbcfg = readl(&regs->gusbcfg);
262
263 /* Program the ULPI External VBUS bit if needed */
264 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
265 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
266 #else
267 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
268 #endif
269
270 /* Set external TS Dline pulsing */
271 #ifdef CONFIG_DWC2_TS_DLINE
272 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
273 #else
274 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
275 #endif
276 writel(usbcfg, &regs->gusbcfg);
277
278 /* Reset the Controller */
279 dwc_otg_core_reset(regs);
280
281 /*
282 * This programming sequence needs to happen in FS mode before
283 * any other programming occurs
284 */
285 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
286 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
287 /* If FS mode with FS PHY */
288 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
289
290 /* Reset after a PHY select */
291 dwc_otg_core_reset(regs);
292
293 /*
294 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
295 * Also do this on HNP Dev/Host mode switches (done in dev_init
296 * and host_init).
297 */
298 if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
299 init_fslspclksel(regs);
300
301 #ifdef CONFIG_DWC2_I2C_ENABLE
302 /* Program GUSBCFG.OtgUtmifsSel to I2C */
303 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
304
305 /* Program GI2CCTL.I2CEn */
306 clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
307 DWC2_GI2CCTL_I2CDEVADDR_MASK,
308 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
309 setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
310 #endif
311
312 #else
313 /* High speed PHY. */
314
315 /*
316 * HS PHY parameters. These parameters are preserved during
317 * soft reset so only program the first time. Do a soft reset
318 * immediately after setting phyif.
319 */
320 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
321 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
322
323 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
324 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
325 usbcfg |= DWC2_GUSBCFG_DDRSEL;
326 #else
327 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
328 #endif
329 } else { /* UTMI+ interface */
330 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
331 usbcfg |= DWC2_GUSBCFG_PHYIF;
332 #endif
333 }
334
335 writel(usbcfg, &regs->gusbcfg);
336
337 /* Reset after setting the PHY parameters */
338 dwc_otg_core_reset(regs);
339 #endif
340
341 usbcfg = readl(&regs->gusbcfg);
342 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
343 #ifdef CONFIG_DWC2_ULPI_FS_LS
344 uint32_t hwcfg2 = readl(&regs->ghwcfg2);
345 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
346 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
347 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
348 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
349 if (hval == 2 && fval == 1) {
350 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
351 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
352 }
353 #endif
354 writel(usbcfg, &regs->gusbcfg);
355
356 /* Program the GAHBCFG Register. */
357 switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
358 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
359 break;
360 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
361 while (brst_sz > 1) {
362 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
363 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
364 brst_sz >>= 1;
365 }
366
367 #ifdef CONFIG_DWC2_DMA_ENABLE
368 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
369 #endif
370 break;
371
372 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
373 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
374 #ifdef CONFIG_DWC2_DMA_ENABLE
375 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
376 #endif
377 break;
378 }
379
380 writel(ahbcfg, &regs->gahbcfg);
381
382 /* Program the GUSBCFG register for HNP/SRP. */
383 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
384
385 #ifdef CONFIG_DWC2_IC_USB_CAP
386 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
387 #endif
388 }
389
390 /*
391 * Prepares a host channel for transferring packets to/from a specific
392 * endpoint. The HCCHARn register is set up with the characteristics specified
393 * in _hc. Host channel interrupts that may need to be serviced while this
394 * transfer is in progress are enabled.
395 *
396 * @param regs Programming view of DWC_otg controller
397 * @param hc Information needed to initialize the host channel
398 */
399 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
400 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
401 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
402 {
403 struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
404 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
405 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
406 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
407 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
408 (max_packet << DWC2_HCCHAR_MPS_OFFSET);
409
410 if (dev->speed == USB_SPEED_LOW)
411 hcchar |= DWC2_HCCHAR_LSPDDEV;
412
413 /* Clear old interrupt conditions for this host channel. */
414 writel(0x3fff, &hc_regs->hcint);
415
416 /*
417 * Program the HCCHARn register with the endpoint characteristics
418 * for the current transfer.
419 */
420 writel(hcchar, &hc_regs->hcchar);
421
422 /* Program the HCSPLIT register for SPLITs */
423 writel(0, &hc_regs->hcsplt);
424 }
425
426 /*
427 * DWC2 to USB API interface
428 */
429 /* Direction: In ; Request: Status */
430 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
431 struct usb_device *dev, void *buffer,
432 int txlen, struct devrequest *cmd)
433 {
434 uint32_t hprt0 = 0;
435 uint32_t port_status = 0;
436 uint32_t port_change = 0;
437 int len = 0;
438 int stat = 0;
439
440 switch (cmd->requesttype & ~USB_DIR_IN) {
441 case 0:
442 *(uint16_t *)buffer = cpu_to_le16(1);
443 len = 2;
444 break;
445 case USB_RECIP_INTERFACE:
446 case USB_RECIP_ENDPOINT:
447 *(uint16_t *)buffer = cpu_to_le16(0);
448 len = 2;
449 break;
450 case USB_TYPE_CLASS:
451 *(uint32_t *)buffer = cpu_to_le32(0);
452 len = 4;
453 break;
454 case USB_RECIP_OTHER | USB_TYPE_CLASS:
455 hprt0 = readl(&regs->hprt0);
456 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
457 port_status |= USB_PORT_STAT_CONNECTION;
458 if (hprt0 & DWC2_HPRT0_PRTENA)
459 port_status |= USB_PORT_STAT_ENABLE;
460 if (hprt0 & DWC2_HPRT0_PRTSUSP)
461 port_status |= USB_PORT_STAT_SUSPEND;
462 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
463 port_status |= USB_PORT_STAT_OVERCURRENT;
464 if (hprt0 & DWC2_HPRT0_PRTRST)
465 port_status |= USB_PORT_STAT_RESET;
466 if (hprt0 & DWC2_HPRT0_PRTPWR)
467 port_status |= USB_PORT_STAT_POWER;
468
469 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
470 port_status |= USB_PORT_STAT_LOW_SPEED;
471 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
472 DWC2_HPRT0_PRTSPD_HIGH)
473 port_status |= USB_PORT_STAT_HIGH_SPEED;
474
475 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
476 port_change |= USB_PORT_STAT_C_ENABLE;
477 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
478 port_change |= USB_PORT_STAT_C_CONNECTION;
479 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
480 port_change |= USB_PORT_STAT_C_OVERCURRENT;
481
482 *(uint32_t *)buffer = cpu_to_le32(port_status |
483 (port_change << 16));
484 len = 4;
485 break;
486 default:
487 puts("unsupported root hub command\n");
488 stat = USB_ST_STALLED;
489 }
490
491 dev->act_len = min(len, txlen);
492 dev->status = stat;
493
494 return stat;
495 }
496
497 /* Direction: In ; Request: Descriptor */
498 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
499 void *buffer, int txlen,
500 struct devrequest *cmd)
501 {
502 unsigned char data[32];
503 uint32_t dsc;
504 int len = 0;
505 int stat = 0;
506 uint16_t wValue = cpu_to_le16(cmd->value);
507 uint16_t wLength = cpu_to_le16(cmd->length);
508
509 switch (cmd->requesttype & ~USB_DIR_IN) {
510 case 0:
511 switch (wValue & 0xff00) {
512 case 0x0100: /* device descriptor */
513 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
514 memcpy(buffer, root_hub_dev_des, len);
515 break;
516 case 0x0200: /* configuration descriptor */
517 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
518 memcpy(buffer, root_hub_config_des, len);
519 break;
520 case 0x0300: /* string descriptors */
521 switch (wValue & 0xff) {
522 case 0x00:
523 len = min3(txlen, (int)sizeof(root_hub_str_index0),
524 (int)wLength);
525 memcpy(buffer, root_hub_str_index0, len);
526 break;
527 case 0x01:
528 len = min3(txlen, (int)sizeof(root_hub_str_index1),
529 (int)wLength);
530 memcpy(buffer, root_hub_str_index1, len);
531 break;
532 }
533 break;
534 default:
535 stat = USB_ST_STALLED;
536 }
537 break;
538
539 case USB_TYPE_CLASS:
540 /* Root port config, set 1 port and nothing else. */
541 dsc = 0x00000001;
542
543 data[0] = 9; /* min length; */
544 data[1] = 0x29;
545 data[2] = dsc & RH_A_NDP;
546 data[3] = 0;
547 if (dsc & RH_A_PSM)
548 data[3] |= 0x1;
549 if (dsc & RH_A_NOCP)
550 data[3] |= 0x10;
551 else if (dsc & RH_A_OCPM)
552 data[3] |= 0x8;
553
554 /* corresponds to data[4-7] */
555 data[5] = (dsc & RH_A_POTPGT) >> 24;
556 data[7] = dsc & RH_B_DR;
557 if (data[2] < 7) {
558 data[8] = 0xff;
559 } else {
560 data[0] += 2;
561 data[8] = (dsc & RH_B_DR) >> 8;
562 data[9] = 0xff;
563 data[10] = data[9];
564 }
565
566 len = min3(txlen, (int)data[0], (int)wLength);
567 memcpy(buffer, data, len);
568 break;
569 default:
570 puts("unsupported root hub command\n");
571 stat = USB_ST_STALLED;
572 }
573
574 dev->act_len = min(len, txlen);
575 dev->status = stat;
576
577 return stat;
578 }
579
580 /* Direction: In ; Request: Configuration */
581 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
582 void *buffer, int txlen,
583 struct devrequest *cmd)
584 {
585 int len = 0;
586 int stat = 0;
587
588 switch (cmd->requesttype & ~USB_DIR_IN) {
589 case 0:
590 *(uint8_t *)buffer = 0x01;
591 len = 1;
592 break;
593 default:
594 puts("unsupported root hub command\n");
595 stat = USB_ST_STALLED;
596 }
597
598 dev->act_len = min(len, txlen);
599 dev->status = stat;
600
601 return stat;
602 }
603
604 /* Direction: In */
605 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
606 struct usb_device *dev, void *buffer,
607 int txlen, struct devrequest *cmd)
608 {
609 switch (cmd->request) {
610 case USB_REQ_GET_STATUS:
611 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
612 txlen, cmd);
613 case USB_REQ_GET_DESCRIPTOR:
614 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
615 txlen, cmd);
616 case USB_REQ_GET_CONFIGURATION:
617 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
618 txlen, cmd);
619 default:
620 puts("unsupported root hub command\n");
621 return USB_ST_STALLED;
622 }
623 }
624
625 /* Direction: Out */
626 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
627 struct usb_device *dev,
628 void *buffer, int txlen,
629 struct devrequest *cmd)
630 {
631 struct dwc2_core_regs *regs = priv->regs;
632 int len = 0;
633 int stat = 0;
634 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
635 uint16_t wValue = cpu_to_le16(cmd->value);
636
637 switch (bmrtype_breq & ~USB_DIR_IN) {
638 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
639 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
640 break;
641
642 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
643 switch (wValue) {
644 case USB_PORT_FEAT_C_CONNECTION:
645 setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
646 break;
647 }
648 break;
649
650 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
651 switch (wValue) {
652 case USB_PORT_FEAT_SUSPEND:
653 break;
654
655 case USB_PORT_FEAT_RESET:
656 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
657 DWC2_HPRT0_PRTCONNDET |
658 DWC2_HPRT0_PRTENCHNG |
659 DWC2_HPRT0_PRTOVRCURRCHNG,
660 DWC2_HPRT0_PRTRST);
661 mdelay(50);
662 clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
663 break;
664
665 case USB_PORT_FEAT_POWER:
666 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
667 DWC2_HPRT0_PRTCONNDET |
668 DWC2_HPRT0_PRTENCHNG |
669 DWC2_HPRT0_PRTOVRCURRCHNG,
670 DWC2_HPRT0_PRTRST);
671 break;
672
673 case USB_PORT_FEAT_ENABLE:
674 break;
675 }
676 break;
677 case (USB_REQ_SET_ADDRESS << 8):
678 priv->root_hub_devnum = wValue;
679 break;
680 case (USB_REQ_SET_CONFIGURATION << 8):
681 break;
682 default:
683 puts("unsupported root hub command\n");
684 stat = USB_ST_STALLED;
685 }
686
687 len = min(len, txlen);
688
689 dev->act_len = len;
690 dev->status = stat;
691
692 return stat;
693 }
694
695 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
696 unsigned long pipe, void *buffer, int txlen,
697 struct devrequest *cmd)
698 {
699 int stat = 0;
700
701 if (usb_pipeint(pipe)) {
702 puts("Root-Hub submit IRQ: NOT implemented\n");
703 return 0;
704 }
705
706 if (cmd->requesttype & USB_DIR_IN)
707 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
708 else
709 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
710
711 mdelay(1);
712
713 return stat;
714 }
715
716 int wait_for_chhltd(struct dwc2_core_regs *regs, uint32_t *sub, int *toggle,
717 bool ignore_ack)
718 {
719 uint32_t hcint_comp_hlt_ack = DWC2_HCINT_XFERCOMP | DWC2_HCINT_CHHLTD;
720 struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
721 int ret;
722 uint32_t hcint, hctsiz;
723
724 ret = wait_for_bit(__func__, &hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
725 1000, false);
726 if (ret)
727 return ret;
728
729 hcint = readl(&hc_regs->hcint);
730 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
731 return -EAGAIN;
732 if (ignore_ack)
733 hcint &= ~DWC2_HCINT_ACK;
734 else
735 hcint_comp_hlt_ack |= DWC2_HCINT_ACK;
736 if (hcint != hcint_comp_hlt_ack) {
737 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
738 return -EINVAL;
739 }
740
741 hctsiz = readl(&hc_regs->hctsiz);
742 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
743 DWC2_HCTSIZ_XFERSIZE_OFFSET;
744 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
745
746 debug("%s: sub=%u toggle=%d\n", __func__, *sub, *toggle);
747
748 return 0;
749 }
750
751 static int dwc2_eptype[] = {
752 DWC2_HCCHAR_EPTYPE_ISOC,
753 DWC2_HCCHAR_EPTYPE_INTR,
754 DWC2_HCCHAR_EPTYPE_CONTROL,
755 DWC2_HCCHAR_EPTYPE_BULK,
756 };
757
758 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
759 unsigned long pipe, int *pid, int in, void *buffer, int len,
760 bool ignore_ack)
761 {
762 struct dwc2_core_regs *regs = priv->regs;
763 struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
764 int devnum = usb_pipedevice(pipe);
765 int ep = usb_pipeendpoint(pipe);
766 int max = usb_maxpacket(dev, pipe);
767 int eptype = dwc2_eptype[usb_pipetype(pipe)];
768 int done = 0;
769 int ret = 0;
770 uint32_t sub;
771 uint32_t xfer_len;
772 uint32_t num_packets;
773 int stop_transfer = 0;
774
775 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
776 in, len);
777
778 do {
779 /* Initialize channel */
780 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
781 eptype, max);
782
783 xfer_len = len - done;
784 if (xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
785 xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE - max + 1;
786 if (xfer_len > DWC2_DATA_BUF_SIZE)
787 xfer_len = DWC2_DATA_BUF_SIZE - max + 1;
788
789 /* Make sure that xfer_len is a multiple of max packet size. */
790 if (xfer_len > 0) {
791 num_packets = (xfer_len + max - 1) / max;
792 if (num_packets > CONFIG_DWC2_MAX_PACKET_COUNT) {
793 num_packets = CONFIG_DWC2_MAX_PACKET_COUNT;
794 xfer_len = num_packets * max;
795 }
796 } else {
797 num_packets = 1;
798 }
799
800 if (in)
801 xfer_len = num_packets * max;
802
803 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
804 *pid, xfer_len, num_packets);
805
806 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
807 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
808 (*pid << DWC2_HCTSIZ_PID_OFFSET),
809 &hc_regs->hctsiz);
810
811 if (!in && xfer_len) {
812 memcpy(priv->aligned_buffer, (char *)buffer + done,
813 xfer_len);
814
815 flush_dcache_range((unsigned long)priv->aligned_buffer,
816 (unsigned long)((void *)priv->aligned_buffer +
817 roundup(xfer_len, ARCH_DMA_MINALIGN)));
818 }
819
820 writel(phys_to_bus((unsigned long)priv->aligned_buffer),
821 &hc_regs->hcdma);
822
823 /* Set host channel enable after all other setup is complete. */
824 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
825 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
826 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
827 DWC2_HCCHAR_CHEN);
828
829 ret = wait_for_chhltd(regs, &sub, pid, ignore_ack);
830 if (ret)
831 break;
832
833 if (in) {
834 xfer_len -= sub;
835
836 invalidate_dcache_range((unsigned long)priv->aligned_buffer,
837 (unsigned long)((void *)priv->aligned_buffer +
838 roundup(xfer_len, ARCH_DMA_MINALIGN)));
839
840 memcpy(buffer + done, priv->aligned_buffer, xfer_len);
841 if (sub)
842 stop_transfer = 1;
843 }
844
845 done += xfer_len;
846
847 } while ((done < len) && !stop_transfer);
848
849 writel(0, &hc_regs->hcintmsk);
850 writel(0xFFFFFFFF, &hc_regs->hcint);
851
852 dev->status = 0;
853 dev->act_len = done;
854
855 return ret;
856 }
857
858 /* U-Boot USB transmission interface */
859 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
860 unsigned long pipe, void *buffer, int len)
861 {
862 int devnum = usb_pipedevice(pipe);
863 int ep = usb_pipeendpoint(pipe);
864
865 if (devnum == priv->root_hub_devnum) {
866 dev->status = 0;
867 return -EINVAL;
868 }
869
870 return chunk_msg(priv, dev, pipe, &priv->bulk_data_toggle[devnum][ep],
871 usb_pipein(pipe), buffer, len, true);
872 }
873
874 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
875 unsigned long pipe, void *buffer, int len,
876 struct devrequest *setup)
877 {
878 int devnum = usb_pipedevice(pipe);
879 int pid, ret, act_len;
880 /* For CONTROL endpoint pid should start with DATA1 */
881 int status_direction;
882
883 if (devnum == priv->root_hub_devnum) {
884 dev->status = 0;
885 dev->speed = USB_SPEED_HIGH;
886 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
887 setup);
888 }
889
890 pid = DWC2_HC_PID_SETUP;
891 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8, true);
892 if (ret)
893 return ret;
894
895 if (buffer) {
896 pid = DWC2_HC_PID_DATA1;
897 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe), buffer,
898 len, false);
899 if (ret)
900 return ret;
901 act_len = dev->act_len;
902 } /* End of DATA stage */
903 else
904 act_len = 0;
905
906 /* STATUS stage */
907 if ((len == 0) || usb_pipeout(pipe))
908 status_direction = 1;
909 else
910 status_direction = 0;
911
912 pid = DWC2_HC_PID_DATA1;
913 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
914 priv->status_buffer, 0, false);
915 if (ret)
916 return ret;
917
918 dev->act_len = act_len;
919
920 return 0;
921 }
922
923 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
924 unsigned long pipe, void *buffer, int len, int interval)
925 {
926 unsigned long timeout;
927 int ret;
928
929 /* FIXME: what is interval? */
930
931 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
932 for (;;) {
933 if (get_timer(0) > timeout) {
934 printf("Timeout poll on interrupt endpoint\n");
935 return -ETIMEDOUT;
936 }
937 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
938 if (ret != -EAGAIN)
939 return ret;
940 }
941 }
942
943 static int dwc2_init_common(struct dwc2_priv *priv)
944 {
945 struct dwc2_core_regs *regs = priv->regs;
946 uint32_t snpsid;
947 int i, j;
948
949 snpsid = readl(&regs->gsnpsid);
950 printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
951
952 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
953 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
954 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
955 return -ENODEV;
956 }
957
958 dwc_otg_core_init(regs);
959 dwc_otg_core_host_init(regs);
960
961 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
962 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
963 DWC2_HPRT0_PRTOVRCURRCHNG,
964 DWC2_HPRT0_PRTRST);
965 mdelay(50);
966 clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
967 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
968 DWC2_HPRT0_PRTRST);
969
970 for (i = 0; i < MAX_DEVICE; i++) {
971 for (j = 0; j < MAX_ENDPOINT; j++)
972 priv->bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0;
973 }
974
975 return 0;
976 }
977
978 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
979 {
980 /* Put everything in reset. */
981 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
982 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
983 DWC2_HPRT0_PRTOVRCURRCHNG,
984 DWC2_HPRT0_PRTRST);
985 }
986
987 #ifndef CONFIG_DM_USB
988 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
989 int len, struct devrequest *setup)
990 {
991 return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
992 }
993
994 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
995 int len)
996 {
997 return _submit_bulk_msg(&local, dev, pipe, buffer, len);
998 }
999
1000 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1001 int len, int interval)
1002 {
1003 return _submit_int_msg(&local, dev, pipe, buffer, len, interval);
1004 }
1005
1006 /* U-Boot USB control interface */
1007 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1008 {
1009 struct dwc2_priv *priv = &local;
1010
1011 memset(priv, '\0', sizeof(*priv));
1012 priv->root_hub_devnum = 0;
1013 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1014 priv->aligned_buffer = aligned_buffer_addr;
1015 priv->status_buffer = status_buffer_addr;
1016
1017 /* board-dependant init */
1018 if (board_usb_init(index, USB_INIT_HOST))
1019 return -1;
1020
1021 return dwc2_init_common(priv);
1022 }
1023
1024 int usb_lowlevel_stop(int index)
1025 {
1026 dwc2_uninit_common(local.regs);
1027
1028 return 0;
1029 }
1030 #endif
1031
1032 #ifdef CONFIG_DM_USB
1033 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1034 unsigned long pipe, void *buffer, int length,
1035 struct devrequest *setup)
1036 {
1037 struct dwc2_priv *priv = dev_get_priv(dev);
1038
1039 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1040 dev->name, udev, udev->dev->name, udev->portnr);
1041
1042 return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1043 }
1044
1045 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1046 unsigned long pipe, void *buffer, int length)
1047 {
1048 struct dwc2_priv *priv = dev_get_priv(dev);
1049
1050 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1051
1052 return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1053 }
1054
1055 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1056 unsigned long pipe, void *buffer, int length,
1057 int interval)
1058 {
1059 struct dwc2_priv *priv = dev_get_priv(dev);
1060
1061 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1062
1063 return _submit_int_msg(priv, udev, pipe, buffer, length, interval);
1064 }
1065
1066 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1067 {
1068 struct dwc2_priv *priv = dev_get_priv(dev);
1069 fdt_addr_t addr;
1070
1071 addr = dev_get_addr(dev);
1072 if (addr == FDT_ADDR_T_NONE)
1073 return -EINVAL;
1074 priv->regs = (struct dwc2_core_regs *)addr;
1075
1076 return 0;
1077 }
1078
1079 static int dwc2_usb_probe(struct udevice *dev)
1080 {
1081 struct dwc2_priv *priv = dev_get_priv(dev);
1082
1083 return dwc2_init_common(priv);
1084 }
1085
1086 static int dwc2_usb_remove(struct udevice *dev)
1087 {
1088 struct dwc2_priv *priv = dev_get_priv(dev);
1089
1090 dwc2_uninit_common(priv->regs);
1091
1092 return 0;
1093 }
1094
1095 struct dm_usb_ops dwc2_usb_ops = {
1096 .control = dwc2_submit_control_msg,
1097 .bulk = dwc2_submit_bulk_msg,
1098 .interrupt = dwc2_submit_int_msg,
1099 };
1100
1101 static const struct udevice_id dwc2_usb_ids[] = {
1102 { .compatible = "brcm,bcm2835-usb" },
1103 { .compatible = "snps,dwc2" },
1104 { }
1105 };
1106
1107 U_BOOT_DRIVER(usb_dwc2) = {
1108 .name = "dwc2_usb",
1109 .id = UCLASS_USB,
1110 .of_match = dwc2_usb_ids,
1111 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1112 .probe = dwc2_usb_probe,
1113 .remove = dwc2_usb_remove,
1114 .ops = &dwc2_usb_ops,
1115 .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1116 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1117 };
1118 #endif
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