2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <usbroothubdes.h>
17 /* Use only HC channel 0. */
18 #define DWC2_HC_CHANNEL 0
20 #define DWC2_STATUS_BUF_SIZE 64
21 #define DWC2_DATA_BUF_SIZE (64 * 1024)
23 /* We need doubleword-aligned buffers for DMA transfers */
24 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer
, DWC2_DATA_BUF_SIZE
, 8);
25 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer
, DWC2_STATUS_BUF_SIZE
, 8);
28 #define MAX_ENDPOINT 16
29 static int bulk_data_toggle
[MAX_DEVICE
][MAX_ENDPOINT
];
31 static int root_hub_devnum
;
33 static struct dwc2_core_regs
*regs
=
34 (struct dwc2_core_regs
*)CONFIG_USB_DWC2_REG_ADDR
;
39 static int wait_for_bit(void *reg
, const uint32_t mask
, bool set
)
41 unsigned int timeout
= 1000000;
49 if ((val
& mask
) == mask
)
55 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
56 __func__
, reg
, mask
, set
);
62 * Initializes the FSLSPClkSel field of the HCFG register
63 * depending on the PHY type.
65 static void init_fslspclksel(struct dwc2_core_regs
*regs
)
69 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
70 phyclk
= DWC2_HCFG_FSLSPCLKSEL_48_MHZ
; /* Full speed PHY */
72 /* High speed PHY running at full speed or high speed */
73 phyclk
= DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ
;
76 #ifdef CONFIG_DWC2_ULPI_FS_LS
77 uint32_t hwcfg2
= readl(®s
->ghwcfg2
);
78 uint32_t hval
= (ghwcfg2
& DWC2_HWCFG2_HS_PHY_TYPE_MASK
) >>
79 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET
;
80 uint32_t fval
= (ghwcfg2
& DWC2_HWCFG2_FS_PHY_TYPE_MASK
) >>
81 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET
;
83 if (hval
== 2 && fval
== 1)
84 phyclk
= DWC2_HCFG_FSLSPCLKSEL_48_MHZ
; /* Full speed PHY */
87 clrsetbits_le32(®s
->host_regs
.hcfg
,
88 DWC2_HCFG_FSLSPCLKSEL_MASK
,
89 phyclk
<< DWC2_HCFG_FSLSPCLKSEL_OFFSET
);
95 * @param regs Programming view of DWC_otg controller.
96 * @param num Tx FIFO to flush.
98 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs
*regs
, const int num
)
102 writel(DWC2_GRSTCTL_TXFFLSH
| (num
<< DWC2_GRSTCTL_TXFNUM_OFFSET
),
104 ret
= wait_for_bit(®s
->grstctl
, DWC2_GRSTCTL_TXFFLSH
, 0);
106 printf("%s: Timeout!\n", __func__
);
108 /* Wait for 3 PHY Clocks */
115 * @param regs Programming view of DWC_otg controller.
117 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs
*regs
)
121 writel(DWC2_GRSTCTL_RXFFLSH
, ®s
->grstctl
);
122 ret
= wait_for_bit(®s
->grstctl
, DWC2_GRSTCTL_RXFFLSH
, 0);
124 printf("%s: Timeout!\n", __func__
);
126 /* Wait for 3 PHY Clocks */
131 * Do core a soft reset of the core. Be careful with this because it
132 * resets all the internal state machines of the core.
134 static void dwc_otg_core_reset(struct dwc2_core_regs
*regs
)
138 /* Wait for AHB master IDLE state. */
139 ret
= wait_for_bit(®s
->grstctl
, DWC2_GRSTCTL_AHBIDLE
, 1);
141 printf("%s: Timeout!\n", __func__
);
143 /* Core Soft Reset */
144 writel(DWC2_GRSTCTL_CSFTRST
, ®s
->grstctl
);
145 ret
= wait_for_bit(®s
->grstctl
, DWC2_GRSTCTL_CSFTRST
, 0);
147 printf("%s: Timeout!\n", __func__
);
150 * Wait for core to come out of reset.
151 * NOTE: This long sleep is _very_ important, otherwise the core will
152 * not stay in host mode after a connector ID change!
158 * This function initializes the DWC_otg controller registers for
161 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
162 * request queues. Host channels are reset to ensure that they are ready for
163 * performing transfers.
165 * @param regs Programming view of DWC_otg controller
168 static void dwc_otg_core_host_init(struct dwc2_core_regs
*regs
)
170 uint32_t nptxfifosize
= 0;
171 uint32_t ptxfifosize
= 0;
173 int i
, ret
, num_channels
;
175 /* Restart the Phy Clock */
176 writel(0, ®s
->pcgcctl
);
178 /* Initialize Host Configuration Register */
179 init_fslspclksel(regs
);
180 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
181 setbits_le32(®s
->host_regs
.hcfg
, DWC2_HCFG_FSLSSUPP
);
184 /* Configure data FIFO sizes */
185 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
186 if (readl(®s
->ghwcfg2
) & DWC2_HWCFG2_DYNAMIC_FIFO
) {
188 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE
, ®s
->grxfsiz
);
190 /* Non-periodic Tx FIFO */
191 nptxfifosize
|= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE
<<
192 DWC2_FIFOSIZE_DEPTH_OFFSET
;
193 nptxfifosize
|= CONFIG_DWC2_HOST_RX_FIFO_SIZE
<<
194 DWC2_FIFOSIZE_STARTADDR_OFFSET
;
195 writel(nptxfifosize
, ®s
->gnptxfsiz
);
197 /* Periodic Tx FIFO */
198 ptxfifosize
|= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE
<<
199 DWC2_FIFOSIZE_DEPTH_OFFSET
;
200 ptxfifosize
|= (CONFIG_DWC2_HOST_RX_FIFO_SIZE
+
201 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE
) <<
202 DWC2_FIFOSIZE_STARTADDR_OFFSET
;
203 writel(ptxfifosize
, ®s
->hptxfsiz
);
207 /* Clear Host Set HNP Enable in the OTG Control Register */
208 clrbits_le32(®s
->gotgctl
, DWC2_GOTGCTL_HSTSETHNPEN
);
210 /* Make sure the FIFOs are flushed. */
211 dwc_otg_flush_tx_fifo(regs
, 0x10); /* All Tx FIFOs */
212 dwc_otg_flush_rx_fifo(regs
);
214 /* Flush out any leftover queued requests. */
215 num_channels
= readl(®s
->ghwcfg2
);
216 num_channels
&= DWC2_HWCFG2_NUM_HOST_CHAN_MASK
;
217 num_channels
>>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET
;
220 for (i
= 0; i
< num_channels
; i
++)
221 clrsetbits_le32(®s
->hc_regs
[i
].hcchar
,
222 DWC2_HCCHAR_CHEN
| DWC2_HCCHAR_EPDIR
,
225 /* Halt all channels to put them into a known state. */
226 for (i
= 0; i
< num_channels
; i
++) {
227 clrsetbits_le32(®s
->hc_regs
[i
].hcchar
,
229 DWC2_HCCHAR_CHEN
| DWC2_HCCHAR_CHDIS
);
230 ret
= wait_for_bit(®s
->hc_regs
[i
].hcchar
,
231 DWC2_HCCHAR_CHEN
, 0);
233 printf("%s: Timeout!\n", __func__
);
236 /* Turn on the vbus power. */
237 if (readl(®s
->gintsts
) & DWC2_GINTSTS_CURMODE_HOST
) {
238 hprt0
= readl(®s
->hprt0
);
239 hprt0
&= ~(DWC2_HPRT0_PRTENA
| DWC2_HPRT0_PRTCONNDET
);
240 hprt0
&= ~(DWC2_HPRT0_PRTENCHNG
| DWC2_HPRT0_PRTOVRCURRCHNG
);
241 if (!(hprt0
& DWC2_HPRT0_PRTPWR
)) {
242 hprt0
|= DWC2_HPRT0_PRTPWR
;
243 writel(hprt0
, ®s
->hprt0
);
249 * This function initializes the DWC_otg controller registers and
250 * prepares the core for device mode or host mode operation.
252 * @param regs Programming view of the DWC_otg controller
254 static void dwc_otg_core_init(struct dwc2_core_regs
*regs
)
258 uint8_t brst_sz
= CONFIG_DWC2_DMA_BURST_SIZE
;
260 /* Common Initialization */
261 usbcfg
= readl(®s
->gusbcfg
);
263 /* Program the ULPI External VBUS bit if needed */
264 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
265 usbcfg
|= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV
;
267 usbcfg
&= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV
;
270 /* Set external TS Dline pulsing */
271 #ifdef CONFIG_DWC2_TS_DLINE
272 usbcfg
|= DWC2_GUSBCFG_TERM_SEL_DL_PULSE
;
274 usbcfg
&= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE
;
276 writel(usbcfg
, ®s
->gusbcfg
);
278 /* Reset the Controller */
279 dwc_otg_core_reset(regs
);
282 * This programming sequence needs to happen in FS mode before
283 * any other programming occurs
285 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
286 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
287 /* If FS mode with FS PHY */
288 setbits_le32(®s
->gusbcfg
, DWC2_GUSBCFG_PHYSEL
);
290 /* Reset after a PHY select */
291 dwc_otg_core_reset(regs
);
294 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
295 * Also do this on HNP Dev/Host mode switches (done in dev_init
298 if (readl(®s
->gintsts
) & DWC2_GINTSTS_CURMODE_HOST
)
299 init_fslspclksel(regs
);
301 #ifdef CONFIG_DWC2_I2C_ENABLE
302 /* Program GUSBCFG.OtgUtmifsSel to I2C */
303 setbits_le32(®s
->gusbcfg
, DWC2_GUSBCFG_OTGUTMIFSSEL
);
305 /* Program GI2CCTL.I2CEn */
306 clrsetbits_le32(®s
->gi2cctl
, DWC2_GI2CCTL_I2CEN
|
307 DWC2_GI2CCTL_I2CDEVADDR_MASK
,
308 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET
);
309 setbits_le32(®s
->gi2cctl
, DWC2_GI2CCTL_I2CEN
);
313 /* High speed PHY. */
316 * HS PHY parameters. These parameters are preserved during
317 * soft reset so only program the first time. Do a soft reset
318 * immediately after setting phyif.
320 usbcfg
&= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL
| DWC2_GUSBCFG_PHYIF
);
321 usbcfg
|= CONFIG_DWC2_PHY_TYPE
<< DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET
;
323 if (usbcfg
& DWC2_GUSBCFG_ULPI_UTMI_SEL
) { /* ULPI interface */
324 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
325 usbcfg
|= DWC2_GUSBCFG_DDRSEL
;
327 usbcfg
&= ~DWC2_GUSBCFG_DDRSEL
;
329 } else { /* UTMI+ interface */
330 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
331 usbcfg
|= DWC2_GUSBCFG_PHYIF
;
335 writel(usbcfg
, ®s
->gusbcfg
);
337 /* Reset after setting the PHY parameters */
338 dwc_otg_core_reset(regs
);
341 usbcfg
= readl(®s
->gusbcfg
);
342 usbcfg
&= ~(DWC2_GUSBCFG_ULPI_FSLS
| DWC2_GUSBCFG_ULPI_CLK_SUS_M
);
343 #ifdef CONFIG_DWC2_ULPI_FS_LS
344 uint32_t hwcfg2
= readl(®s
->ghwcfg2
);
345 uint32_t hval
= (ghwcfg2
& DWC2_HWCFG2_HS_PHY_TYPE_MASK
) >>
346 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET
;
347 uint32_t fval
= (ghwcfg2
& DWC2_HWCFG2_FS_PHY_TYPE_MASK
) >>
348 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET
;
349 if (hval
== 2 && fval
== 1) {
350 usbcfg
|= DWC2_GUSBCFG_ULPI_FSLS
;
351 usbcfg
|= DWC2_GUSBCFG_ULPI_CLK_SUS_M
;
354 writel(usbcfg
, ®s
->gusbcfg
);
356 /* Program the GAHBCFG Register. */
357 switch (readl(®s
->ghwcfg2
) & DWC2_HWCFG2_ARCHITECTURE_MASK
) {
358 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY
:
360 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA
:
361 while (brst_sz
> 1) {
362 ahbcfg
|= ahbcfg
+ (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET
);
363 ahbcfg
&= DWC2_GAHBCFG_HBURSTLEN_MASK
;
367 #ifdef CONFIG_DWC2_DMA_ENABLE
368 ahbcfg
|= DWC2_GAHBCFG_DMAENABLE
;
372 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA
:
373 ahbcfg
|= DWC2_GAHBCFG_HBURSTLEN_INCR4
;
374 #ifdef CONFIG_DWC2_DMA_ENABLE
375 ahbcfg
|= DWC2_GAHBCFG_DMAENABLE
;
380 writel(ahbcfg
, ®s
->gahbcfg
);
382 /* Program the GUSBCFG register for HNP/SRP. */
383 setbits_le32(®s
->gusbcfg
, DWC2_GUSBCFG_HNPCAP
| DWC2_GUSBCFG_SRPCAP
);
385 #ifdef CONFIG_DWC2_IC_USB_CAP
386 setbits_le32(®s
->gusbcfg
, DWC2_GUSBCFG_IC_USB_CAP
);
391 * Prepares a host channel for transferring packets to/from a specific
392 * endpoint. The HCCHARn register is set up with the characteristics specified
393 * in _hc. Host channel interrupts that may need to be serviced while this
394 * transfer is in progress are enabled.
396 * @param regs Programming view of DWC_otg controller
397 * @param hc Information needed to initialize the host channel
399 static void dwc_otg_hc_init(struct dwc2_core_regs
*regs
, uint8_t hc_num
,
400 uint8_t dev_addr
, uint8_t ep_num
, uint8_t ep_is_in
,
401 uint8_t ep_type
, uint16_t max_packet
)
403 struct dwc2_hc_regs
*hc_regs
= ®s
->hc_regs
[hc_num
];
404 const uint32_t hcchar
= (dev_addr
<< DWC2_HCCHAR_DEVADDR_OFFSET
) |
405 (ep_num
<< DWC2_HCCHAR_EPNUM_OFFSET
) |
406 (ep_is_in
<< DWC2_HCCHAR_EPDIR_OFFSET
) |
407 (ep_type
<< DWC2_HCCHAR_EPTYPE_OFFSET
) |
408 (max_packet
<< DWC2_HCCHAR_MPS_OFFSET
);
410 /* Clear old interrupt conditions for this host channel. */
411 writel(0x3fff, &hc_regs
->hcint
);
414 * Program the HCCHARn register with the endpoint characteristics
415 * for the current transfer.
417 writel(hcchar
, &hc_regs
->hcchar
);
419 /* Program the HCSPLIT register for SPLITs */
420 writel(0, &hc_regs
->hcsplt
);
424 * DWC2 to USB API interface
426 /* Direction: In ; Request: Status */
427 static int dwc_otg_submit_rh_msg_in_status(struct usb_device
*dev
, void *buffer
,
428 int txlen
, struct devrequest
*cmd
)
431 uint32_t port_status
= 0;
432 uint32_t port_change
= 0;
436 switch (cmd
->requesttype
& ~USB_DIR_IN
) {
438 *(uint16_t *)buffer
= cpu_to_le16(1);
441 case USB_RECIP_INTERFACE
:
442 case USB_RECIP_ENDPOINT
:
443 *(uint16_t *)buffer
= cpu_to_le16(0);
447 *(uint32_t *)buffer
= cpu_to_le32(0);
450 case USB_RECIP_OTHER
| USB_TYPE_CLASS
:
451 hprt0
= readl(®s
->hprt0
);
452 if (hprt0
& DWC2_HPRT0_PRTCONNSTS
)
453 port_status
|= USB_PORT_STAT_CONNECTION
;
454 if (hprt0
& DWC2_HPRT0_PRTENA
)
455 port_status
|= USB_PORT_STAT_ENABLE
;
456 if (hprt0
& DWC2_HPRT0_PRTSUSP
)
457 port_status
|= USB_PORT_STAT_SUSPEND
;
458 if (hprt0
& DWC2_HPRT0_PRTOVRCURRACT
)
459 port_status
|= USB_PORT_STAT_OVERCURRENT
;
460 if (hprt0
& DWC2_HPRT0_PRTRST
)
461 port_status
|= USB_PORT_STAT_RESET
;
462 if (hprt0
& DWC2_HPRT0_PRTPWR
)
463 port_status
|= USB_PORT_STAT_POWER
;
465 port_status
|= USB_PORT_STAT_HIGH_SPEED
;
467 if (hprt0
& DWC2_HPRT0_PRTENCHNG
)
468 port_change
|= USB_PORT_STAT_C_ENABLE
;
469 if (hprt0
& DWC2_HPRT0_PRTCONNDET
)
470 port_change
|= USB_PORT_STAT_C_CONNECTION
;
471 if (hprt0
& DWC2_HPRT0_PRTOVRCURRCHNG
)
472 port_change
|= USB_PORT_STAT_C_OVERCURRENT
;
474 *(uint32_t *)buffer
= cpu_to_le32(port_status
|
475 (port_change
<< 16));
479 puts("unsupported root hub command\n");
480 stat
= USB_ST_STALLED
;
483 dev
->act_len
= min(len
, txlen
);
489 /* Direction: In ; Request: Descriptor */
490 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device
*dev
,
491 void *buffer
, int txlen
,
492 struct devrequest
*cmd
)
494 unsigned char data
[32];
498 uint16_t wValue
= cpu_to_le16(cmd
->value
);
499 uint16_t wLength
= cpu_to_le16(cmd
->length
);
501 switch (cmd
->requesttype
& ~USB_DIR_IN
) {
503 switch (wValue
& 0xff00) {
504 case 0x0100: /* device descriptor */
505 len
= min3(txlen
, (int)sizeof(root_hub_dev_des
), (int)wLength
);
506 memcpy(buffer
, root_hub_dev_des
, len
);
508 case 0x0200: /* configuration descriptor */
509 len
= min3(txlen
, (int)sizeof(root_hub_config_des
), (int)wLength
);
510 memcpy(buffer
, root_hub_config_des
, len
);
512 case 0x0300: /* string descriptors */
513 switch (wValue
& 0xff) {
515 len
= min3(txlen
, (int)sizeof(root_hub_str_index0
),
517 memcpy(buffer
, root_hub_str_index0
, len
);
520 len
= min3(txlen
, (int)sizeof(root_hub_str_index1
),
522 memcpy(buffer
, root_hub_str_index1
, len
);
527 stat
= USB_ST_STALLED
;
532 /* Root port config, set 1 port and nothing else. */
535 data
[0] = 9; /* min length; */
537 data
[2] = dsc
& RH_A_NDP
;
543 else if (dsc
& RH_A_OCPM
)
546 /* corresponds to data[4-7] */
547 data
[5] = (dsc
& RH_A_POTPGT
) >> 24;
548 data
[7] = dsc
& RH_B_DR
;
553 data
[8] = (dsc
& RH_B_DR
) >> 8;
558 len
= min3(txlen
, (int)data
[0], (int)wLength
);
559 memcpy(buffer
, data
, len
);
562 puts("unsupported root hub command\n");
563 stat
= USB_ST_STALLED
;
566 dev
->act_len
= min(len
, txlen
);
572 /* Direction: In ; Request: Configuration */
573 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device
*dev
,
574 void *buffer
, int txlen
,
575 struct devrequest
*cmd
)
580 switch (cmd
->requesttype
& ~USB_DIR_IN
) {
582 *(uint8_t *)buffer
= 0x01;
586 puts("unsupported root hub command\n");
587 stat
= USB_ST_STALLED
;
590 dev
->act_len
= min(len
, txlen
);
597 static int dwc_otg_submit_rh_msg_in(struct usb_device
*dev
,
598 void *buffer
, int txlen
,
599 struct devrequest
*cmd
)
601 switch (cmd
->request
) {
602 case USB_REQ_GET_STATUS
:
603 return dwc_otg_submit_rh_msg_in_status(dev
, buffer
,
605 case USB_REQ_GET_DESCRIPTOR
:
606 return dwc_otg_submit_rh_msg_in_descriptor(dev
, buffer
,
608 case USB_REQ_GET_CONFIGURATION
:
609 return dwc_otg_submit_rh_msg_in_configuration(dev
, buffer
,
612 puts("unsupported root hub command\n");
613 return USB_ST_STALLED
;
618 static int dwc_otg_submit_rh_msg_out(struct usb_device
*dev
,
619 void *buffer
, int txlen
,
620 struct devrequest
*cmd
)
624 uint16_t bmrtype_breq
= cmd
->requesttype
| (cmd
->request
<< 8);
625 uint16_t wValue
= cpu_to_le16(cmd
->value
);
627 switch (bmrtype_breq
& ~USB_DIR_IN
) {
628 case (USB_REQ_CLEAR_FEATURE
<< 8) | USB_RECIP_ENDPOINT
:
629 case (USB_REQ_CLEAR_FEATURE
<< 8) | USB_TYPE_CLASS
:
632 case (USB_REQ_CLEAR_FEATURE
<< 8) | USB_RECIP_OTHER
| USB_TYPE_CLASS
:
634 case USB_PORT_FEAT_C_CONNECTION
:
635 setbits_le32(®s
->hprt0
, DWC2_HPRT0_PRTCONNDET
);
640 case (USB_REQ_SET_FEATURE
<< 8) | USB_RECIP_OTHER
| USB_TYPE_CLASS
:
642 case USB_PORT_FEAT_SUSPEND
:
645 case USB_PORT_FEAT_RESET
:
646 clrsetbits_le32(®s
->hprt0
, DWC2_HPRT0_PRTENA
|
647 DWC2_HPRT0_PRTCONNDET
|
648 DWC2_HPRT0_PRTENCHNG
|
649 DWC2_HPRT0_PRTOVRCURRCHNG
,
652 clrbits_le32(®s
->hprt0
, DWC2_HPRT0_PRTRST
);
655 case USB_PORT_FEAT_POWER
:
656 clrsetbits_le32(®s
->hprt0
, DWC2_HPRT0_PRTENA
|
657 DWC2_HPRT0_PRTCONNDET
|
658 DWC2_HPRT0_PRTENCHNG
|
659 DWC2_HPRT0_PRTOVRCURRCHNG
,
663 case USB_PORT_FEAT_ENABLE
:
667 case (USB_REQ_SET_ADDRESS
<< 8):
668 root_hub_devnum
= wValue
;
670 case (USB_REQ_SET_CONFIGURATION
<< 8):
673 puts("unsupported root hub command\n");
674 stat
= USB_ST_STALLED
;
677 len
= min(len
, txlen
);
685 static int dwc_otg_submit_rh_msg(struct usb_device
*dev
, unsigned long pipe
,
686 void *buffer
, int txlen
,
687 struct devrequest
*cmd
)
691 if (usb_pipeint(pipe
)) {
692 puts("Root-Hub submit IRQ: NOT implemented\n");
696 if (cmd
->requesttype
& USB_DIR_IN
)
697 stat
= dwc_otg_submit_rh_msg_in(dev
, buffer
, txlen
, cmd
);
699 stat
= dwc_otg_submit_rh_msg_out(dev
, buffer
, txlen
, cmd
);
706 int wait_for_chhltd(uint32_t *sub
, int *toggle
)
708 const uint32_t hcint_comp_hlt_ack
= DWC2_HCINT_XFERCOMP
|
709 DWC2_HCINT_CHHLTD
| DWC2_HCINT_ACK
;
710 struct dwc2_hc_regs
*hc_regs
= ®s
->hc_regs
[DWC2_HC_CHANNEL
];
712 uint32_t hcint
, hctsiz
;
714 ret
= wait_for_bit(&hc_regs
->hcint
, DWC2_HCINT_CHHLTD
, true);
718 hcint
= readl(&hc_regs
->hcint
);
719 if (hcint
!= hcint_comp_hlt_ack
) {
720 debug("%s: Error (HCINT=%08x)\n", __func__
, hcint
);
724 hctsiz
= readl(&hc_regs
->hctsiz
);
725 *sub
= (hctsiz
& DWC2_HCTSIZ_XFERSIZE_MASK
) >>
726 DWC2_HCTSIZ_XFERSIZE_OFFSET
;
728 *toggle
= (hctsiz
& DWC2_HCTSIZ_PID_MASK
) >>
729 DWC2_HCTSIZ_PID_OFFSET
;
731 debug("%s: sub=%u toggle=%d\n", __func__
, *sub
, toggle
? *toggle
: -1);
736 static int dwc2_eptype
[] = {
737 DWC2_HCCHAR_EPTYPE_ISOC
,
738 DWC2_HCCHAR_EPTYPE_INTR
,
739 DWC2_HCCHAR_EPTYPE_CONTROL
,
740 DWC2_HCCHAR_EPTYPE_BULK
,
743 int chunk_msg(struct usb_device
*dev
, unsigned long pipe
, int *pid
, int in
,
744 void *buffer
, int len
)
746 struct dwc2_hc_regs
*hc_regs
= ®s
->hc_regs
[DWC2_HC_CHANNEL
];
747 int devnum
= usb_pipedevice(pipe
);
748 int ep
= usb_pipeendpoint(pipe
);
749 int max
= usb_maxpacket(dev
, pipe
);
750 int eptype
= dwc2_eptype
[usb_pipetype(pipe
)];
755 uint32_t num_packets
;
756 int stop_transfer
= 0;
758 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__
, pipe
, *pid
,
761 if (len
> DWC2_DATA_BUF_SIZE
) {
762 printf("%s: %d is more then available buffer size (%d)\n",
763 __func__
, len
, DWC2_DATA_BUF_SIZE
);
770 /* Initialize channel */
771 dwc_otg_hc_init(regs
, DWC2_HC_CHANNEL
, devnum
, ep
, in
, eptype
,
774 xfer_len
= len
- done
;
775 /* Make sure that xfer_len is a multiple of max packet size. */
776 if (xfer_len
> CONFIG_DWC2_MAX_TRANSFER_SIZE
)
777 xfer_len
= CONFIG_DWC2_MAX_TRANSFER_SIZE
- max
+ 1;
780 num_packets
= (xfer_len
+ max
- 1) / max
;
781 if (num_packets
> CONFIG_DWC2_MAX_PACKET_COUNT
) {
782 num_packets
= CONFIG_DWC2_MAX_PACKET_COUNT
;
783 xfer_len
= num_packets
* max
;
790 xfer_len
= num_packets
* max
;
792 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__
,
793 *pid
, xfer_len
, num_packets
);
795 writel((xfer_len
<< DWC2_HCTSIZ_XFERSIZE_OFFSET
) |
796 (num_packets
<< DWC2_HCTSIZ_PKTCNT_OFFSET
) |
797 (*pid
<< DWC2_HCTSIZ_PID_OFFSET
),
800 memcpy(aligned_buffer
, (char *)buffer
+ done
, len
- done
);
801 writel((uint32_t)aligned_buffer
, &hc_regs
->hcdma
);
803 /* Set host channel enable after all other setup is complete. */
804 clrsetbits_le32(&hc_regs
->hcchar
, DWC2_HCCHAR_MULTICNT_MASK
|
805 DWC2_HCCHAR_CHEN
| DWC2_HCCHAR_CHDIS
,
806 (1 << DWC2_HCCHAR_MULTICNT_OFFSET
) |
809 ret
= wait_for_chhltd(&sub
, pid
);
821 } while ((done
< len
) && !stop_transfer
);
824 memcpy(buffer
, aligned_buffer
, done
);
826 writel(0, &hc_regs
->hcintmsk
);
827 writel(0xFFFFFFFF, &hc_regs
->hcint
);
835 /* U-Boot USB transmission interface */
836 int submit_bulk_msg(struct usb_device
*dev
, unsigned long pipe
, void *buffer
,
839 int devnum
= usb_pipedevice(pipe
);
840 int ep
= usb_pipeendpoint(pipe
);
842 if (devnum
== root_hub_devnum
) {
847 return chunk_msg(dev
, pipe
, &bulk_data_toggle
[devnum
][ep
],
848 usb_pipein(pipe
), buffer
, len
);
851 int submit_control_msg(struct usb_device
*dev
, unsigned long pipe
, void *buffer
,
852 int len
, struct devrequest
*setup
)
854 int devnum
= usb_pipedevice(pipe
);
855 int pid
, ret
, act_len
;
856 /* For CONTROL endpoint pid should start with DATA1 */
857 int status_direction
;
859 if (devnum
== root_hub_devnum
) {
861 dev
->speed
= USB_SPEED_HIGH
;
862 return dwc_otg_submit_rh_msg(dev
, pipe
, buffer
, len
, setup
);
865 pid
= DWC2_HC_PID_SETUP
;
866 ret
= chunk_msg(dev
, pipe
, &pid
, 0, setup
, 8);
871 pid
= DWC2_HC_PID_DATA1
;
872 ret
= chunk_msg(dev
, pipe
, &pid
, usb_pipein(pipe
), buffer
,
876 act_len
= dev
->act_len
;
877 } /* End of DATA stage */
882 if ((len
== 0) || usb_pipeout(pipe
))
883 status_direction
= 1;
885 status_direction
= 0;
887 pid
= DWC2_HC_PID_DATA1
;
888 ret
= chunk_msg(dev
, pipe
, &pid
, status_direction
, status_buffer
, 0);
892 dev
->act_len
= act_len
;
897 int submit_int_msg(struct usb_device
*dev
, unsigned long pipe
, void *buffer
,
898 int len
, int interval
)
900 printf("dev = %p pipe = %#lx buf = %p size = %d int = %d\n",
901 dev
, pipe
, buffer
, len
, interval
);
905 /* U-Boot USB control interface */
906 int usb_lowlevel_init(int index
, enum usb_init_type init
, void **controller
)
913 snpsid
= readl(®s
->gsnpsid
);
914 printf("Core Release: %x.%03x\n", snpsid
>> 12 & 0xf, snpsid
& 0xfff);
916 if ((snpsid
& DWC2_SNPSID_DEVID_MASK
) != DWC2_SNPSID_DEVID_VER_2xx
) {
917 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid
);
921 dwc_otg_core_init(regs
);
922 dwc_otg_core_host_init(regs
);
924 clrsetbits_le32(®s
->hprt0
, DWC2_HPRT0_PRTENA
|
925 DWC2_HPRT0_PRTCONNDET
| DWC2_HPRT0_PRTENCHNG
|
926 DWC2_HPRT0_PRTOVRCURRCHNG
,
929 clrbits_le32(®s
->hprt0
, DWC2_HPRT0_PRTENA
| DWC2_HPRT0_PRTCONNDET
|
930 DWC2_HPRT0_PRTENCHNG
| DWC2_HPRT0_PRTOVRCURRCHNG
|
933 for (i
= 0; i
< MAX_DEVICE
; i
++) {
934 for (j
= 0; j
< MAX_ENDPOINT
; j
++)
935 bulk_data_toggle
[i
][j
] = DWC2_HC_PID_DATA0
;
941 int usb_lowlevel_stop(int index
)
943 /* Put everything in reset. */
944 clrsetbits_le32(®s
->hprt0
, DWC2_HPRT0_PRTENA
|
945 DWC2_HPRT0_PRTCONNDET
| DWC2_HPRT0_PRTENCHNG
|
946 DWC2_HPRT0_PRTOVRCURRCHNG
,