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usb: dwc2: Pass private data into dwc_otg_core_init()
[people/ms/u-boot.git] / drivers / usb / host / dwc2.c
1 /*
2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <usb.h>
12 #include <malloc.h>
13 #include <memalign.h>
14 #include <phys2bus.h>
15 #include <usbroothubdes.h>
16 #include <wait_bit.h>
17 #include <asm/io.h>
18
19 #include "dwc2.h"
20
21 /* Use only HC channel 0. */
22 #define DWC2_HC_CHANNEL 0
23
24 #define DWC2_STATUS_BUF_SIZE 64
25 #define DWC2_DATA_BUF_SIZE (64 * 1024)
26
27 #define MAX_DEVICE 16
28 #define MAX_ENDPOINT 16
29
30 struct dwc2_priv {
31 #ifdef CONFIG_DM_USB
32 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
33 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
34 #else
35 uint8_t *aligned_buffer;
36 uint8_t *status_buffer;
37 #endif
38 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
39 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
40 struct dwc2_core_regs *regs;
41 int root_hub_devnum;
42 };
43
44 #ifndef CONFIG_DM_USB
45 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
46 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
47 ARCH_DMA_MINALIGN);
48 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
49 ARCH_DMA_MINALIGN);
50
51 static struct dwc2_priv local;
52 #endif
53
54 /*
55 * DWC2 IP interface
56 */
57
58 /*
59 * Initializes the FSLSPClkSel field of the HCFG register
60 * depending on the PHY type.
61 */
62 static void init_fslspclksel(struct dwc2_core_regs *regs)
63 {
64 uint32_t phyclk;
65
66 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
67 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
68 #else
69 /* High speed PHY running at full speed or high speed */
70 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
71 #endif
72
73 #ifdef CONFIG_DWC2_ULPI_FS_LS
74 uint32_t hwcfg2 = readl(&regs->ghwcfg2);
75 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
76 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
77 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
78 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
79
80 if (hval == 2 && fval == 1)
81 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
82 #endif
83
84 clrsetbits_le32(&regs->host_regs.hcfg,
85 DWC2_HCFG_FSLSPCLKSEL_MASK,
86 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
87 }
88
89 /*
90 * Flush a Tx FIFO.
91 *
92 * @param regs Programming view of DWC_otg controller.
93 * @param num Tx FIFO to flush.
94 */
95 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
96 {
97 int ret;
98
99 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
100 &regs->grstctl);
101 ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_TXFFLSH,
102 false, 1000, false);
103 if (ret)
104 printf("%s: Timeout!\n", __func__);
105
106 /* Wait for 3 PHY Clocks */
107 udelay(1);
108 }
109
110 /*
111 * Flush Rx FIFO.
112 *
113 * @param regs Programming view of DWC_otg controller.
114 */
115 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
116 {
117 int ret;
118
119 writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
120 ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_RXFFLSH,
121 false, 1000, false);
122 if (ret)
123 printf("%s: Timeout!\n", __func__);
124
125 /* Wait for 3 PHY Clocks */
126 udelay(1);
127 }
128
129 /*
130 * Do core a soft reset of the core. Be careful with this because it
131 * resets all the internal state machines of the core.
132 */
133 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
134 {
135 int ret;
136
137 /* Wait for AHB master IDLE state. */
138 ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_AHBIDLE,
139 true, 1000, false);
140 if (ret)
141 printf("%s: Timeout!\n", __func__);
142
143 /* Core Soft Reset */
144 writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
145 ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_CSFTRST,
146 false, 1000, false);
147 if (ret)
148 printf("%s: Timeout!\n", __func__);
149
150 /*
151 * Wait for core to come out of reset.
152 * NOTE: This long sleep is _very_ important, otherwise the core will
153 * not stay in host mode after a connector ID change!
154 */
155 mdelay(100);
156 }
157
158 /*
159 * This function initializes the DWC_otg controller registers for
160 * host mode.
161 *
162 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
163 * request queues. Host channels are reset to ensure that they are ready for
164 * performing transfers.
165 *
166 * @param regs Programming view of DWC_otg controller
167 *
168 */
169 static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
170 {
171 uint32_t nptxfifosize = 0;
172 uint32_t ptxfifosize = 0;
173 uint32_t hprt0 = 0;
174 int i, ret, num_channels;
175
176 /* Restart the Phy Clock */
177 writel(0, &regs->pcgcctl);
178
179 /* Initialize Host Configuration Register */
180 init_fslspclksel(regs);
181 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
182 setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
183 #endif
184
185 /* Configure data FIFO sizes */
186 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
187 if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
188 /* Rx FIFO */
189 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
190
191 /* Non-periodic Tx FIFO */
192 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
193 DWC2_FIFOSIZE_DEPTH_OFFSET;
194 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
195 DWC2_FIFOSIZE_STARTADDR_OFFSET;
196 writel(nptxfifosize, &regs->gnptxfsiz);
197
198 /* Periodic Tx FIFO */
199 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
200 DWC2_FIFOSIZE_DEPTH_OFFSET;
201 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
202 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
203 DWC2_FIFOSIZE_STARTADDR_OFFSET;
204 writel(ptxfifosize, &regs->hptxfsiz);
205 }
206 #endif
207
208 /* Clear Host Set HNP Enable in the OTG Control Register */
209 clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
210
211 /* Make sure the FIFOs are flushed. */
212 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
213 dwc_otg_flush_rx_fifo(regs);
214
215 /* Flush out any leftover queued requests. */
216 num_channels = readl(&regs->ghwcfg2);
217 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
218 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
219 num_channels += 1;
220
221 for (i = 0; i < num_channels; i++)
222 clrsetbits_le32(&regs->hc_regs[i].hcchar,
223 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
224 DWC2_HCCHAR_CHDIS);
225
226 /* Halt all channels to put them into a known state. */
227 for (i = 0; i < num_channels; i++) {
228 clrsetbits_le32(&regs->hc_regs[i].hcchar,
229 DWC2_HCCHAR_EPDIR,
230 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
231 ret = wait_for_bit(__func__, &regs->hc_regs[i].hcchar,
232 DWC2_HCCHAR_CHEN, false, 1000, false);
233 if (ret)
234 printf("%s: Timeout!\n", __func__);
235 }
236
237 /* Turn on the vbus power. */
238 if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
239 hprt0 = readl(&regs->hprt0);
240 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
241 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
242 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
243 hprt0 |= DWC2_HPRT0_PRTPWR;
244 writel(hprt0, &regs->hprt0);
245 }
246 }
247 }
248
249 /*
250 * This function initializes the DWC_otg controller registers and
251 * prepares the core for device mode or host mode operation.
252 *
253 * @param regs Programming view of the DWC_otg controller
254 */
255 static void dwc_otg_core_init(struct dwc2_priv *priv)
256 {
257 struct dwc2_core_regs *regs = priv->regs;
258 uint32_t ahbcfg = 0;
259 uint32_t usbcfg = 0;
260 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
261
262 /* Common Initialization */
263 usbcfg = readl(&regs->gusbcfg);
264
265 /* Program the ULPI External VBUS bit if needed */
266 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
267 usbcfg |= (DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV |
268 DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
269 DWC2_GUSBCFG_INDICATOR_PASSTHROUGH);
270 #else
271 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
272 #endif
273
274 /* Set external TS Dline pulsing */
275 #ifdef CONFIG_DWC2_TS_DLINE
276 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
277 #else
278 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
279 #endif
280 writel(usbcfg, &regs->gusbcfg);
281
282 /* Reset the Controller */
283 dwc_otg_core_reset(regs);
284
285 /*
286 * This programming sequence needs to happen in FS mode before
287 * any other programming occurs
288 */
289 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
290 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
291 /* If FS mode with FS PHY */
292 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
293
294 /* Reset after a PHY select */
295 dwc_otg_core_reset(regs);
296
297 /*
298 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
299 * Also do this on HNP Dev/Host mode switches (done in dev_init
300 * and host_init).
301 */
302 if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
303 init_fslspclksel(regs);
304
305 #ifdef CONFIG_DWC2_I2C_ENABLE
306 /* Program GUSBCFG.OtgUtmifsSel to I2C */
307 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
308
309 /* Program GI2CCTL.I2CEn */
310 clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
311 DWC2_GI2CCTL_I2CDEVADDR_MASK,
312 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
313 setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
314 #endif
315
316 #else
317 /* High speed PHY. */
318
319 /*
320 * HS PHY parameters. These parameters are preserved during
321 * soft reset so only program the first time. Do a soft reset
322 * immediately after setting phyif.
323 */
324 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
325 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
326
327 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
328 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
329 usbcfg |= DWC2_GUSBCFG_DDRSEL;
330 #else
331 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
332 #endif
333 } else { /* UTMI+ interface */
334 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
335 usbcfg |= DWC2_GUSBCFG_PHYIF;
336 #endif
337 }
338
339 writel(usbcfg, &regs->gusbcfg);
340
341 /* Reset after setting the PHY parameters */
342 dwc_otg_core_reset(regs);
343 #endif
344
345 usbcfg = readl(&regs->gusbcfg);
346 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
347 #ifdef CONFIG_DWC2_ULPI_FS_LS
348 uint32_t hwcfg2 = readl(&regs->ghwcfg2);
349 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
350 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
351 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
352 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
353 if (hval == 2 && fval == 1) {
354 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
355 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
356 }
357 #endif
358 writel(usbcfg, &regs->gusbcfg);
359
360 /* Program the GAHBCFG Register. */
361 switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
362 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
363 break;
364 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
365 while (brst_sz > 1) {
366 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
367 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
368 brst_sz >>= 1;
369 }
370
371 #ifdef CONFIG_DWC2_DMA_ENABLE
372 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
373 #endif
374 break;
375
376 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
377 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
378 #ifdef CONFIG_DWC2_DMA_ENABLE
379 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
380 #endif
381 break;
382 }
383
384 writel(ahbcfg, &regs->gahbcfg);
385
386 /* Program the GUSBCFG register for HNP/SRP. */
387 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
388
389 #ifdef CONFIG_DWC2_IC_USB_CAP
390 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
391 #endif
392 }
393
394 /*
395 * Prepares a host channel for transferring packets to/from a specific
396 * endpoint. The HCCHARn register is set up with the characteristics specified
397 * in _hc. Host channel interrupts that may need to be serviced while this
398 * transfer is in progress are enabled.
399 *
400 * @param regs Programming view of DWC_otg controller
401 * @param hc Information needed to initialize the host channel
402 */
403 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
404 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
405 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
406 {
407 struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
408 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
409 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
410 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
411 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
412 (max_packet << DWC2_HCCHAR_MPS_OFFSET);
413
414 if (dev->speed == USB_SPEED_LOW)
415 hcchar |= DWC2_HCCHAR_LSPDDEV;
416
417 /*
418 * Program the HCCHARn register with the endpoint characteristics
419 * for the current transfer.
420 */
421 writel(hcchar, &hc_regs->hcchar);
422
423 /* Program the HCSPLIT register, default to no SPLIT */
424 writel(0, &hc_regs->hcsplt);
425 }
426
427 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
428 uint8_t hub_devnum, uint8_t hub_port)
429 {
430 uint32_t hcsplt = 0;
431
432 hcsplt = DWC2_HCSPLT_SPLTENA;
433 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
434 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
435
436 /* Program the HCSPLIT register for SPLITs */
437 writel(hcsplt, &hc_regs->hcsplt);
438 }
439
440 /*
441 * DWC2 to USB API interface
442 */
443 /* Direction: In ; Request: Status */
444 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
445 struct usb_device *dev, void *buffer,
446 int txlen, struct devrequest *cmd)
447 {
448 uint32_t hprt0 = 0;
449 uint32_t port_status = 0;
450 uint32_t port_change = 0;
451 int len = 0;
452 int stat = 0;
453
454 switch (cmd->requesttype & ~USB_DIR_IN) {
455 case 0:
456 *(uint16_t *)buffer = cpu_to_le16(1);
457 len = 2;
458 break;
459 case USB_RECIP_INTERFACE:
460 case USB_RECIP_ENDPOINT:
461 *(uint16_t *)buffer = cpu_to_le16(0);
462 len = 2;
463 break;
464 case USB_TYPE_CLASS:
465 *(uint32_t *)buffer = cpu_to_le32(0);
466 len = 4;
467 break;
468 case USB_RECIP_OTHER | USB_TYPE_CLASS:
469 hprt0 = readl(&regs->hprt0);
470 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
471 port_status |= USB_PORT_STAT_CONNECTION;
472 if (hprt0 & DWC2_HPRT0_PRTENA)
473 port_status |= USB_PORT_STAT_ENABLE;
474 if (hprt0 & DWC2_HPRT0_PRTSUSP)
475 port_status |= USB_PORT_STAT_SUSPEND;
476 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
477 port_status |= USB_PORT_STAT_OVERCURRENT;
478 if (hprt0 & DWC2_HPRT0_PRTRST)
479 port_status |= USB_PORT_STAT_RESET;
480 if (hprt0 & DWC2_HPRT0_PRTPWR)
481 port_status |= USB_PORT_STAT_POWER;
482
483 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
484 port_status |= USB_PORT_STAT_LOW_SPEED;
485 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
486 DWC2_HPRT0_PRTSPD_HIGH)
487 port_status |= USB_PORT_STAT_HIGH_SPEED;
488
489 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
490 port_change |= USB_PORT_STAT_C_ENABLE;
491 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
492 port_change |= USB_PORT_STAT_C_CONNECTION;
493 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
494 port_change |= USB_PORT_STAT_C_OVERCURRENT;
495
496 *(uint32_t *)buffer = cpu_to_le32(port_status |
497 (port_change << 16));
498 len = 4;
499 break;
500 default:
501 puts("unsupported root hub command\n");
502 stat = USB_ST_STALLED;
503 }
504
505 dev->act_len = min(len, txlen);
506 dev->status = stat;
507
508 return stat;
509 }
510
511 /* Direction: In ; Request: Descriptor */
512 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
513 void *buffer, int txlen,
514 struct devrequest *cmd)
515 {
516 unsigned char data[32];
517 uint32_t dsc;
518 int len = 0;
519 int stat = 0;
520 uint16_t wValue = cpu_to_le16(cmd->value);
521 uint16_t wLength = cpu_to_le16(cmd->length);
522
523 switch (cmd->requesttype & ~USB_DIR_IN) {
524 case 0:
525 switch (wValue & 0xff00) {
526 case 0x0100: /* device descriptor */
527 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
528 memcpy(buffer, root_hub_dev_des, len);
529 break;
530 case 0x0200: /* configuration descriptor */
531 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
532 memcpy(buffer, root_hub_config_des, len);
533 break;
534 case 0x0300: /* string descriptors */
535 switch (wValue & 0xff) {
536 case 0x00:
537 len = min3(txlen, (int)sizeof(root_hub_str_index0),
538 (int)wLength);
539 memcpy(buffer, root_hub_str_index0, len);
540 break;
541 case 0x01:
542 len = min3(txlen, (int)sizeof(root_hub_str_index1),
543 (int)wLength);
544 memcpy(buffer, root_hub_str_index1, len);
545 break;
546 }
547 break;
548 default:
549 stat = USB_ST_STALLED;
550 }
551 break;
552
553 case USB_TYPE_CLASS:
554 /* Root port config, set 1 port and nothing else. */
555 dsc = 0x00000001;
556
557 data[0] = 9; /* min length; */
558 data[1] = 0x29;
559 data[2] = dsc & RH_A_NDP;
560 data[3] = 0;
561 if (dsc & RH_A_PSM)
562 data[3] |= 0x1;
563 if (dsc & RH_A_NOCP)
564 data[3] |= 0x10;
565 else if (dsc & RH_A_OCPM)
566 data[3] |= 0x8;
567
568 /* corresponds to data[4-7] */
569 data[5] = (dsc & RH_A_POTPGT) >> 24;
570 data[7] = dsc & RH_B_DR;
571 if (data[2] < 7) {
572 data[8] = 0xff;
573 } else {
574 data[0] += 2;
575 data[8] = (dsc & RH_B_DR) >> 8;
576 data[9] = 0xff;
577 data[10] = data[9];
578 }
579
580 len = min3(txlen, (int)data[0], (int)wLength);
581 memcpy(buffer, data, len);
582 break;
583 default:
584 puts("unsupported root hub command\n");
585 stat = USB_ST_STALLED;
586 }
587
588 dev->act_len = min(len, txlen);
589 dev->status = stat;
590
591 return stat;
592 }
593
594 /* Direction: In ; Request: Configuration */
595 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
596 void *buffer, int txlen,
597 struct devrequest *cmd)
598 {
599 int len = 0;
600 int stat = 0;
601
602 switch (cmd->requesttype & ~USB_DIR_IN) {
603 case 0:
604 *(uint8_t *)buffer = 0x01;
605 len = 1;
606 break;
607 default:
608 puts("unsupported root hub command\n");
609 stat = USB_ST_STALLED;
610 }
611
612 dev->act_len = min(len, txlen);
613 dev->status = stat;
614
615 return stat;
616 }
617
618 /* Direction: In */
619 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
620 struct usb_device *dev, void *buffer,
621 int txlen, struct devrequest *cmd)
622 {
623 switch (cmd->request) {
624 case USB_REQ_GET_STATUS:
625 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
626 txlen, cmd);
627 case USB_REQ_GET_DESCRIPTOR:
628 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
629 txlen, cmd);
630 case USB_REQ_GET_CONFIGURATION:
631 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
632 txlen, cmd);
633 default:
634 puts("unsupported root hub command\n");
635 return USB_ST_STALLED;
636 }
637 }
638
639 /* Direction: Out */
640 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
641 struct usb_device *dev,
642 void *buffer, int txlen,
643 struct devrequest *cmd)
644 {
645 struct dwc2_core_regs *regs = priv->regs;
646 int len = 0;
647 int stat = 0;
648 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
649 uint16_t wValue = cpu_to_le16(cmd->value);
650
651 switch (bmrtype_breq & ~USB_DIR_IN) {
652 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
653 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
654 break;
655
656 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
657 switch (wValue) {
658 case USB_PORT_FEAT_C_CONNECTION:
659 setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
660 break;
661 }
662 break;
663
664 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
665 switch (wValue) {
666 case USB_PORT_FEAT_SUSPEND:
667 break;
668
669 case USB_PORT_FEAT_RESET:
670 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
671 DWC2_HPRT0_PRTCONNDET |
672 DWC2_HPRT0_PRTENCHNG |
673 DWC2_HPRT0_PRTOVRCURRCHNG,
674 DWC2_HPRT0_PRTRST);
675 mdelay(50);
676 clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
677 break;
678
679 case USB_PORT_FEAT_POWER:
680 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
681 DWC2_HPRT0_PRTCONNDET |
682 DWC2_HPRT0_PRTENCHNG |
683 DWC2_HPRT0_PRTOVRCURRCHNG,
684 DWC2_HPRT0_PRTRST);
685 break;
686
687 case USB_PORT_FEAT_ENABLE:
688 break;
689 }
690 break;
691 case (USB_REQ_SET_ADDRESS << 8):
692 priv->root_hub_devnum = wValue;
693 break;
694 case (USB_REQ_SET_CONFIGURATION << 8):
695 break;
696 default:
697 puts("unsupported root hub command\n");
698 stat = USB_ST_STALLED;
699 }
700
701 len = min(len, txlen);
702
703 dev->act_len = len;
704 dev->status = stat;
705
706 return stat;
707 }
708
709 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
710 unsigned long pipe, void *buffer, int txlen,
711 struct devrequest *cmd)
712 {
713 int stat = 0;
714
715 if (usb_pipeint(pipe)) {
716 puts("Root-Hub submit IRQ: NOT implemented\n");
717 return 0;
718 }
719
720 if (cmd->requesttype & USB_DIR_IN)
721 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
722 else
723 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
724
725 mdelay(1);
726
727 return stat;
728 }
729
730 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
731 {
732 int ret;
733 uint32_t hcint, hctsiz;
734
735 ret = wait_for_bit(__func__, &hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
736 1000, false);
737 if (ret)
738 return ret;
739
740 hcint = readl(&hc_regs->hcint);
741 hctsiz = readl(&hc_regs->hctsiz);
742 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
743 DWC2_HCTSIZ_XFERSIZE_OFFSET;
744 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
745
746 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
747 *toggle);
748
749 if (hcint & DWC2_HCINT_XFERCOMP)
750 return 0;
751
752 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
753 return -EAGAIN;
754
755 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
756 return -EINVAL;
757 }
758
759 static int dwc2_eptype[] = {
760 DWC2_HCCHAR_EPTYPE_ISOC,
761 DWC2_HCCHAR_EPTYPE_INTR,
762 DWC2_HCCHAR_EPTYPE_CONTROL,
763 DWC2_HCCHAR_EPTYPE_BULK,
764 };
765
766 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
767 u8 *pid, int in, void *buffer, int num_packets,
768 int xfer_len, int *actual_len, int odd_frame)
769 {
770 int ret = 0;
771 uint32_t sub;
772
773 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
774 *pid, xfer_len, num_packets);
775
776 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
777 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
778 (*pid << DWC2_HCTSIZ_PID_OFFSET),
779 &hc_regs->hctsiz);
780
781 if (!in && xfer_len) {
782 memcpy(aligned_buffer, buffer, xfer_len);
783
784 flush_dcache_range((unsigned long)aligned_buffer,
785 (unsigned long)aligned_buffer +
786 roundup(xfer_len, ARCH_DMA_MINALIGN));
787 }
788
789 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
790
791 /* Clear old interrupt conditions for this host channel. */
792 writel(0x3fff, &hc_regs->hcint);
793
794 /* Set host channel enable after all other setup is complete. */
795 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
796 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
797 DWC2_HCCHAR_ODDFRM,
798 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
799 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
800 DWC2_HCCHAR_CHEN);
801
802 ret = wait_for_chhltd(hc_regs, &sub, pid);
803 if (ret < 0)
804 return ret;
805
806 if (in) {
807 xfer_len -= sub;
808
809 invalidate_dcache_range((unsigned long)aligned_buffer,
810 (unsigned long)aligned_buffer +
811 roundup(xfer_len, ARCH_DMA_MINALIGN));
812
813 memcpy(buffer, aligned_buffer, xfer_len);
814 }
815 *actual_len = xfer_len;
816
817 return ret;
818 }
819
820 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
821 unsigned long pipe, u8 *pid, int in, void *buffer, int len)
822 {
823 struct dwc2_core_regs *regs = priv->regs;
824 struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
825 struct dwc2_host_regs *host_regs = &regs->host_regs;
826 int devnum = usb_pipedevice(pipe);
827 int ep = usb_pipeendpoint(pipe);
828 int max = usb_maxpacket(dev, pipe);
829 int eptype = dwc2_eptype[usb_pipetype(pipe)];
830 int done = 0;
831 int ret = 0;
832 int do_split = 0;
833 int complete_split = 0;
834 uint32_t xfer_len;
835 uint32_t num_packets;
836 int stop_transfer = 0;
837 uint32_t max_xfer_len;
838 int ssplit_frame_num = 0;
839
840 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
841 in, len);
842
843 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
844 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
845 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
846 if (max_xfer_len > DWC2_DATA_BUF_SIZE)
847 max_xfer_len = DWC2_DATA_BUF_SIZE;
848
849 /* Make sure that max_xfer_len is a multiple of max packet size. */
850 num_packets = max_xfer_len / max;
851 max_xfer_len = num_packets * max;
852
853 /* Initialize channel */
854 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
855 eptype, max);
856
857 /* Check if the target is a FS/LS device behind a HS hub */
858 if (dev->speed != USB_SPEED_HIGH) {
859 uint8_t hub_addr;
860 uint8_t hub_port;
861 uint32_t hprt0 = readl(&regs->hprt0);
862 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
863 DWC2_HPRT0_PRTSPD_HIGH) {
864 usb_find_usb2_hub_address_port(dev, &hub_addr,
865 &hub_port);
866 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
867
868 do_split = 1;
869 num_packets = 1;
870 max_xfer_len = max;
871 }
872 }
873
874 do {
875 int actual_len = 0;
876 uint32_t hcint;
877 int odd_frame = 0;
878 xfer_len = len - done;
879
880 if (xfer_len > max_xfer_len)
881 xfer_len = max_xfer_len;
882 else if (xfer_len > max)
883 num_packets = (xfer_len + max - 1) / max;
884 else
885 num_packets = 1;
886
887 if (complete_split)
888 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
889 else if (do_split)
890 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
891
892 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
893 int uframe_num = readl(&host_regs->hfnum);
894 if (!(uframe_num & 0x1))
895 odd_frame = 1;
896 }
897
898 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
899 in, (char *)buffer + done, num_packets,
900 xfer_len, &actual_len, odd_frame);
901
902 hcint = readl(&hc_regs->hcint);
903 if (complete_split) {
904 stop_transfer = 0;
905 if (hcint & DWC2_HCINT_NYET) {
906 ret = 0;
907 int frame_num = DWC2_HFNUM_MAX_FRNUM &
908 readl(&host_regs->hfnum);
909 if (((frame_num - ssplit_frame_num) &
910 DWC2_HFNUM_MAX_FRNUM) > 4)
911 ret = -EAGAIN;
912 } else
913 complete_split = 0;
914 } else if (do_split) {
915 if (hcint & DWC2_HCINT_ACK) {
916 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
917 readl(&host_regs->hfnum);
918 ret = 0;
919 complete_split = 1;
920 }
921 }
922
923 if (ret)
924 break;
925
926 if (actual_len < xfer_len)
927 stop_transfer = 1;
928
929 done += actual_len;
930
931 /* Transactions are done when when either all data is transferred or
932 * there is a short transfer. In case of a SPLIT make sure the CSPLIT
933 * is executed.
934 */
935 } while (((done < len) && !stop_transfer) || complete_split);
936
937 writel(0, &hc_regs->hcintmsk);
938 writel(0xFFFFFFFF, &hc_regs->hcint);
939
940 dev->status = 0;
941 dev->act_len = done;
942
943 return ret;
944 }
945
946 /* U-Boot USB transmission interface */
947 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
948 unsigned long pipe, void *buffer, int len)
949 {
950 int devnum = usb_pipedevice(pipe);
951 int ep = usb_pipeendpoint(pipe);
952 u8* pid;
953
954 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
955 dev->status = 0;
956 return -EINVAL;
957 }
958
959 if (usb_pipein(pipe))
960 pid = &priv->in_data_toggle[devnum][ep];
961 else
962 pid = &priv->out_data_toggle[devnum][ep];
963
964 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
965 }
966
967 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
968 unsigned long pipe, void *buffer, int len,
969 struct devrequest *setup)
970 {
971 int devnum = usb_pipedevice(pipe);
972 int ret, act_len;
973 u8 pid;
974 /* For CONTROL endpoint pid should start with DATA1 */
975 int status_direction;
976
977 if (devnum == priv->root_hub_devnum) {
978 dev->status = 0;
979 dev->speed = USB_SPEED_HIGH;
980 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
981 setup);
982 }
983
984 /* SETUP stage */
985 pid = DWC2_HC_PID_SETUP;
986 do {
987 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
988 } while (ret == -EAGAIN);
989 if (ret)
990 return ret;
991
992 /* DATA stage */
993 act_len = 0;
994 if (buffer) {
995 pid = DWC2_HC_PID_DATA1;
996 do {
997 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
998 buffer, len);
999 act_len += dev->act_len;
1000 buffer += dev->act_len;
1001 len -= dev->act_len;
1002 } while (ret == -EAGAIN);
1003 if (ret)
1004 return ret;
1005 status_direction = usb_pipeout(pipe);
1006 } else {
1007 /* No-data CONTROL always ends with an IN transaction */
1008 status_direction = 1;
1009 }
1010
1011 /* STATUS stage */
1012 pid = DWC2_HC_PID_DATA1;
1013 do {
1014 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1015 priv->status_buffer, 0);
1016 } while (ret == -EAGAIN);
1017 if (ret)
1018 return ret;
1019
1020 dev->act_len = act_len;
1021
1022 return 0;
1023 }
1024
1025 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1026 unsigned long pipe, void *buffer, int len, int interval)
1027 {
1028 unsigned long timeout;
1029 int ret;
1030
1031 /* FIXME: what is interval? */
1032
1033 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1034 for (;;) {
1035 if (get_timer(0) > timeout) {
1036 printf("Timeout poll on interrupt endpoint\n");
1037 return -ETIMEDOUT;
1038 }
1039 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1040 if (ret != -EAGAIN)
1041 return ret;
1042 }
1043 }
1044
1045 static int dwc2_init_common(struct dwc2_priv *priv)
1046 {
1047 struct dwc2_core_regs *regs = priv->regs;
1048 uint32_t snpsid;
1049 int i, j;
1050
1051 snpsid = readl(&regs->gsnpsid);
1052 printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
1053
1054 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1055 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1056 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
1057 return -ENODEV;
1058 }
1059
1060 dwc_otg_core_init(priv);
1061 dwc_otg_core_host_init(regs);
1062
1063 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1064 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1065 DWC2_HPRT0_PRTOVRCURRCHNG,
1066 DWC2_HPRT0_PRTRST);
1067 mdelay(50);
1068 clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1069 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1070 DWC2_HPRT0_PRTRST);
1071
1072 for (i = 0; i < MAX_DEVICE; i++) {
1073 for (j = 0; j < MAX_ENDPOINT; j++) {
1074 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1075 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1076 }
1077 }
1078
1079 return 0;
1080 }
1081
1082 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1083 {
1084 /* Put everything in reset. */
1085 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1086 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1087 DWC2_HPRT0_PRTOVRCURRCHNG,
1088 DWC2_HPRT0_PRTRST);
1089 }
1090
1091 #ifndef CONFIG_DM_USB
1092 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1093 int len, struct devrequest *setup)
1094 {
1095 return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1096 }
1097
1098 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1099 int len)
1100 {
1101 return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1102 }
1103
1104 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1105 int len, int interval)
1106 {
1107 return _submit_int_msg(&local, dev, pipe, buffer, len, interval);
1108 }
1109
1110 /* U-Boot USB control interface */
1111 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1112 {
1113 struct dwc2_priv *priv = &local;
1114
1115 memset(priv, '\0', sizeof(*priv));
1116 priv->root_hub_devnum = 0;
1117 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1118 priv->aligned_buffer = aligned_buffer_addr;
1119 priv->status_buffer = status_buffer_addr;
1120
1121 /* board-dependant init */
1122 if (board_usb_init(index, USB_INIT_HOST))
1123 return -1;
1124
1125 return dwc2_init_common(priv);
1126 }
1127
1128 int usb_lowlevel_stop(int index)
1129 {
1130 dwc2_uninit_common(local.regs);
1131
1132 return 0;
1133 }
1134 #endif
1135
1136 #ifdef CONFIG_DM_USB
1137 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1138 unsigned long pipe, void *buffer, int length,
1139 struct devrequest *setup)
1140 {
1141 struct dwc2_priv *priv = dev_get_priv(dev);
1142
1143 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1144 dev->name, udev, udev->dev->name, udev->portnr);
1145
1146 return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1147 }
1148
1149 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1150 unsigned long pipe, void *buffer, int length)
1151 {
1152 struct dwc2_priv *priv = dev_get_priv(dev);
1153
1154 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1155
1156 return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1157 }
1158
1159 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1160 unsigned long pipe, void *buffer, int length,
1161 int interval)
1162 {
1163 struct dwc2_priv *priv = dev_get_priv(dev);
1164
1165 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1166
1167 return _submit_int_msg(priv, udev, pipe, buffer, length, interval);
1168 }
1169
1170 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1171 {
1172 struct dwc2_priv *priv = dev_get_priv(dev);
1173 fdt_addr_t addr;
1174
1175 addr = dev_get_addr(dev);
1176 if (addr == FDT_ADDR_T_NONE)
1177 return -EINVAL;
1178 priv->regs = (struct dwc2_core_regs *)addr;
1179
1180 return 0;
1181 }
1182
1183 static int dwc2_usb_probe(struct udevice *dev)
1184 {
1185 struct dwc2_priv *priv = dev_get_priv(dev);
1186
1187 return dwc2_init_common(priv);
1188 }
1189
1190 static int dwc2_usb_remove(struct udevice *dev)
1191 {
1192 struct dwc2_priv *priv = dev_get_priv(dev);
1193
1194 dwc2_uninit_common(priv->regs);
1195
1196 return 0;
1197 }
1198
1199 struct dm_usb_ops dwc2_usb_ops = {
1200 .control = dwc2_submit_control_msg,
1201 .bulk = dwc2_submit_bulk_msg,
1202 .interrupt = dwc2_submit_int_msg,
1203 };
1204
1205 static const struct udevice_id dwc2_usb_ids[] = {
1206 { .compatible = "brcm,bcm2835-usb" },
1207 { .compatible = "snps,dwc2" },
1208 { }
1209 };
1210
1211 U_BOOT_DRIVER(usb_dwc2) = {
1212 .name = "dwc2_usb",
1213 .id = UCLASS_USB,
1214 .of_match = dwc2_usb_ids,
1215 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1216 .probe = dwc2_usb_probe,
1217 .remove = dwc2_usb_remove,
1218 .ops = &dwc2_usb_ops,
1219 .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1220 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1221 };
1222 #endif
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