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usb: dwc2: add support for external vbus supply
[people/ms/u-boot.git] / drivers / usb / host / dwc2.c
1 /*
2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <usb.h>
12 #include <malloc.h>
13 #include <memalign.h>
14 #include <phys2bus.h>
15 #include <usbroothubdes.h>
16 #include <wait_bit.h>
17 #include <asm/io.h>
18 #include <power/regulator.h>
19
20 #include "dwc2.h"
21
22 DECLARE_GLOBAL_DATA_PTR;
23
24 /* Use only HC channel 0. */
25 #define DWC2_HC_CHANNEL 0
26
27 #define DWC2_STATUS_BUF_SIZE 64
28 #define DWC2_DATA_BUF_SIZE (64 * 1024)
29
30 #define MAX_DEVICE 16
31 #define MAX_ENDPOINT 16
32
33 struct dwc2_priv {
34 #ifdef CONFIG_DM_USB
35 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
36 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
37 #else
38 uint8_t *aligned_buffer;
39 uint8_t *status_buffer;
40 #endif
41 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
42 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
43 struct dwc2_core_regs *regs;
44 int root_hub_devnum;
45 bool ext_vbus;
46 bool oc_disable;
47 };
48
49 #ifndef CONFIG_DM_USB
50 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
51 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
52 ARCH_DMA_MINALIGN);
53 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
54 ARCH_DMA_MINALIGN);
55
56 static struct dwc2_priv local;
57 #endif
58
59 /*
60 * DWC2 IP interface
61 */
62
63 /*
64 * Initializes the FSLSPClkSel field of the HCFG register
65 * depending on the PHY type.
66 */
67 static void init_fslspclksel(struct dwc2_core_regs *regs)
68 {
69 uint32_t phyclk;
70
71 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
72 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
73 #else
74 /* High speed PHY running at full speed or high speed */
75 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
76 #endif
77
78 #ifdef CONFIG_DWC2_ULPI_FS_LS
79 uint32_t hwcfg2 = readl(&regs->ghwcfg2);
80 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
81 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
82 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
83 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
84
85 if (hval == 2 && fval == 1)
86 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
87 #endif
88
89 clrsetbits_le32(&regs->host_regs.hcfg,
90 DWC2_HCFG_FSLSPCLKSEL_MASK,
91 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
92 }
93
94 /*
95 * Flush a Tx FIFO.
96 *
97 * @param regs Programming view of DWC_otg controller.
98 * @param num Tx FIFO to flush.
99 */
100 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
101 {
102 int ret;
103
104 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
105 &regs->grstctl);
106 ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_TXFFLSH,
107 false, 1000, false);
108 if (ret)
109 printf("%s: Timeout!\n", __func__);
110
111 /* Wait for 3 PHY Clocks */
112 udelay(1);
113 }
114
115 /*
116 * Flush Rx FIFO.
117 *
118 * @param regs Programming view of DWC_otg controller.
119 */
120 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
121 {
122 int ret;
123
124 writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
125 ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_RXFFLSH,
126 false, 1000, false);
127 if (ret)
128 printf("%s: Timeout!\n", __func__);
129
130 /* Wait for 3 PHY Clocks */
131 udelay(1);
132 }
133
134 /*
135 * Do core a soft reset of the core. Be careful with this because it
136 * resets all the internal state machines of the core.
137 */
138 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
139 {
140 int ret;
141
142 /* Wait for AHB master IDLE state. */
143 ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_AHBIDLE,
144 true, 1000, false);
145 if (ret)
146 printf("%s: Timeout!\n", __func__);
147
148 /* Core Soft Reset */
149 writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
150 ret = wait_for_bit(__func__, &regs->grstctl, DWC2_GRSTCTL_CSFTRST,
151 false, 1000, false);
152 if (ret)
153 printf("%s: Timeout!\n", __func__);
154
155 /*
156 * Wait for core to come out of reset.
157 * NOTE: This long sleep is _very_ important, otherwise the core will
158 * not stay in host mode after a connector ID change!
159 */
160 mdelay(100);
161 }
162
163 #if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR)
164 static int dwc_vbus_supply_init(struct udevice *dev)
165 {
166 struct udevice *vbus_supply;
167 int ret;
168
169 ret = device_get_supply_regulator(dev, "vbus-supply", &vbus_supply);
170 if (ret) {
171 debug("%s: No vbus supply\n", dev->name);
172 return 0;
173 }
174
175 ret = regulator_set_enable(vbus_supply, true);
176 if (ret) {
177 error("Error enabling vbus supply\n");
178 return ret;
179 }
180
181 return 0;
182 }
183 #else
184 static int dwc_vbus_supply_init(struct udevice *dev)
185 {
186 return 0;
187 }
188 #endif
189
190 /*
191 * This function initializes the DWC_otg controller registers for
192 * host mode.
193 *
194 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
195 * request queues. Host channels are reset to ensure that they are ready for
196 * performing transfers.
197 *
198 * @param dev USB Device (NULL if driver model is not being used)
199 * @param regs Programming view of DWC_otg controller
200 *
201 */
202 static void dwc_otg_core_host_init(struct udevice *dev,
203 struct dwc2_core_regs *regs)
204 {
205 uint32_t nptxfifosize = 0;
206 uint32_t ptxfifosize = 0;
207 uint32_t hprt0 = 0;
208 int i, ret, num_channels;
209
210 /* Restart the Phy Clock */
211 writel(0, &regs->pcgcctl);
212
213 /* Initialize Host Configuration Register */
214 init_fslspclksel(regs);
215 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
216 setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
217 #endif
218
219 /* Configure data FIFO sizes */
220 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
221 if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
222 /* Rx FIFO */
223 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
224
225 /* Non-periodic Tx FIFO */
226 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
227 DWC2_FIFOSIZE_DEPTH_OFFSET;
228 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
229 DWC2_FIFOSIZE_STARTADDR_OFFSET;
230 writel(nptxfifosize, &regs->gnptxfsiz);
231
232 /* Periodic Tx FIFO */
233 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
234 DWC2_FIFOSIZE_DEPTH_OFFSET;
235 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
236 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
237 DWC2_FIFOSIZE_STARTADDR_OFFSET;
238 writel(ptxfifosize, &regs->hptxfsiz);
239 }
240 #endif
241
242 /* Clear Host Set HNP Enable in the OTG Control Register */
243 clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
244
245 /* Make sure the FIFOs are flushed. */
246 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
247 dwc_otg_flush_rx_fifo(regs);
248
249 /* Flush out any leftover queued requests. */
250 num_channels = readl(&regs->ghwcfg2);
251 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
252 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
253 num_channels += 1;
254
255 for (i = 0; i < num_channels; i++)
256 clrsetbits_le32(&regs->hc_regs[i].hcchar,
257 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
258 DWC2_HCCHAR_CHDIS);
259
260 /* Halt all channels to put them into a known state. */
261 for (i = 0; i < num_channels; i++) {
262 clrsetbits_le32(&regs->hc_regs[i].hcchar,
263 DWC2_HCCHAR_EPDIR,
264 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
265 ret = wait_for_bit(__func__, &regs->hc_regs[i].hcchar,
266 DWC2_HCCHAR_CHEN, false, 1000, false);
267 if (ret)
268 printf("%s: Timeout!\n", __func__);
269 }
270
271 /* Turn on the vbus power. */
272 if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
273 hprt0 = readl(&regs->hprt0);
274 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
275 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
276 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
277 hprt0 |= DWC2_HPRT0_PRTPWR;
278 writel(hprt0, &regs->hprt0);
279 }
280 }
281
282 if (dev)
283 dwc_vbus_supply_init(dev);
284 }
285
286 /*
287 * This function initializes the DWC_otg controller registers and
288 * prepares the core for device mode or host mode operation.
289 *
290 * @param regs Programming view of the DWC_otg controller
291 */
292 static void dwc_otg_core_init(struct dwc2_priv *priv)
293 {
294 struct dwc2_core_regs *regs = priv->regs;
295 uint32_t ahbcfg = 0;
296 uint32_t usbcfg = 0;
297 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
298
299 /* Common Initialization */
300 usbcfg = readl(&regs->gusbcfg);
301
302 /* Program the ULPI External VBUS bit if needed */
303 if (priv->ext_vbus) {
304 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
305 if (!priv->oc_disable) {
306 usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
307 DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
308 }
309 } else {
310 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
311 }
312
313 /* Set external TS Dline pulsing */
314 #ifdef CONFIG_DWC2_TS_DLINE
315 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
316 #else
317 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
318 #endif
319 writel(usbcfg, &regs->gusbcfg);
320
321 /* Reset the Controller */
322 dwc_otg_core_reset(regs);
323
324 /*
325 * This programming sequence needs to happen in FS mode before
326 * any other programming occurs
327 */
328 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
329 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
330 /* If FS mode with FS PHY */
331 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
332
333 /* Reset after a PHY select */
334 dwc_otg_core_reset(regs);
335
336 /*
337 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
338 * Also do this on HNP Dev/Host mode switches (done in dev_init
339 * and host_init).
340 */
341 if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
342 init_fslspclksel(regs);
343
344 #ifdef CONFIG_DWC2_I2C_ENABLE
345 /* Program GUSBCFG.OtgUtmifsSel to I2C */
346 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
347
348 /* Program GI2CCTL.I2CEn */
349 clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
350 DWC2_GI2CCTL_I2CDEVADDR_MASK,
351 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
352 setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
353 #endif
354
355 #else
356 /* High speed PHY. */
357
358 /*
359 * HS PHY parameters. These parameters are preserved during
360 * soft reset so only program the first time. Do a soft reset
361 * immediately after setting phyif.
362 */
363 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
364 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
365
366 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
367 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
368 usbcfg |= DWC2_GUSBCFG_DDRSEL;
369 #else
370 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
371 #endif
372 } else { /* UTMI+ interface */
373 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
374 usbcfg |= DWC2_GUSBCFG_PHYIF;
375 #endif
376 }
377
378 writel(usbcfg, &regs->gusbcfg);
379
380 /* Reset after setting the PHY parameters */
381 dwc_otg_core_reset(regs);
382 #endif
383
384 usbcfg = readl(&regs->gusbcfg);
385 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
386 #ifdef CONFIG_DWC2_ULPI_FS_LS
387 uint32_t hwcfg2 = readl(&regs->ghwcfg2);
388 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
389 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
390 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
391 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
392 if (hval == 2 && fval == 1) {
393 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
394 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
395 }
396 #endif
397 writel(usbcfg, &regs->gusbcfg);
398
399 /* Program the GAHBCFG Register. */
400 switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
401 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
402 break;
403 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
404 while (brst_sz > 1) {
405 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
406 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
407 brst_sz >>= 1;
408 }
409
410 #ifdef CONFIG_DWC2_DMA_ENABLE
411 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
412 #endif
413 break;
414
415 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
416 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
417 #ifdef CONFIG_DWC2_DMA_ENABLE
418 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
419 #endif
420 break;
421 }
422
423 writel(ahbcfg, &regs->gahbcfg);
424
425 /* Program the GUSBCFG register for HNP/SRP. */
426 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
427
428 #ifdef CONFIG_DWC2_IC_USB_CAP
429 setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
430 #endif
431 }
432
433 /*
434 * Prepares a host channel for transferring packets to/from a specific
435 * endpoint. The HCCHARn register is set up with the characteristics specified
436 * in _hc. Host channel interrupts that may need to be serviced while this
437 * transfer is in progress are enabled.
438 *
439 * @param regs Programming view of DWC_otg controller
440 * @param hc Information needed to initialize the host channel
441 */
442 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
443 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
444 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
445 {
446 struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
447 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
448 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
449 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
450 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
451 (max_packet << DWC2_HCCHAR_MPS_OFFSET);
452
453 if (dev->speed == USB_SPEED_LOW)
454 hcchar |= DWC2_HCCHAR_LSPDDEV;
455
456 /*
457 * Program the HCCHARn register with the endpoint characteristics
458 * for the current transfer.
459 */
460 writel(hcchar, &hc_regs->hcchar);
461
462 /* Program the HCSPLIT register, default to no SPLIT */
463 writel(0, &hc_regs->hcsplt);
464 }
465
466 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
467 uint8_t hub_devnum, uint8_t hub_port)
468 {
469 uint32_t hcsplt = 0;
470
471 hcsplt = DWC2_HCSPLT_SPLTENA;
472 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
473 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
474
475 /* Program the HCSPLIT register for SPLITs */
476 writel(hcsplt, &hc_regs->hcsplt);
477 }
478
479 /*
480 * DWC2 to USB API interface
481 */
482 /* Direction: In ; Request: Status */
483 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
484 struct usb_device *dev, void *buffer,
485 int txlen, struct devrequest *cmd)
486 {
487 uint32_t hprt0 = 0;
488 uint32_t port_status = 0;
489 uint32_t port_change = 0;
490 int len = 0;
491 int stat = 0;
492
493 switch (cmd->requesttype & ~USB_DIR_IN) {
494 case 0:
495 *(uint16_t *)buffer = cpu_to_le16(1);
496 len = 2;
497 break;
498 case USB_RECIP_INTERFACE:
499 case USB_RECIP_ENDPOINT:
500 *(uint16_t *)buffer = cpu_to_le16(0);
501 len = 2;
502 break;
503 case USB_TYPE_CLASS:
504 *(uint32_t *)buffer = cpu_to_le32(0);
505 len = 4;
506 break;
507 case USB_RECIP_OTHER | USB_TYPE_CLASS:
508 hprt0 = readl(&regs->hprt0);
509 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
510 port_status |= USB_PORT_STAT_CONNECTION;
511 if (hprt0 & DWC2_HPRT0_PRTENA)
512 port_status |= USB_PORT_STAT_ENABLE;
513 if (hprt0 & DWC2_HPRT0_PRTSUSP)
514 port_status |= USB_PORT_STAT_SUSPEND;
515 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
516 port_status |= USB_PORT_STAT_OVERCURRENT;
517 if (hprt0 & DWC2_HPRT0_PRTRST)
518 port_status |= USB_PORT_STAT_RESET;
519 if (hprt0 & DWC2_HPRT0_PRTPWR)
520 port_status |= USB_PORT_STAT_POWER;
521
522 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
523 port_status |= USB_PORT_STAT_LOW_SPEED;
524 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
525 DWC2_HPRT0_PRTSPD_HIGH)
526 port_status |= USB_PORT_STAT_HIGH_SPEED;
527
528 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
529 port_change |= USB_PORT_STAT_C_ENABLE;
530 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
531 port_change |= USB_PORT_STAT_C_CONNECTION;
532 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
533 port_change |= USB_PORT_STAT_C_OVERCURRENT;
534
535 *(uint32_t *)buffer = cpu_to_le32(port_status |
536 (port_change << 16));
537 len = 4;
538 break;
539 default:
540 puts("unsupported root hub command\n");
541 stat = USB_ST_STALLED;
542 }
543
544 dev->act_len = min(len, txlen);
545 dev->status = stat;
546
547 return stat;
548 }
549
550 /* Direction: In ; Request: Descriptor */
551 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
552 void *buffer, int txlen,
553 struct devrequest *cmd)
554 {
555 unsigned char data[32];
556 uint32_t dsc;
557 int len = 0;
558 int stat = 0;
559 uint16_t wValue = cpu_to_le16(cmd->value);
560 uint16_t wLength = cpu_to_le16(cmd->length);
561
562 switch (cmd->requesttype & ~USB_DIR_IN) {
563 case 0:
564 switch (wValue & 0xff00) {
565 case 0x0100: /* device descriptor */
566 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
567 memcpy(buffer, root_hub_dev_des, len);
568 break;
569 case 0x0200: /* configuration descriptor */
570 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
571 memcpy(buffer, root_hub_config_des, len);
572 break;
573 case 0x0300: /* string descriptors */
574 switch (wValue & 0xff) {
575 case 0x00:
576 len = min3(txlen, (int)sizeof(root_hub_str_index0),
577 (int)wLength);
578 memcpy(buffer, root_hub_str_index0, len);
579 break;
580 case 0x01:
581 len = min3(txlen, (int)sizeof(root_hub_str_index1),
582 (int)wLength);
583 memcpy(buffer, root_hub_str_index1, len);
584 break;
585 }
586 break;
587 default:
588 stat = USB_ST_STALLED;
589 }
590 break;
591
592 case USB_TYPE_CLASS:
593 /* Root port config, set 1 port and nothing else. */
594 dsc = 0x00000001;
595
596 data[0] = 9; /* min length; */
597 data[1] = 0x29;
598 data[2] = dsc & RH_A_NDP;
599 data[3] = 0;
600 if (dsc & RH_A_PSM)
601 data[3] |= 0x1;
602 if (dsc & RH_A_NOCP)
603 data[3] |= 0x10;
604 else if (dsc & RH_A_OCPM)
605 data[3] |= 0x8;
606
607 /* corresponds to data[4-7] */
608 data[5] = (dsc & RH_A_POTPGT) >> 24;
609 data[7] = dsc & RH_B_DR;
610 if (data[2] < 7) {
611 data[8] = 0xff;
612 } else {
613 data[0] += 2;
614 data[8] = (dsc & RH_B_DR) >> 8;
615 data[9] = 0xff;
616 data[10] = data[9];
617 }
618
619 len = min3(txlen, (int)data[0], (int)wLength);
620 memcpy(buffer, data, len);
621 break;
622 default:
623 puts("unsupported root hub command\n");
624 stat = USB_ST_STALLED;
625 }
626
627 dev->act_len = min(len, txlen);
628 dev->status = stat;
629
630 return stat;
631 }
632
633 /* Direction: In ; Request: Configuration */
634 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
635 void *buffer, int txlen,
636 struct devrequest *cmd)
637 {
638 int len = 0;
639 int stat = 0;
640
641 switch (cmd->requesttype & ~USB_DIR_IN) {
642 case 0:
643 *(uint8_t *)buffer = 0x01;
644 len = 1;
645 break;
646 default:
647 puts("unsupported root hub command\n");
648 stat = USB_ST_STALLED;
649 }
650
651 dev->act_len = min(len, txlen);
652 dev->status = stat;
653
654 return stat;
655 }
656
657 /* Direction: In */
658 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
659 struct usb_device *dev, void *buffer,
660 int txlen, struct devrequest *cmd)
661 {
662 switch (cmd->request) {
663 case USB_REQ_GET_STATUS:
664 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
665 txlen, cmd);
666 case USB_REQ_GET_DESCRIPTOR:
667 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
668 txlen, cmd);
669 case USB_REQ_GET_CONFIGURATION:
670 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
671 txlen, cmd);
672 default:
673 puts("unsupported root hub command\n");
674 return USB_ST_STALLED;
675 }
676 }
677
678 /* Direction: Out */
679 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
680 struct usb_device *dev,
681 void *buffer, int txlen,
682 struct devrequest *cmd)
683 {
684 struct dwc2_core_regs *regs = priv->regs;
685 int len = 0;
686 int stat = 0;
687 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
688 uint16_t wValue = cpu_to_le16(cmd->value);
689
690 switch (bmrtype_breq & ~USB_DIR_IN) {
691 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
692 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
693 break;
694
695 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
696 switch (wValue) {
697 case USB_PORT_FEAT_C_CONNECTION:
698 setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
699 break;
700 }
701 break;
702
703 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
704 switch (wValue) {
705 case USB_PORT_FEAT_SUSPEND:
706 break;
707
708 case USB_PORT_FEAT_RESET:
709 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
710 DWC2_HPRT0_PRTCONNDET |
711 DWC2_HPRT0_PRTENCHNG |
712 DWC2_HPRT0_PRTOVRCURRCHNG,
713 DWC2_HPRT0_PRTRST);
714 mdelay(50);
715 clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
716 break;
717
718 case USB_PORT_FEAT_POWER:
719 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
720 DWC2_HPRT0_PRTCONNDET |
721 DWC2_HPRT0_PRTENCHNG |
722 DWC2_HPRT0_PRTOVRCURRCHNG,
723 DWC2_HPRT0_PRTRST);
724 break;
725
726 case USB_PORT_FEAT_ENABLE:
727 break;
728 }
729 break;
730 case (USB_REQ_SET_ADDRESS << 8):
731 priv->root_hub_devnum = wValue;
732 break;
733 case (USB_REQ_SET_CONFIGURATION << 8):
734 break;
735 default:
736 puts("unsupported root hub command\n");
737 stat = USB_ST_STALLED;
738 }
739
740 len = min(len, txlen);
741
742 dev->act_len = len;
743 dev->status = stat;
744
745 return stat;
746 }
747
748 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
749 unsigned long pipe, void *buffer, int txlen,
750 struct devrequest *cmd)
751 {
752 int stat = 0;
753
754 if (usb_pipeint(pipe)) {
755 puts("Root-Hub submit IRQ: NOT implemented\n");
756 return 0;
757 }
758
759 if (cmd->requesttype & USB_DIR_IN)
760 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
761 else
762 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
763
764 mdelay(1);
765
766 return stat;
767 }
768
769 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
770 {
771 int ret;
772 uint32_t hcint, hctsiz;
773
774 ret = wait_for_bit(__func__, &hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
775 1000, false);
776 if (ret)
777 return ret;
778
779 hcint = readl(&hc_regs->hcint);
780 hctsiz = readl(&hc_regs->hctsiz);
781 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
782 DWC2_HCTSIZ_XFERSIZE_OFFSET;
783 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
784
785 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
786 *toggle);
787
788 if (hcint & DWC2_HCINT_XFERCOMP)
789 return 0;
790
791 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
792 return -EAGAIN;
793
794 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
795 return -EINVAL;
796 }
797
798 static int dwc2_eptype[] = {
799 DWC2_HCCHAR_EPTYPE_ISOC,
800 DWC2_HCCHAR_EPTYPE_INTR,
801 DWC2_HCCHAR_EPTYPE_CONTROL,
802 DWC2_HCCHAR_EPTYPE_BULK,
803 };
804
805 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
806 u8 *pid, int in, void *buffer, int num_packets,
807 int xfer_len, int *actual_len, int odd_frame)
808 {
809 int ret = 0;
810 uint32_t sub;
811
812 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
813 *pid, xfer_len, num_packets);
814
815 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
816 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
817 (*pid << DWC2_HCTSIZ_PID_OFFSET),
818 &hc_regs->hctsiz);
819
820 if (!in && xfer_len) {
821 memcpy(aligned_buffer, buffer, xfer_len);
822
823 flush_dcache_range((unsigned long)aligned_buffer,
824 (unsigned long)aligned_buffer +
825 roundup(xfer_len, ARCH_DMA_MINALIGN));
826 }
827
828 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
829
830 /* Clear old interrupt conditions for this host channel. */
831 writel(0x3fff, &hc_regs->hcint);
832
833 /* Set host channel enable after all other setup is complete. */
834 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
835 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
836 DWC2_HCCHAR_ODDFRM,
837 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
838 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
839 DWC2_HCCHAR_CHEN);
840
841 ret = wait_for_chhltd(hc_regs, &sub, pid);
842 if (ret < 0)
843 return ret;
844
845 if (in) {
846 xfer_len -= sub;
847
848 invalidate_dcache_range((unsigned long)aligned_buffer,
849 (unsigned long)aligned_buffer +
850 roundup(xfer_len, ARCH_DMA_MINALIGN));
851
852 memcpy(buffer, aligned_buffer, xfer_len);
853 }
854 *actual_len = xfer_len;
855
856 return ret;
857 }
858
859 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
860 unsigned long pipe, u8 *pid, int in, void *buffer, int len)
861 {
862 struct dwc2_core_regs *regs = priv->regs;
863 struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
864 struct dwc2_host_regs *host_regs = &regs->host_regs;
865 int devnum = usb_pipedevice(pipe);
866 int ep = usb_pipeendpoint(pipe);
867 int max = usb_maxpacket(dev, pipe);
868 int eptype = dwc2_eptype[usb_pipetype(pipe)];
869 int done = 0;
870 int ret = 0;
871 int do_split = 0;
872 int complete_split = 0;
873 uint32_t xfer_len;
874 uint32_t num_packets;
875 int stop_transfer = 0;
876 uint32_t max_xfer_len;
877 int ssplit_frame_num = 0;
878
879 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
880 in, len);
881
882 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
883 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
884 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
885 if (max_xfer_len > DWC2_DATA_BUF_SIZE)
886 max_xfer_len = DWC2_DATA_BUF_SIZE;
887
888 /* Make sure that max_xfer_len is a multiple of max packet size. */
889 num_packets = max_xfer_len / max;
890 max_xfer_len = num_packets * max;
891
892 /* Initialize channel */
893 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
894 eptype, max);
895
896 /* Check if the target is a FS/LS device behind a HS hub */
897 if (dev->speed != USB_SPEED_HIGH) {
898 uint8_t hub_addr;
899 uint8_t hub_port;
900 uint32_t hprt0 = readl(&regs->hprt0);
901 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
902 DWC2_HPRT0_PRTSPD_HIGH) {
903 usb_find_usb2_hub_address_port(dev, &hub_addr,
904 &hub_port);
905 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
906
907 do_split = 1;
908 num_packets = 1;
909 max_xfer_len = max;
910 }
911 }
912
913 do {
914 int actual_len = 0;
915 uint32_t hcint;
916 int odd_frame = 0;
917 xfer_len = len - done;
918
919 if (xfer_len > max_xfer_len)
920 xfer_len = max_xfer_len;
921 else if (xfer_len > max)
922 num_packets = (xfer_len + max - 1) / max;
923 else
924 num_packets = 1;
925
926 if (complete_split)
927 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
928 else if (do_split)
929 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
930
931 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
932 int uframe_num = readl(&host_regs->hfnum);
933 if (!(uframe_num & 0x1))
934 odd_frame = 1;
935 }
936
937 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
938 in, (char *)buffer + done, num_packets,
939 xfer_len, &actual_len, odd_frame);
940
941 hcint = readl(&hc_regs->hcint);
942 if (complete_split) {
943 stop_transfer = 0;
944 if (hcint & DWC2_HCINT_NYET) {
945 ret = 0;
946 int frame_num = DWC2_HFNUM_MAX_FRNUM &
947 readl(&host_regs->hfnum);
948 if (((frame_num - ssplit_frame_num) &
949 DWC2_HFNUM_MAX_FRNUM) > 4)
950 ret = -EAGAIN;
951 } else
952 complete_split = 0;
953 } else if (do_split) {
954 if (hcint & DWC2_HCINT_ACK) {
955 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
956 readl(&host_regs->hfnum);
957 ret = 0;
958 complete_split = 1;
959 }
960 }
961
962 if (ret)
963 break;
964
965 if (actual_len < xfer_len)
966 stop_transfer = 1;
967
968 done += actual_len;
969
970 /* Transactions are done when when either all data is transferred or
971 * there is a short transfer. In case of a SPLIT make sure the CSPLIT
972 * is executed.
973 */
974 } while (((done < len) && !stop_transfer) || complete_split);
975
976 writel(0, &hc_regs->hcintmsk);
977 writel(0xFFFFFFFF, &hc_regs->hcint);
978
979 dev->status = 0;
980 dev->act_len = done;
981
982 return ret;
983 }
984
985 /* U-Boot USB transmission interface */
986 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
987 unsigned long pipe, void *buffer, int len)
988 {
989 int devnum = usb_pipedevice(pipe);
990 int ep = usb_pipeendpoint(pipe);
991 u8* pid;
992
993 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
994 dev->status = 0;
995 return -EINVAL;
996 }
997
998 if (usb_pipein(pipe))
999 pid = &priv->in_data_toggle[devnum][ep];
1000 else
1001 pid = &priv->out_data_toggle[devnum][ep];
1002
1003 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
1004 }
1005
1006 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
1007 unsigned long pipe, void *buffer, int len,
1008 struct devrequest *setup)
1009 {
1010 int devnum = usb_pipedevice(pipe);
1011 int ret, act_len;
1012 u8 pid;
1013 /* For CONTROL endpoint pid should start with DATA1 */
1014 int status_direction;
1015
1016 if (devnum == priv->root_hub_devnum) {
1017 dev->status = 0;
1018 dev->speed = USB_SPEED_HIGH;
1019 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
1020 setup);
1021 }
1022
1023 /* SETUP stage */
1024 pid = DWC2_HC_PID_SETUP;
1025 do {
1026 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
1027 } while (ret == -EAGAIN);
1028 if (ret)
1029 return ret;
1030
1031 /* DATA stage */
1032 act_len = 0;
1033 if (buffer) {
1034 pid = DWC2_HC_PID_DATA1;
1035 do {
1036 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
1037 buffer, len);
1038 act_len += dev->act_len;
1039 buffer += dev->act_len;
1040 len -= dev->act_len;
1041 } while (ret == -EAGAIN);
1042 if (ret)
1043 return ret;
1044 status_direction = usb_pipeout(pipe);
1045 } else {
1046 /* No-data CONTROL always ends with an IN transaction */
1047 status_direction = 1;
1048 }
1049
1050 /* STATUS stage */
1051 pid = DWC2_HC_PID_DATA1;
1052 do {
1053 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1054 priv->status_buffer, 0);
1055 } while (ret == -EAGAIN);
1056 if (ret)
1057 return ret;
1058
1059 dev->act_len = act_len;
1060
1061 return 0;
1062 }
1063
1064 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1065 unsigned long pipe, void *buffer, int len, int interval)
1066 {
1067 unsigned long timeout;
1068 int ret;
1069
1070 /* FIXME: what is interval? */
1071
1072 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1073 for (;;) {
1074 if (get_timer(0) > timeout) {
1075 printf("Timeout poll on interrupt endpoint\n");
1076 return -ETIMEDOUT;
1077 }
1078 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1079 if (ret != -EAGAIN)
1080 return ret;
1081 }
1082 }
1083
1084 static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
1085 {
1086 struct dwc2_core_regs *regs = priv->regs;
1087 uint32_t snpsid;
1088 int i, j;
1089
1090 snpsid = readl(&regs->gsnpsid);
1091 printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
1092
1093 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1094 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1095 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
1096 return -ENODEV;
1097 }
1098
1099 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
1100 priv->ext_vbus = 1;
1101 #else
1102 priv->ext_vbus = 0;
1103 #endif
1104
1105 dwc_otg_core_init(priv);
1106 dwc_otg_core_host_init(dev, regs);
1107
1108 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1109 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1110 DWC2_HPRT0_PRTOVRCURRCHNG,
1111 DWC2_HPRT0_PRTRST);
1112 mdelay(50);
1113 clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1114 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1115 DWC2_HPRT0_PRTRST);
1116
1117 for (i = 0; i < MAX_DEVICE; i++) {
1118 for (j = 0; j < MAX_ENDPOINT; j++) {
1119 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1120 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1121 }
1122 }
1123
1124 /*
1125 * Add a 1 second delay here. This gives the host controller
1126 * a bit time before the comminucation with the USB devices
1127 * is started (the bus is scanned) and fixes the USB detection
1128 * problems with some problematic USB keys.
1129 */
1130 if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
1131 mdelay(1000);
1132
1133 return 0;
1134 }
1135
1136 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1137 {
1138 /* Put everything in reset. */
1139 clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1140 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1141 DWC2_HPRT0_PRTOVRCURRCHNG,
1142 DWC2_HPRT0_PRTRST);
1143 }
1144
1145 #ifndef CONFIG_DM_USB
1146 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1147 int len, struct devrequest *setup)
1148 {
1149 return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1150 }
1151
1152 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1153 int len)
1154 {
1155 return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1156 }
1157
1158 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1159 int len, int interval)
1160 {
1161 return _submit_int_msg(&local, dev, pipe, buffer, len, interval);
1162 }
1163
1164 /* U-Boot USB control interface */
1165 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1166 {
1167 struct dwc2_priv *priv = &local;
1168
1169 memset(priv, '\0', sizeof(*priv));
1170 priv->root_hub_devnum = 0;
1171 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1172 priv->aligned_buffer = aligned_buffer_addr;
1173 priv->status_buffer = status_buffer_addr;
1174
1175 /* board-dependant init */
1176 if (board_usb_init(index, USB_INIT_HOST))
1177 return -1;
1178
1179 return dwc2_init_common(NULL, priv);
1180 }
1181
1182 int usb_lowlevel_stop(int index)
1183 {
1184 dwc2_uninit_common(local.regs);
1185
1186 return 0;
1187 }
1188 #endif
1189
1190 #ifdef CONFIG_DM_USB
1191 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1192 unsigned long pipe, void *buffer, int length,
1193 struct devrequest *setup)
1194 {
1195 struct dwc2_priv *priv = dev_get_priv(dev);
1196
1197 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1198 dev->name, udev, udev->dev->name, udev->portnr);
1199
1200 return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1201 }
1202
1203 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1204 unsigned long pipe, void *buffer, int length)
1205 {
1206 struct dwc2_priv *priv = dev_get_priv(dev);
1207
1208 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1209
1210 return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1211 }
1212
1213 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1214 unsigned long pipe, void *buffer, int length,
1215 int interval)
1216 {
1217 struct dwc2_priv *priv = dev_get_priv(dev);
1218
1219 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1220
1221 return _submit_int_msg(priv, udev, pipe, buffer, length, interval);
1222 }
1223
1224 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1225 {
1226 struct dwc2_priv *priv = dev_get_priv(dev);
1227 const void *prop;
1228 fdt_addr_t addr;
1229
1230 addr = dev_get_addr(dev);
1231 if (addr == FDT_ADDR_T_NONE)
1232 return -EINVAL;
1233 priv->regs = (struct dwc2_core_regs *)addr;
1234
1235 prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
1236 "disable-over-current", NULL);
1237 if (prop)
1238 priv->oc_disable = true;
1239
1240 return 0;
1241 }
1242
1243 static int dwc2_usb_probe(struct udevice *dev)
1244 {
1245 struct dwc2_priv *priv = dev_get_priv(dev);
1246 struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
1247
1248 bus_priv->desc_before_addr = true;
1249
1250 return dwc2_init_common(dev, priv);
1251 }
1252
1253 static int dwc2_usb_remove(struct udevice *dev)
1254 {
1255 struct dwc2_priv *priv = dev_get_priv(dev);
1256
1257 dwc2_uninit_common(priv->regs);
1258
1259 return 0;
1260 }
1261
1262 struct dm_usb_ops dwc2_usb_ops = {
1263 .control = dwc2_submit_control_msg,
1264 .bulk = dwc2_submit_bulk_msg,
1265 .interrupt = dwc2_submit_int_msg,
1266 };
1267
1268 static const struct udevice_id dwc2_usb_ids[] = {
1269 { .compatible = "brcm,bcm2835-usb" },
1270 { .compatible = "snps,dwc2" },
1271 { }
1272 };
1273
1274 U_BOOT_DRIVER(usb_dwc2) = {
1275 .name = "dwc2_usb",
1276 .id = UCLASS_USB,
1277 .of_match = dwc2_usb_ids,
1278 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1279 .probe = dwc2_usb_probe,
1280 .remove = dwc2_usb_remove,
1281 .ops = &dwc2_usb_ops,
1282 .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1283 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1284 };
1285 #endif
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